Embodiments described herein relate generally to a semiconductor device and a method for manufacturing a semiconductor device.
In a memory cell transistor (hereinafter referred to as a memory cell) including a control gate electrode and a charge storage layer such as a floating gate electrode, a coupling ratio (CR) between the control gate electrode and the floating gate electrode is one of parameters characterizing a performance of a memory cell.
According to one embodiment, a semiconductor device includes a memory cell array including a first memory cell provided on a substrate and a second memory cell provided on the substrate. The memory cell array includes a charge storage layer provided on the substrate and a control electrode provided on the charge storage layer. A coupling ratio of the second memory cell is different from a coupling ratio of the first memory cell.
Embodiments will now be described with reference to the drawings. The same components in the drawings are marked with the same reference numerals. Although silicon is exemplified in the following embodiments as a semiconductor, a semiconductor other than silicon may be used.
The semiconductor memory device of the embodiment includes a memory cell array 1. The memory cell array 1 includes a plurality of semiconductor regions (active regions) 11 and a plurality of control gate electrodes 50. A planar layout of the semiconductor regions 11 and the control gate electrodes 50 is shown in
The semiconductor regions 11 extend in a Y-direction (first direction). The semiconductor regions 11 are separate from each other in a X-direction intersecting with the Y-direction. For example, the X-direction is substantively perpendicular to the Y-direction. The control gate electrodes 50 extend in the X-direction (second direction) different from the Y-direction. The control gate electrodes 50 are separate from each other in the Y-direction intersecting with the Y-direction. For example, the Y-direction is substantively perpendicular to the X-direction. The control gate electrodes 50 extend across the semiconductor regions 11 in the X-direction above the semiconductor regions 11.
A memory cell MC described below is provided at an intersection of the semiconductor region 11 and the control gate electrode 50. The memory cell array 1 includes a plurality of memory cells MC arrayed in the X-direction and the Y-direction.
As shown in
As shown in
A first insulating film (gate insulating film, tunneling insulating film) 20 is provided on the semiconductor region 11. The first insulating film 20 is, for example, a silicon oxide film. As shown in
A plurality of charge storage layers 30 is provided on the first insulating film 20. The charge storage layer 30 is a polysilicon film doped with, for example, phosphorus that is a dopant for a conductive polysilicon. The charge storage layer 30 may be a silicon film doped with phosphorus and carbon. The charge storage layer 30 may contain tungsten, titanium nitride, or tantalum nitride. As shown in
The second insulating film (interelectrode insulating film) 40 is provided on the charge storage layer 30. The second insulating film 40 is formed of a material having a dielectric constant higher than a dielectric constant of the first insulating film 20. The second insulating film 40 is provided on the upper surface of the charge storage layers 30. As shown in
The control gate electrode 50 is provided on the second insulating film 40. The control gate electrode 50 can be formed of the same material as the charge storage layer 30 that is the floating gate electrode. As shown in
As shown in
As shown in
The charge storage layer 30 is surrounded by the insulator, and is not electrically connected to anywhere. The electron stored in the charge storage layer 30 is not released from the charge storage layer 30 and the electron is not injected into the charge storage layer 30 even when the power supply is OFF. The semiconductor memory device (semiconductor device) of the embodiment is a nonvolatile semiconductor memory device that can retain the data without the power supply.
The charge storage layer 30 may have many trap sites that trap charge inside an insulative film. Such a charge storage layer 30 may include a silicon nitride film.
The control gate electrode 50 is provided on the upper surface of the charge storage layer 30 with the second insulating film 40 interposed. As shown in
The control gate electrode 50 faces to the upper surface and the side surface of the charge storage layer 30 with the second insulating film 40 interposed. The control gate electrode 50 faces to the upper surface of the charge storage layer 30, and faces to also the side surface of the charge storage layer 30. This increase an opposing area of the control gate electrode 50 and the charge storage layer 30, and increase a capacitance between the control gate electrode 50 and the charge storage layer 30. The strong capacitance coupling between the control gate electrode 50 and the charge storage layer 30 enhances the write efficiency and the erase efficiency.
As shown in
The memory cell array 1 of the embodiment includes, as shown in
According to the embodiment, a coupling ratio (first coupling ratio) of the first memory cell MCa is different from a coupling ratio (second coupling ratio) of the second memory cell MCb.
The coupling ratio CR is represented by the first capacitance Ctnl between the semiconductor region 11 and the charge storage layer 30, and the second capacitance Cipd between the charge storage layer 30 and the control gate electrode 50. For example, the coupling ratio CR is the ratio of the second capacitance Cipd to the capacitance (Ctnl+Cipd) viewed from the charge storage layer 30. The coupling ratio CR is calculated by the following equation (1).
CR=Cipd/(Ctnl+Cipd) (1)
In the embodiment, the coupling ratio of the first memory cell MCa is different from the coupling ratio of the second memory cell MCb by changing the dielectric constant of the material of the second insulating film 40a of the first memory cell MCa and the dielectric constant of the material of the second insulating film 40b of the second memory cell MCb. For example, the material of the second insulating film 40b of the second memory cell MCb contains a major element different from a major element contained in the material of the second insulating film 40a of the first memory cell MCa.
For example, the high-k material such as hafnium oxide (HfO2) is used as the second insulating film 40a of the first memory cell MCa. The second insulating film 40a may be, for example, a silicon nitride film, or an insulating film containing hafnium aluminate.
When the material of the second insulating film 40a of the first memory cell MCa is hafnium oxide, for example, hafnium silicate (HfSiO), or hafnium oxide doped with silicon is used as the material of the second insulating film 40b of the second memory cell MCb.
When the material of the second insulating film 40a of the first memory cell MCa is silicon oxynitride, for example, aluminum silicate containing nitrogen, or silicon oxynitride doped with aluminum is used as the material of the second insulating film 40b of the second memory cell MCb.
When the material of the second insulating film 40a of the first memory cell MCa is an insulating film containing hafnium aluminate, for example, an insulating film containing hafnium aluminate having an aluminum concentration higher than an aluminum concentration in the second insulating film 40a of the first memory cell MCa is used as the material of the second insulating film 40b of the second memory cell MCb.
The second insulating film 40a of the first memory cell MCa is not limited to the above example. The insulating material having changeable dielectric constant by doping an element not contained in the second insulating film 40a or an element not major element of the second insulating film 40a is used as the material of the second insulating film 40a.
The material having the changed dielectric constant is used as the material of the second insulating film 40b of the second memory cell MCb.
The change of the dielectric constant of the second insulating film 40 between the charge storage layer 30 and the control gate electrode 50 changes the second capacitance Cipd between the charge storage layer 30 and the control gate electrode 50. According to the above equation (1), the coupling ratio CR of the first memory cell MCa can be different from the coupling ratio CR of the second memory cell MCb.
According to the embodiment, the first memory cell MCa and the second memory cell MCb having the coupling ratio CR different from the coupling ratio CR of the first memory cell MCa are formed on the same substrate 10. The first memory cell MCa and the second memory cell MCb having the coupling ratio CR different from the coupling ratio CR of the first memory cell MCa are included in one chip.
The number of the first memory cell MCa and the second memory cell MCb, the arrangement of the first memory cell MCa and the second memory cell MCb on the substrate 10 are arbitrarily configured.
The coupling ratio CR defines the voltage Vfg applied to the charge storage layer 30 by the control gate electrode 50 to which the voltage Vcg is applied. The higher coupling ratio CR increases the write efficiency and the erase efficiency of the data to the memory cell MC. The coupling ratio CR is one of the parameters characterizing the performance of the memory cell MC. According to the embodiment, the memory cell MCa and the memory cell MCb having different characteristics each other are provided on one substrate 10 or in one chip.
Next, a method for manufacturing the semiconductor memory device of the embodiment will now be described.
First, the first insulating film 20 is formed on the substrate 10. And then a first polysilicon film 31 is formed on the insulating film 20.
The first polysilicon film 31 and the insulating film 20 are etched in series by RIE method using a mask not shown. The first polysilicon film 31 and the insulating film 20 are divided in the X-direction. And then the exposed region of the substrate 10 is etched to form a trench. The fin-shaped semiconductor region 11 is formed between the adjacent the trenches in the X-direction.
The insulating film, for example, the silicon oxide film is buried in the trench and the separation portion 60 is formed.
The second polysilicon film 32 is deposited on the first polysilicon film 31 and the separation portion 60. The first polysilicon film 31 and the second polysilicon film 32 are included in the charge storage layer 30.
And then the second polysilicon film 32 on the separation portion 60 is selectively removed, for example, by RIE method using a mask not shown. The plurality of second polysilicon films 32 are separated in the X-direction with the trench 61 interposed between the second polysilicon films 32.
Next, as shown in
For example, the hafnium oxide (HfO2) film is formed as the second insulating film 40 by atomic layer deposition (ALD) method.
After depositing the second insulating film 40, the dielectric constant of the area of the part of the second insulating film 40 is changed. Here, the dielectric constant of the second insulating film 40 in the area corresponding to the second memory cell MCb is changed. According to the embodiment, the dielectric constant of the second insulating film 40 of the second memory cell MCb is changed by implanting silicon (si) selectively into the second insulating film 40 of the second memory cell MCb. The silicon is implanted by ion implantation method. As shown in
After depositing the material film of the mask M1 on the second insulating film 40, the predetermined opening pattern is formed in the material film. The mask M1 is, for example, a resist film itself, or a film patterned using a resist film. Here, the opening portion MO is formed in the area corresponding to the second memory cell MCb.
The silicon is implanted into the second insulating film 40 exposed in the opening portion MO by ion implantation method. The dose amount of the silicon is, for example, 1×1014 to 1×1016 atom/cm2.
The silicon is not implanted into the second insulating film 40 of the area covered with the mask M1. The second insulating film 40 of the area doped with the silicon becomes a hafnium silicate film. The dielectric constant of the hafnium silicate film is lower than the dielectric constant of the second insulating film 40 (hafnium oxide film) of the area not doped with the silicon. Or, the second insulating film 40 of the area doped with the silicon contains silicon at a higher concentration than the second insulating film 40 of the area not doped with the silicon, and have a dielectric constant lower than that of the second insulating film 40 of the area not doped with the silicon. After implanting the silicon, the mask M1 is removed.
After removing the mask M1, as shown in
First, a polysilicon film 51 is formed. As shown in
As shown in
Next, an n-type impurity ion is implanted into the surface of the semiconductor region 11 through the gate insulating film 20 exposed in the cell separating trench. The n-type impurity ion implanted into the surface of the semiconductor region 11 is, for example, arsenic ion or phosphorus ion. The interlayer insulating film 70 is formed in the cell separating trench by plasma CVD method. And then a contact (not shown) connected to the semiconductor region 12 is formed in the interlayer insulating film 70.
In the above embodiment, after forming the second insulating film 40, before forming the control gate electrode 50, the ion is selectively implanted into the second insulating film 40. However, the method for manufacturing the semiconductor memory device of the embodiment is not limited to the above method. For example, after forming the polysilicon film 51 of the control gate electrode 50, before forming the metal silicide film 52, the silicon ion may be implanted into the second insulating film 40 through the polysilicon film 51.
Also in this instance, as shown in
The memory cell array 1 including the plurality of memory cells MC may have three or more different coupling ratios.
The three or more different coupling ratios are configured by three or more different materials of the second insulating film 40. This is achieved, for example, by the difference of the dose amount of the silicon ion into the second insulating film 40. For example, as shown in
For example, after the first ion implantation of the silicon using the mask M1 shown in
The similar method described above is applicable to the second insulating film 40 having a material containing aluminum oxide.
As described above, according to the method for manufacturing the semiconductor memory device of the embodiment, the memory cells MC including the second insulating film 40 having different dielectric constant can be formed on one substrate 10 by only the additional ion implantation step with the mask. The memory cells MC including the second insulating film 40 having different dielectric constant have different coupling ratio CR and different characteristics. Therefore, according to the method for manufacturing the semiconductor memory device of the embodiment, the memory cells MC having different performance can be obtained on one substrate 10 without changing the size of the memory cells MC (height or width of the charge storage layer 30). According to the embodiment, the dielectric constant of the second insulating film 40 can be changed by the ion implantation or not. This makes it possible to obtain the memory cells MC having different performance on one substrate 10 at low cost.
It is not limited to determining the coupling ratio for each memory cell MC in the memory cell array 1. As shown in
A plurality of memory cell arrays 1 may be formed in one chip, and the coupling ratio may be determined for the memory cell array 1. That is, the one-chip semiconductor memory device (memory chip) includes a first memory cell array including the plurality of first memory cells MCa and not including the second memory cell MCb, a second memory cell array including the plurality of second memory cells MCb and not including the first memory cell MCa.
As described above, the coupling ratio CR is determined according to the equation (1). As shown the following equation (2), the coupling ratio CR is a coefficient for calculating a voltage Vfg applied to the charge storage layer 30 from a voltage Vcg applied to the control gate electrode 50.
Vfg=CR·Vcg (2)
The voltage Vcg (control voltage) applied to the memory cell MC at writing and erasing is different depending on the coupling ratio CR of the memory cell MC. The memory cell having a higher coupling ratio CR may have a lower control voltage. The control voltage Vcgh of the second memory cell MCb having lower coupling ratio CR is higher than the control voltage Vcgl of the first memory cell MCa having higher coupling ratio CR.
If the same writing voltage Vcg is applied to the second memory cell MCb as the writing voltage Vcg of the first memory cell MCa, charge may not be injected to the charge storage layer 30 of the second memory cell MCb. That is, data may not be written to the second memory cell MCb. If the same erasing voltage Vcg is applied to the second memory cell MCb as the erasing voltage Vcg of the first memory cell MCa, charge may not be released from the charge storage layer 30 of the second memory cell MCb. That is, data may not be erased from the second memory cell MCb. According to the semiconductor device of the embodiment, the CR difference can determine 0/1 of the first memory cell MCa and the second memory cell MCb in one operating voltage by properly setting the voltage Vcg.
The area RGh including the first memory cell MCa can be used as a rewritable memory area and the area RGI including the second memory cell MCb can be used as a non-rewritable read only memory (ROM) area with the control voltage lower than the above Vcgh and being equal to the above Vcgl or higher than the above Vcgl. Before shipment of the product, data can be written to the second memory cell MCb with the control voltage being equal to the Vcgh or higher than the Vcgh. According to the semiconductor memory device of the embodiment, different two kinds of memory areas can be formed in one chip (on one substrate 10) without complex manufacturing process and changing the memory size.
Further, according to the semiconductor memory device of the embodiment, the data stored in the area RGI used as the ROM area can be rewritten only by changing the control voltage to the Vcgh. It is required to make a photomask when changing the stored data in the general ROM mask. In the embodiment, the stored data can be rewritten with the control voltage. This reduces costs of development and manufacturing.
Further, according to embodiment, writing/eracing characteristics can be changed for each memory cell MC. This allows the use as ROM storing data with inhibiting the writing to the predetermined area or entire area.
In that case, data may be programmed depending on the ion implantation or not with a mask M1 made according to the user's ROM code. That is, “0” or “1” is determined depending on the ion implantation or not. As shown in
The semiconductor device is, for example, a micro controller unit (MCU) 8. The MCU 8 includes a memory portion 81, a memory portion 82, a logic circuit portion 83, a digital-analog converter (DAC) portion 84, an analog-digital converter (ADC) portion 85, and a peripheral circuit portion 86.
The memory portion 81, the memory portion 82, the logic circuit portion 83, the digital-analog converter (DAC) portion 84, the analog-digital converter (ADC) portion 85, and the peripheral circuit portion 86 are formed on the same substrate with one-chipped structure. Or the memory portion 81, the memory portion 82, the logic circuit portion 83, the digital-analog converter (DAC) portion 84, the analog-digital converter (ADC) portion 85, and the peripheral circuit portion 86 are formed as separate chips. These chips are mounted on an interposer with one-packaged structure.
The memory portion 81 corresponds to the above semiconductor memory device of the embodiment, and includes a data storage area 81d and a code storage area 81c.
The coupling ratio of the memory cell MC included in the data storage area 81d may be different from the coupling ratio of the memory cell MC included in the code storage area 81c. For example, the data storage area 81d may be made up of the first memory cell MCa, and the code storage area 81c may be made up of the second memory cell MCb.
In that case, in the same manner as the above embodiment, the dielectric constant of the second insulating film 40 may be change by the ion implantation in the manufacturing process of the memory portion 81. The coupling ratio of the memory cell MC included in the data storage area 81d may be different from the coupling ratio of the memory cell MC included in the code storage area 81c by the change of the dielectric constant of the second insulating film 40.
For example, a program executed by the logic circuit portion 83 is stored in the code storage area 81c. For example, a data controlled by the logic circuit portion 83 is stored in the data storage area 81d. The motor, the electronic device, the vehicle and others are controlled by the logic circuit portion 83.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
This application is a division of U.S. patent application Ser. No. 15/372,190, filed on Dec. 7, 2016, which is based upon and claims the benefit of priority from U.S. Provisional Patent Application 62/304,730, filed on Mar. 7, 2016, the entire contents of each of which are incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
62304730 | Mar 2016 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 15372190 | Dec 2016 | US |
Child | 16587764 | US |