Patent Application
20110291203
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2010-124295 filed in Japan on May 31, 2010; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device having a field plate and a method for manufacturing the same.
In a semiconductor device such as a transistor having a conventional field plate, a drain electrode, a gate electrode, and a source electrode are formed on a semiconductor substrate, and, furthermore, a source field plate is formed between the drain electrode and the source electrode over a passivation layer with appropriate thickness. The source field plate is extended to a drain electrode side over the gate electrode through the passivation layer. Herein, a drain side end of the source field plate exists between the gate electrode and the drain electrode. The source field plate is electrically connected to a source electrode. The connection width is substantially equal to a width of electrodes (a length in a direction perpendicular to a direction of a current flow) of the source electrode and the source field plate.
By reducing the electric field concentration of the drain side edge of the gate electrode, the source field plate enables to improve break down voltages. Therefore, a higher output power is available with a semiconductor device having a source field plate.
In such a conventional semiconductor device as a transistor having the source field plate, wide electrodes are formed on a gate electrode through a passivation layer. Since the electrode is formed in contact with the passivation layer, a capacitance is generated between the gate electrode and the source field plate. Therefore, a gate parasitic capacitance Cgs between the gate electrode and the source electrode increases. When the gate parasitic capacitance Cgs increases as described above, the characteristics of the semiconductor device, for example, a gain of the semiconductor device is deteriorated.
A semiconductor device according to an embodiment of the present invention includes a active region, a drain electrode, a source electrode, a gate electrode, a passivation layer and a source field plate. The active region is formed on a semiconductor substrate. The drain electrode and the source electrode are formed on a surface of the active region with a space. The gate electrode is formed between the drain electrode and the source electrode. The passivation layer is formed on a surface of the active region. The source field plate is formed on the passivation layer. The drain side of the source field plate is extended over the gate electrode to drain side. Here, the drain side end of the source field plate exists between the gate electrode and the drain electrode. The electrical connection is formed on the passivation layer to connect the source field plate and the source electrode. The connection has same width as the source field plate and the source electrode.
A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a drain electrode, a source electrode, and a gate electrode on a surface of a active region formed on a semiconductor substrate, forming a passivation layer, forming a first photo resist layer, and forming a source field plate and a electrical connection. In the step of forming a passivation layer, a passivation layer is formed on the active region to cover the gate electrode. In the step of forming a first photo resist layer, a first photo resist layer is formed on the passivation layer having electrode with openings formed at least over an upper portion of a drain-side end portion of the gate electrode and over the source electrode and a electrical connection with openings formed between the electrode to connect the openings and having an opening width smaller than that of the electrode. In the step of forming a source field plate and a electrical connection, the first photo resist layer is removed to form a source field plate and a electrical connection electrically connecting the source field plate and the source electrode and having a electrical connection width smaller than electrode widths of the electrodes after a metal is deposited by using the first photo resist layer as a mask.
The semiconductor device and a method for manufacturing a semiconductor device will be described below with reference to the accompanying drawings.
On the active region 12, a drain electrode 13 and a source electrode 14 are formed with a space between them. On the active region 12 between the drain electrode 13 and the source electrode 14, a gate electrode 15 is formed. The drain electrode 13 and the source electrode 14 consist of a material which is in ohmic contact with, for example, the active region 12, and the gate electrode 15 consists of a material forming a Schottky-barrier-junction, for example, with the active region 12.
On the active region 12, a gate field plate 16 is formed through a passivation layer 19, which will be described later. The gate field plate 16 is connected to a drain-side end portion of the gate electrode 15. The gate field plate 16 consists of the same material as that of the gate electrode 15.
The gate field plate 16 enables to prevent the electric field concentration at the drain-side end portion of the gate electrode 15 and thereby improving a break down voltage of the semiconductor device. Therefore, although the semiconductor device according to the embodiment preferably has the gate field plate 16, the gate field plate 16 is not always necessary.
On a surface of the drain electrode 13, a drain connect electrode 17 is formed. On a surface of the source electrode 14, a source connect electrode 18 is formed. The connect electrodes 17 and 18 consist of a material such as gold.
The passivation layer 19 is formed on the active region 12 between the drain electrode 13 and the source electrode 14 to cover the gate electrode 15 and the gate field plate 16. The passivation layer 19 consists of, for example, SiN. However, the passivation layer 19 may consist of SiO2 or the like.
A source field plate 20 is formed on the passivation layer 19 between the source electrode 14 and the drain electrode 13 so as to cover the gate electrode 15. The source field plate 20 consists of a material such as gold.
The source field plate 20 is formed such that at least a source-side end portion 20-1 of the electrode 20 is located at a position closer to the source electrode than the drain-side end portion 16-1 of gate field plate 16. More specifically, the source field plate 20 is formed at a position covering the drain-side end portion of the gate field plate 16. When the source field plate 20 is formed at the position, the drain-side end portion of the gate field plate 16 is prevented from the electric field concentration. Therefore, the breakdown voltage of the semiconductor device is improved.
When the gate field plate 16 is not formed, the source field plate 20 is formed such that at least the source-side end portion 20-1 of the electrode 20 is located at a position closer to the source electrode than the drain-side end portion 15-1 of the gate electrode 15. Accordingly, the drain-side end portion 15-1 of the gate electrode 15 is prevented from being a high potential due to concentration of an electric field, and thus the break down voltage of the semiconductor device is improved.
The source field plate 20 and the source connect electrode 18 are connected to each other by a plurality of parallel linear thin electrical connections 21, as shown in
The method for manufacturing a semiconductor device stated above will be described below with reference to
As shown in
As shown in
The electrode forming openings 22a are formed at least above the drain-side end portion of the gate field plate 16, the drain electrode 13, and the source electrode 14, respectively. The plurality of electrical connection forming openings 22b are formed between the electrode forming openings 22a, 22a over the source electrode 14 and the gate field plate 16 to connect the openings 22a, 22a to each other. A width of the each opening of the electrical connection forming openings 22b is smaller than the width of the each opening of the electrode forming opening 22a. The width of the opening means a length of an opening in the same direction as those of the electrode width and the electrical connection width.
The first photo resist layer 22 is formed in the following manner. For example, a first photo resist material is coated on the entire surface of the device as a photosensitive organic film. Thereafter, a second photo resist material is coated on the entire surface of the first photo resist material having a mask pattern which exposes portions for forming the openings 22a and 22b. The first photo resist material is removed by reactive dry etching or chemical dry etching by using the second photo resist mask pattern. Finally, the second photo resist pattern is removed to form the first photo resist layer 22. In place of the first photo resist layer 22, an SiN film may be formed in the same method as described above. The formation of the opening in this case may be performed by removing unnecessary portions of the SiN film by chemical dry etching.
As shown in
Finally, the first photo resist layer 22 is removed together with the metal 23 on the layer 22. In this manner, the semiconductor device shown in
The semiconductor device according to the embodiment described above, the electrical connection width of each of the electrical connections 21 is smaller than a electrical connection width of a conventional electrical connection. The capacitances between the gate electrode 15 and the plurality of electrical connections 21 are reduced compared with the conventional semiconductor device. Therefore, a gate parasitic capacitance Cgs between the gate electrode 15 and the source electrode 14 can be reduced. In this manner, characteristics such as the gain of amplification of the semiconductor device can be improved.
A method for manufacturing the semiconductor device shown in
As in the method for manufacturing a semiconductor device according to the first embodiment, more specifically, as in
The second photo resist layer 26 is a resist layer for forming a plurality of electrical connections 24 over the passivation layer 19 via a desired space 25. The second photo resist layer 26 has a width equal to the electrode widths of the source electrode 14 and the gate field plate 16. The second photo resist layer 26 is formed on the passivation layer 19 extending from an upper part of the drain-side end portion of the source electrode 14 to an upper part of the drain-side end portion of the gate field plate 16. The second photo resist layer 26, like the first photo resist layer 22, may be made by SiN layer.
The second photo resist layer 26 is manufactured by the same method as that of the first photo resist layer 22 except that a position for forming the second photo resist layer 26 is different from a position for forming the first photo resist layer 22.
As shown in
Finally, the first photo resist layer 22 is removed together with the metal 23 on the layer 22. Subsequently, the second photo resist layer 26 is removed. In particular, the second photo resist layer 26 is desolved and removed by wet etching such that the second photo resist layer 26 is dipped in a chemical solution, or is removed by dry etching. In this method, the semiconductor device shown in
Even in the semiconductor device according to the second embodiment described above, a width of each of the electrical connections 24 is smaller than a width of a conventional electrical connection. Therefore, like the semiconductor device according to the first embodiment, the gate parasitic capacitance Cgs can be reduced, and the electric field concentration can be stably preventing along the entire width of the gate field plate 16.
Even in the semiconductor device according to the embodiment, like the semiconductor device according to the first embodiment, the number of thin electrical connections 24 is preferably small (for example, one) in terms of a reduction of the gate parasitic capacitance Cgs. However, since a stable voltage is difficult to be applied to the source field plate 20, a plurality of source field plate 20 is preferably formed.
In the semiconductor device according to the second embodiment, the plurality of electrical connections 24 are formed at an upper position spaced from the passivation layer. Therefore, the gate parasitic capacitance Cgs can be further reduced.
In the step of removing the second photo resist layer 26 in the second embodiment, the second photo resist layer 26 is exposed from portions between the pluralities of electrical connections 24. Therefore, the chemical solution to remove the second photo resist layer 26, reactive ions, an etching gas and the like penetrate from the exposed portions between the plurality of electrical connections 24 and a side surface of the second photo resist layer 26 into the entire area of the second photo resist layer 26. Therefore, the second photo resist layer 26 can be easily removed.
The method for manufacturing a semiconductor device will be described below with reference to
The drain electrode 13, the source electrode 14, the gate electrode 15, the gate field plate 16, the passivation layer 19 and the like are formed in the same manner as that shown in
The first photo resist layer 31 has electrode forming openings 31a for forming the drain connect electrode 17, the source connect electrode 18 and the source field plate 20 and a electrical connection forming opening 31b for forming the electrical connection 30, as shown in
The electrode forming openings 31a are formed at least above the drain-side end portion of the gate field plate 16, the drain electrode 13 and the source electrode 14, respectively. The electrical connection forming opening 31b is formed between the electrode forming openings 31a above the source electrode 14 and the gate field plate 16 to connect the openings 31a to each other. An opening width of each of the electrical connection forming openings 31b is substantially equal to an opening width of the electrode forming opening 31a.
The first photo resist layer 31 is manufactured by the same manner as the first photo resist layer 22 shown in
After the first photo resist layer 31 and the second photo resist layer 26 are formed, as in the method shown in
Finally, the first photo resist Layer 31 is removed together with the metal 23 on the layer 31. Subsequently, as in the second embodiment, the second photo resist layer 26 is removed by wet etching or dry etching. The second photo resist layer 26 can be removed although a longer time than those in the first and second embodiments is required to cause a wet etching solution or a dry etching gas to permeate in a lower side of the electrical connection 30 because the electrical connection 30 is wide. In order to shorten the time, a resist material having a high etching rate is used, or an insulating film such as SiO2 which can be easily etched may be used in place of the resist material. In this method, the semiconductor device shown in
In the semiconductor device according to the third embodiment described above, a width of the electrical connection 30 is substantially equal to that of a electrical connection of a conventional semiconductor device. However, the electrical connection 30 according to the third embodiment is formed at a position vertically spaced from the passivation layer. Therefore, the gate parasitic capacitance Cgs can be reduced.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel semiconductor device and the novel method for manufacturing a semiconductor device described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the semiconductor device and the method for manufacturing a semiconductor device described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
For example, the semiconductor device according to each of the embodiments described above is a single semiconductor device. However, each of the embodiments can be similarly applied to a structure obtained by arranging and forming a plurality of semiconductor devices in parallel to each other. In this case, in particular, the electrical connections 21, 24, and 30 are formed between the source connect electrode 18 and the source field plate 20 with shortest distances. Therefore, a nonuniform operation of each of the semiconductor devices caused by small differences between the plurality of electrical connections 21, 24, and 30 is also prevented.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-124295 | May 2010 | JP | national |
