BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view of a major part illustrating the structure of a semiconductor device according to an embodiment of the present invention.
FIG. 2A is a sectional view of a major part illustrating the structure of the semiconductor device according to the embodiment of the present invention and FIG. 2B is a sectional view of a major part illustrating a modification of the structure of the semiconductor device according to the embodiment of the present invention, both of which taken along the line IIa-IIa shown in FIG. 1.
FIGS. 3A and 3B are plan views of a major part illustrating the modification of the structure of the semiconductor device according to the embodiment of the present invention.
FIGS. 4A to 4C are sectional views of a major part illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention.
FIGS. 5A to 5C are sectional views of a major part illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.
FIGS. 6A and 6B are a plan view and a sectional view of a major part illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.
FIGS. 7A to 7C are sectional views of a major part illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.
FIGS. 8A to 8C are sectional views of a major part illustrating a method for manufacturing a conventional semiconductor device.
FIGS. 9A and 9B are sectional views of a major part illustrating the method for manufacturing the conventional semiconductor device.
FIG. 10 is a sectional view of a major part illustrating a general structure of the conventional semiconductor device.
FIGS. 11A and 11B are sectional views of a major part illustrating the structure of a semiconductor device to explain the problem to be solved by the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, explanation of a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention is provided with reference to the drawings.
First, the structure of the semiconductor device according to the embodiment of the present invention is described below.
FIG. 1 is a plan view of a major part illustrating the structure of the semiconductor device according to the embodiment of the present invention.
As shown in FIG. 1, active regions 3T1 and 3T2 having p-wells (not shown) and an isolation region 2 surrounding the active regions 3T1 and 3T2 are formed in the main surface of a silicon semiconductor substrate 1. The isolation region 2 may be formed by a shallow trench isolation technique. N-type source/drain regions 3a are formed in upper portions of the active region 3T1 (a second active region) and the active region 3T2 (a first active region). A dummy active region (a first dummy active region) 4 having a p-well (not shown) is also formed in the main surface of the semiconductor substrate 1 and surrounded by the isolation region 2. The dummy active region 4 is opposed to the active region 3T2 with the isolation region 2 interposed therebetween to have a distance S from the active region 3T2 (part of the isolation region 2 between the active region 3T2 and the dummy active region 4 corresponds to a first isolation region). The distance S between the active region 3T2 and the dummy active region 4 is smaller than the double of the thickness of a silicon gate material film for forming a fully silicided gate electrode 5 to be described later. This configuration makes it possible to prevent a recess from generating in the silicon gate material film deposited on the isolation region 2 between the active region 3T2 and the dummy active region 4.
A fully silicided gate electrode 5 is formed on the semiconductor substrate 1 to cross the active regions 3T1 and 3T2 and the dummy active region 4 which are formed in the semiconductor substrate 1 and divided from each other by the isolation region 2. The fully silicided gate electrode 5 is made of silicide obtained by reaction between the silicon gate material film and metallic material (detailed later). Sidewall spacers 6 made of a silicon nitride film are formed on both sides of the fully silicided gate electrode 5. Thus, a first FET 7 having a small gate width is formed on the active region 3T1 whose dimension in the gate width direction is small, while a second FET 8 having a larger gate width than the first FET 7 is formed on the active region 3T2 whose dimension in the gate width direction is larger than the active region 3T1.
It is preferable that the dummy active region 4 is arranged to at least partially intersect with the fully silicided gate electrode 5. More specifically, dimension x of the dummy active region 4 in the gate width direction is preferably not smaller than the minimum dimension as the active region and dimension y of the dummy active region 4 in the gate length direction is preferably not smaller than the sum of the gate length of the fully silicided gate electrode 5 and an allowance for misalignment with the fully silicided gate electrode 5. It is preferable to form the dummy active region 4 in the minimum size within the above-described range because if the dummy active region 4 becomes large, capacitance value of the fully silicided gate electrode 5 and wires (not shown) with respect to the semiconductor substrate 1 increases and the performance of the semiconductor device may deteriorate.
As shown in FIG. 2A, which is a sectional view of a major part taken along the line IIa-IIa of FIG. 1 for illustrating the structure of the semiconductor device according to the embodiment of the invention, a HfO2 gate insulating film 9 is formed on the active regions 3T1 and 3T2 and the dummy active region 4 which are formed in the semiconductor substrate 1 and defined by the isolation region 2. The top surface of the isolation region 2 is lower than the top surfaces of the active regions 3T1 and 3T2 and the dummy active region 4 (the top surface of the semiconductor substrate 1). The fully silicided gate electrode 5 is formed on the isolation region 2 and the gate insulating film 9 to cross the active regions 3T1 and 3T2 and the dummy active region 4 divided from each other by the isolation region 2 (part of the isolation region 2 between the active regions 3T1 and 3T2 corresponds to a second isolation region).
FIG. 2A shows the structure in which the fully silicided gate electrode 5 is formed through a complete reaction between the silicon gate material film and metallic material. This structure reduces wiring resistance and therefore contributes to improvement in performance of the device. However, as shown in FIG. 2B, it may be possible that unreacted portions of the silicon gate material film 10 remain on the isolation region 2 due to insufficient reaction between the silicon gate material film and the metallic material. More specifically, since the FETs are not formed on the isolation region 2, silicide obtained on the isolation region 2 may have different composition from that of the silicide forming the fully silicided gate electrode 5 on the active regions 3T1 and 3T2. In fact, the remaining of the silicon gate material film 10 reduces the capacitance value of the fully silicided gate electrode 5 with respect to the semiconductor substrate 1, which contributes to the improvement in performance of the semiconductor device.
In the thus-configured semiconductor device according to the embodiment of the present invention, the top surface of the isolation region 2 is lower than the top surfaces of the active regions 3T1 and 3T2 and the dummy active region 4 and the dummy active region 4 is arranged to have a distance S from the active region 3T2. As a result, on the isolation region 2 whose top surface is lower than the fop surfaces of the active regions 3T1 and 3T2, the silicon gate material film is deposited without generating a recess that hinders the silicidation in the top surface thereof. Further, on the active regions 3T1 and 3T2 where the first and second FETs 7 and 8 are formed, the silicon gate material film is deposited with uniform thickness. Therefore, irrespective of the two-dimensional sizes of the active regions 3T1 and 3T2, i.e., regardless of the gate width of the fully silicided gate electrode 5, the fully silicided gate electrode 5 is provided with uniform composition. Thus, the FETs are obtained with reduced variations in threshold value.
—Modification—
FIGS. 3A and 3B are plan views of a major part illustrating a modification of the structure of the semiconductor device according to the embodiment of the present invention.
The modified structure shown in FIGS. 3A and 3B is the same as that shown in FIG. 1 except that the location of the dummy active region 4 is different from that shown in FIG. 1.
As shown in FIG. 3A, a dummy active region 4a is formed opposite the active region 3T2 with the isolation region 2 interposed therebetween to have a distance SI from the active region 3T2. Further, a dummy active region 4b (a second dummy active region) is formed opposite the active region 3T1 with the isolation region 2 interposed therebetween to have a distance S2 from the active region 3T1. With this configuration, the effect of the dummy active region 4a opposed to the active region 3T2 is also obtained by the dummy active region 4b opposed to the active region 3T1. In FIG. 3A, the dimension y of the dummy active regions 4a and 4b in the gate length direction is depicted as the same as the dimension of the active regions 3T1 and 3T2 in the gate length direction. However, the dimensions x and y of the dummy active regions 4a and 4b are not particularly limited as long as they are within the range described above.
In order to obtain the same effect achieved by the provision of the dummy active regions 4a and 4b opposed to the active regions 3T2 and 3T1, respectively, a dummy active region 4c may be provided around the periphery of the isolation region 2 while keeping the distances S1 and S2 from the active regions 3T2 and 3T1 in the gate width direction, respectively. The location of the dummy active region 4 is not limited to the above and it may be arranged anywhere as long as the distances S1 and S2 from the active regions 3T2 and 3T1 in the gate width direction, the dimension x of the dummy active region 4 in the gate width direction and the dimension y of the dummy active region 4 in the gate length direction are within the suitable range.
Hereinafter, a method for manufacturing the semiconductor device according to the embodiment of the present invention is explained.
FIGS. 4A to 4C, 5A to 5C, 6A and 6B and 7A to 7C are sectional or plan views for illustrating the manufacturing method according to the embodiment of the present invention step by step. FIGS. 4A to 4C, 5A to 5C and 7A to 7C are sectional views taken along the line IIa-IIa of FIG. 1. FIG. 6A is a plan view and FIG. 6B is a sectional view taken along the line VIb-VIb shown in FIG. 6A.
First, as shown in FIG. 4A, p-wells (not shown) are formed in a silicon semiconductor substrate 1 by ion implantation and a protective oxide film 11 and a nitride film 12 are formed in this order on the semiconductor substrate 101.
Then, a resist 13 for defining active regions 3T1 and 3T2 and a dummy active region 4 to be described later is formed and the nitride film 12 and the protective oxide film 11 are etched using the resist 13 as a mask. Further, the semiconductor substrate 1 is also etched down to a predetermined depth to form an isolation groove 1A as shown in FIG. 4B. The isolation groove 1A defines the active regions 3T1 and 3T2 and the dummy active region 4. It is preferable that the dummy active region 4 is arranged to at least partially intersect with a fully silicided gate electrode 5 described later. More specifically, dimension x of the dummy active region 4 in the gate width direction is preferably not smaller than the minimum dimension as the active region and dimension y of the dummy active region 4 in the gate length direction is preferably not smaller than the sum of the gate length of the fully silicided gate electrode 5 and an allowance for misalignment with the fully silicided gate electrode 5. It is preferable to form the dummy active region 4 in the minimum size within the above-described range because if the dummy active region 4 becomes large, capacitance value of the fully silicided gate electrode 5 and wires (not shown) with respect to the semiconductor substrate 1 increases and the performance of the semiconductor device may deteriorate. The dummy active region 4 may be arranged as shown in FIGS. 3A and 3B mentioned above.
After the resist 13 is removed, an isolation insulation film is deposited on the entire surface of the semiconductor substrate 1 by CVD, for example, and then planarized by CMP until the surface of the nitride film 12 is exposed. Thus, the isolation insulation film is buried the isolation groove 1A to form an isolation region 2 as shown in FIG. 4C. A distance S depicted in the figure, i.e., a distance S between the active region 3T2 and the dummy active region 4, is smaller than the double of the thickness of a silicon gate material film deposited to form a fully silicided gate electrode 5 in a later step. This configuration makes it possible to prevent a recess from generating in the silicon gate material film deposited on the isolation region 2 between the active region 3T2 and the dummy active region 4. In the present embodiment, the silicon gate material film 10 is deposited to 100 nm in thickness and the distance S is set to 150 nm.
Although the isolation region 2 described above is formed by a general STI technique, it may be formed by stacking a protective oxide film, a polysilicon film and a nitride film. Alternatively, the isolation region 2 may have a laminated structure formed by oxidizing the surface of the semiconductor substrate 1 and depositing an isolation insulation film thereon. Explanation of thermal treatment and the like is omitted, though they may be performed in some cases.
Then, as shown in FIG. 5A, the top surface of the isolation region 2 is etched down using a hydrogen fluoride solution. The etching is performed to bring the top surface of the isolation region 2 lower than the top surface of the semiconductor substrate 1, i.e., the top surfaces of the active regions 3T1 and 3T2 and the dummy active region 4.
Then, as shown in FIG. 5B, the nitride film 12 is removed using a phosphoric acid solution and the protective oxide film 11 is removed using a hydrogen fluoride solution. As a result, the top surfaces of the active regions 3T1 and 3T2 and the dummy active region 4 are exposed.
Then, a HfO2 film for forming a gate insulating film is formed on the active regions 3T1 and 3T2 and the dummy active region 4 by CVD. Further, a polysilicon film is deposited up to 100 nm on the isolation region 2 and the HfO2 film. A resist (not shown) for forming a gate electrode crossing the active regions 3T1 and 3T2 and the dummy active region 4 is formed by lithography and the HfO2 film and the polysilicon film are etched using the resist pattern as a mask. Thus, a gate insulating film 9 and a silicon gate material film 10 are obtained as shown in FIG. 5C. Then, the resist pattern is removed. In this configuration, the active region 3T2 and the dummy active region 4 have the above-described distance S between them, i.e., a distance smaller than the double of the thickness of the silicon gate material film 10, and the top surface of the isolation region 2 is lower than the top surface of the semiconductor substrate 1. This configuration makes it possible to prevent a recess that hinders the silicidation from generating in the silicon gate material film 10 deposited on the isolation region 2 between the active region 3T2 and the dummy active region 4, thereby making the top surface of the silicon gate material film 10 substantially flat.
Then, according to a known method, sidewalls 6 are formed on both sides of the silicon gate material film 10 and n-type source/drain regions 3a are formed in parts of the active regions 3T1 and 3T2 on both sides of the silicon gate material film 10. An interlayer insulating film 14 made of a silicon oxide film is then formed on the entire surface of the semiconductor substrate 1 by CVD and planarized by CMP until the top surface of the silicon gate material film 10 is exposed. Thus, the structure shown in FIGS. 6A and 6B is obtained. Since the silicon gate material film 10 has the substantially flat top surface as described above, the top surface of the silicon gate material film 10 formed to cross the active regions 3T1 and 3T2 and the dummy active region 4 is exposed by planarizing the interlayer insulating film 14 as shown in the plan view of FIG. 6A and the sectional view of FIG. 6B taken along the VIb-VIb of FIG. 6A, irrespective of the sizes of the active regions 3T1 and 3T2 and the dummy active region 4.
The sidewalls 6 and the source/drain regions 3a may be formed by implanting n-type impurity ions using the silicon gate material film 10 as a mask. More specifically, n-type shallow source/drain layers are formed in parts of the active regions 3T1 and 3T2 on both sides of the silicon gate material film 10. A silicon nitride film is then deposited on the entire surface of the semiconductor substrate 1 by CVD and anisotropically etched to provide the sidewalls 6 on both sides of the silicon gate material film 10. Subsequently, n-type impurity ions are implanted using the sidewalls 6 as a mask and thermal treatment is performed to form n-type deep source/drain diffusion layers in parts of the active regions 3T1 and 3T2 on both sides of the sidewalls 6. The shallow and deep n-type source/drain diffusion layers provide the n-type source/drain regions 3a. The ion implantation for forming the shallow source/drain diffusion layers may be performed using the silicon gate material film 10 and offset spacers formed on both sides of the silicon gate material film 10 as a mask. In this case, the sidewalls 6 are formed on the offset spacers formed on the both sides of the silicon gate material film 10. The sidewalls 6 may be made of a layered film of a silicon oxide film and a silicon nitride film.
Subsequently, as shown in FIG. 7A, metallic material 15 such as nickel (Ni) is deposited to 70 nm on the interlayer insulating film 14 and the exposed silicon gate material film 10 by sputtering. The metallic material 15 is deposited to a sufficient thickness to cause full silicidation of at least part of the silicon gate material film 10 on the active regions 3T1 and 3T2.
Then, as shown in FIG. 7B, thermal treatment such as rapid thermal annealing (RTA) is performed in nitrogen atmosphere at 400° C. to cause silicidation between the metallic material 15 and the silicon gate material film 10, thereby obtaining a fully silicided gate electrode 5. Thus, first and second FETs 7 and 8 are formed on the active regions 3T1 and 3T2, respectively. The silicidation does not occur between the source/drain region 3a and the metallic material 15 because the interlayer insulating film 14 is interposed therebetween. Then, unreacted part of the metallic material 15 is removed by selective etching. Further, an interlayer insulating film, contact plugs and metal wires are formed by a known method.
FIG. 7B illustrates the case where the fully silicided gate electrode 5 is formed by full silicidation between the silicon gate material film 10 and the metallic material 15. Since this structure reduces the wiring resistance, it contributes to improvement in performance of the device. However, the case of FIG. 7C is also acceptable, in which the reaction between the silicon gate material film 10 and the metallic material 15 is not completely achieved and unreacted portions of the silicon gate material film 10 are left on the isolation region 2. For example, as shown in FIG. 7C, the difference in height between the top surface of the isolation region 2 and the top surface of the semiconductor substrate 1 may be increased in the step shown in FIG. 5A, or alternatively, the thickness of the metallic material 15 may be controlled such that part of the silicon gate material film 10 on the isolation region 2 is not fully silicided in the step shown in FIG. 7A such that the silicon gate material film 10 is left or a fully silicided gate electrode 5 of different composition is formed on the isolation region 2. Even in such a case, the fully silicided gate electrodes 5 on the active regions 3T1 and 3T2 always have the same composition irrespective of the sizes (two-dimensional sizes) of the active regions 3T1 and 3T2. Since the FETs are not formed on the isolation region 2, there will be no problem even if the silicide formed on the isolation region 2 has different composition from the silicide constituting the fully silicided gate electrodes 5 on the active regions 3T1 and 3T2. Moreover, if the gate silicon layer 10 remains on the isolation region 2, the capacitance value of the fully silicided gate electrodes 5 with respect to the semiconductor substrate 1 is reduced. This contributes to the improvement in performance of the semiconductor device.
Thus, according to the method of the present embodiment, the top surface of the isolation region 2 is set lower than the top surfaces of the active regions 3T1 and 3T2 and the dummy active region 4 and the dummy active region 4 is arranged to have a distance S from the active region 3T2. As a result, on the isolation region 2 whose top surface is lower than the top surfaces of the active regions 3T1 and 3T2, the silicon gate material film is deposited while preventing the generation of a recess that hinders the silicidation in the top surface thereof. Further, on the active regions 3T1 and 3T2 where the first and second FETs 7 and 8 are formed, the silicon gate material film 10 is deposited with uniform thickness. Therefore, irrespective of the two-dimensional sizes of the active regions 3T1 and 3T2, i.e., regardless of the gate width of the fully silicided gate electrode 5, the fully silicided gate electrode 5 is provided with uniform composition. As a result, the first and second FETs 7 and 8 having the same and uniform composition are simultaneously formed on the single semiconductor substrate 1. Thus, the FETs are obtained with reduced variations in threshold value.
In the embodiment of the present invention, description is made only on the first and second FETs 7 and 8 formed on the substrate for explanation's sake. However, it should be understood that a larger number of elements are formed on the semiconductor substrate 1. The first and second FETs 7 and 8 are not limited to the conductivity type described above and they may be either of N— or P-type FETs.
Instead of oxide hafnium (HfO2) used as the material for the gate insulating film 9, HfSiO, HfSiON, SiO2 or SiON may be used. Further, nickel used as the metallic material 9 may be replaced with titanium (Ti), cobalt (Co), platinum (Pt) or a compound thereof.
The semiconductor device and the method for manufacturing the same according to the present invention are useful as a semiconductor device including field-effect transistors having FUSI gate electrodes and a method for manufacturing the same.
Patent Application
20080079088
