Claims
- 1. A semiconductor device having an emitter region, a base region, and a collector region, formed on an insulating substrate laterally, wherein said emitter region, said base region, and said collector region are each disposed on said insulating substrate, said base region includes a SiGe mixed crystal semiconductor region, and a base electrode formed of polysilicon is connected to said SiGe mixed crystal semiconductor region, said device having an emitter junction between said base region and said emitter region and a collector junction between said base region and said collector region,wherein a forbidden bandwidth of said base region is reduced from the emitter junction toward the collector junction.
- 2. A semiconductor device according to claim 1, wherein said SiGe mixed crystal semiconductor region is in the vicinity of the junction of said emitter region and said base region.
- 3. A semiconductor device according to claim 1 wherein a forbidden band width of said base region is varied from the emitter junction to the collector junction.
- 4. A semiconductor device according to claim 1, wherein the Ge concentration of said SiGe mixed crystal semiconductor is increased from the emitter junction to the collector junction.
- 5. A semiconductor device according to claim 1 wherein an insulating film is formed in contact to said base region to control a potential of said base region, and an electrode is formed in contact to said insulating film.
- 6. A semiconductor device according to claim 1 wherein an insulating film is formed on an interface of said base region and said emitter region.
- 7. A semiconductor device according to claim 1 wherein an insulating film is formed on said emitter region.
- 8. A semiconductor device according to claim 1, wherein said SiGe mixed crystal semiconductor region is included in the vicinity of a junction of said collector region and said base region.
- 9. A semiconductor device according to claim 1, wherein said SiGe mixed crystal semiconductor region is included in the vicinity of a junction of said emitter region and said base region.
Priority Claims (2)
Number |
Date |
Country |
Kind |
5-080317 |
Mar 1993 |
JP |
|
5-298189 |
Nov 1993 |
JP |
|
Parent Case Info
This application is a continuation of application Ser. No. 08/527,499, filed Sep. 13 1995, now abandoned, which was a continuation of application Ser. No. 08/208,696, filed Mar. 11, 1994, now abandoned.
US Referenced Citations (12)
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JP |
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Non-Patent Literature Citations (2)
Entry |
Sato et al. “A Super Self-Aligned Selectively Grown SiGe Base (SSSB) Bipolar Transistor Fabricated by Cold-Wall Type UHV/CVD Technology”, 1994 IEEE.* |
Sato et al. “A Super Self-Aligned Selectively Grown SiGe Base (SSSB) Bipolar Transistor Fabricated by Cold-Wall Type UHV/CVD Technology”, 1994 IEEE. |
Continuations (2)
|
Number |
Date |
Country |
Parent |
08/527499 |
Sep 1995 |
US |
Child |
08/840897 |
|
US |
Parent |
08/208696 |
Mar 1994 |
US |
Child |
08/527499 |
|
US |