The present invention relates to a semiconductor device, and particularly to a MIS transistor having an elevated source/drain structure, in which a source and a drain are formed at higher positions than a gate insulating film.
To date, advancing miniaturization has been the guiding principle to improve the performance of field effect transistors (FETs). For sub-100 nm generation MISFETs (metal-insulator semiconductor FETs), it has been essential that the source/drain high-concentration diffusion layer be made shallow in order to prevent short channel effects and punch-through. Making the source/drain high-concentration diffusion layer shallow causes the portion located below the silicide layer of the source/drain high-concentration diffusion layer to have a reduced thickness, resulting in an increase in the parasitic resistance component and an increase in the junction leakage in the pn junction between the source/drain high-concentration diffusion layer and a body region, which originates from the silicide layer. In order to deal with such a problem, an elevated source/drain structure, in which a portion of each of the source and the drain adjacent to its connection portion to a contact is located outside the silicon substrate, has drawn considerable attention in recent years (see, for example, Satoshi Yamakawa et al., IEEE Electron Device Lett., Vol. 20, No. 7, p. 366, 1999).
Referring to
Particularly with a fully depleted device using an SOI substrate, the thickness of the Si body layer for realizing full depletion has tended to be reduced increasingly as the gate is miniaturized further. In sub-100 nm generation devices the thickness of the Si body layer needs to be as thin as about 30 nm. In an SOI device, if the silicide layer reaches the SiO2 box layer, the contact area between the silicide layer and the source/drain diffusion layer reduces significantly, increasing the resistance. In an attempt to reduce the thickness of the Si body layer in an SOI device as well, it is possible to avoid the problems originating from the silicide layer by adopting the elevated source/drain structure.
In addition, the technique of enhancing the current drive power by using a strained Si layer deposited on a SiGe layer for a channel layer has attracted attention in recent years, which is expected to be brought into practical use (for example, see: Zhi-Yuan Cheng et al., IEEE Electron Device Lett., Vol. 22, No. 7, p. 321, 2001.). With this technique, the strained Si layer on the SiGe layer cannot be deposited thicker than a critical film thickness, so a thin film with a thickness of about 10 to 60 nm is used generally. The SiGe layer, however, is known to have the function to inhibit the formation of cobalt silicide (CoSi2), which is widely used for the contact portions in semiconductor elements (for example, cf R. A. Donaton et al., Appl. Phys. Lett., Vol. 70, No. 10, p. 1266, 1997), and the thickness reduction in strained Si layer can become a cause of variation in contact resistance. Thus, in the utilization of strained Si device as well, problems associated with the silicide formation can be avoided by adopting the elevated source/drain structure.
Nevertheless, formation of the elevated source/drain structure by selective growth has problems such as follows. (See
With reference to
<Problem 1> Disorder in impurity profile (indicated by reference numeral 19)
With the elevated source/drain structure, a source/drain diffusion layer 10 is formed by implanting impurity ions into the Si body layer 3, and thereafter, the protruding portions 18, which form the upper portions of the source and the drain, are formed by selective growth; consequently, the impurity profile of the source/drain diffusion layer 10 is disordered because of the heat treatment during the selective growth of the protruding portions 18. When the impurity profile is disordered, variations in the effective gate length and short channel effects occur, causing the threshold voltage to fluctuate. To suppress this, reducing the temperature of the selective growth (generally 700° C. or lower) is necessary. This, however, creates a problem of lower throughput because the growth rate of low-temperature Si growing is slow.
<Problem 2> Polysilicon deposition on sidewall (indicated by reference numeral 20)
With the elevated source/drain structure, the protruding portions 18 are formed by selective growth of epitaxial Si or polysilicon, but in the selective growth of polysilicon, polysilicon may deposit on the sidewall 9 and so forth. The sidewall 9 covers the side faces of the gate electrode 14. The deposited polysilicon can bring about electrical short-circuiting between the gate and the source or between the gate and the drain. In order to prevent this, it is necessary to achieve high selectivity in the selective growth of epitaxial Si or polysilicon. To enhance the selectivity, addition of a hydrogen chloride gas during the crystal growth is known to be effective; however, the use of a chlorine-based gas may risk corrosion of chamber or piping.
<Problem 3> Local impurity profile disorder in a facet portion (indicated by reference numeral 21)
In the selective growth, a facet (crystal face) is formed in the edge portion of a mask pattern aperture for the selective growth. In such a facet portion, the impurity profile tends to be disordered locally because of channeling effects or the like during the impurity ion implantation. The impurity profile fluctuation can bring about variations in contact resistance. The shape of the facet is difficult to control because it depends on the aperture rate of the mask pattern and the material of the mask in addition to the conditions for the crystal growth.
As discussed above, although the elevated source/drain structure has proved to be effective in improving device performance, the selective growth for forming the elevated source/drain structure has not yet been practical because it has many problems.
It is an object of the present invention to provide a semiconductor device and a method of fabricating the same that are capable of realizing an elevated source/drain structure without using selective growth in forming the source/drain.
In order to accomplish the object, a semiconductor device according to the present invention comprising a MISFET, comprises: a semiconductor layer having a recessed portion formed in a surface thereof, the recessed portion having an opening whose outer circumference is closed; a gate insulating film formed so as to cover at least an inner face of the recessed portion; a gate electrode filling the recessed portion such that the gate insulating film is interposed between the gate electrode and the inner face of the recessed portion; and a pair of source/drains, located on both sides of the gate electrode when viewed in plan and formed to a predetermined depth from the surface of the semiconductor layer. This configuration makes it possible to realize an elevated source/drain structure without using selective growth in forming the source/drain.
The foregoing semiconductor may further comprise: a first sidewall, which has tubular form and is made of an insulator, provided along the opening of the recessed portion so as to protrude from the surface of the semiconductor layer; wherein: the gate insulating film is formed so as to cover an inner circumferential face of the first sidewall and the inner face of the recessed portion; the gate electrode fills an interior of the first sidewall and the recessed portion such that the gate insulating film is interposed between the gate electrode and the inner circumferential face of the first sidewall and the recessed portion; and the pair of source/drains are formed so as to be located on both sides the first sidewall when viewed in plan.
The foregoing semiconductor layer may be made of silicon.
The foregoing semiconductor device may comprise a substrate having the foregoing semiconductor layer.
The foregoing substrate may be an SOI substrate, and the foregoing semiconductor layer may be formed by a Si body layer.
It is preferable that the recessed portion be formed in the Si body layer; that a silicide layer be formed in portion of the source/drain including the surface thereof, and that the following expressions be satisfied:
T1<T2, and
T3<T2,
where T1 is the thickness of the silicide layer, T2 is the thickness of a portion of the Si body layer in which the recessed portion is not formed, and T3 is the thickness of a portion of the Si body layer in which the recessed portion is formed.
The foregoing substrate may have a SiGeC channel layer through which carriers run and a Si cap layer formed on the SiGeC channel layer, and the foregoing semiconductor layer may be formed by the Si cap layer.
It is preferable that: the recessed portion be formed in the Si cap layer; that a silicide layer be formed in portion of the source/drain including the surface thereof, and that the following expressions be satisfied:
T1<T4, and
T5<T4,
where T1 is the thickness of the silicide layer, T4 is the thickness of a portion of the Si cap layer in which the recessed portion is not formed, and T5 is the thickness of a portion of the Si cap layer in which the recessed portion is formed.
The foregoing substrate may have a lattice-relaxed SiGeC layer, and a strained Si channel layer formed on the lattice-relaxed SiGeC layer, and the semiconductor layer may be formed by the strained Si channel layer.
It is preferable that: the recessed portion be formed in the strained Si channel layer; that the silicide layer be formed in portion of the source/drain including the surface thereof, and that the following expressions be satisfied
T1<T6 and
T7<T6,
where T1 is the thickness of the silicide layer, T6 is the thickness of a portion of the strained Si channel layer in which the recessed portion is not formed, and T7 is the thickness of a portion of the strained Si channel layer in which the recessed portion is formed.
The gate insulating film may be formed such that the gate insulating film covers, and is in contact with, the inner circumferential face of the first sidewall and the inner face of the recessed portion.
The recessed portion may have an inner circumferential face and a bottom face, a second sidewall made of an insulator may be formed so as to cover the inner circumferential face of the first sidewall and the inner circumferential face of the recessed portion, and the gate insulating film may be formed so as to cover the bottom face of the recessed portion and so as to cover the inner circumferential face of the recessed portion such that the second sidewall is interposed between the gate insulating film and the inner circumferential face of the recessed portion.
The source/drain may have a silicide layer, and the silicide layer may contain any one of TiSi2, VSi2, CrSi2, ZrSi2, NbSi2, MoSi2, HfSi2, TaSi2, WSi2, NiSi2, NiSi, CoSi2, CoSi, Pt2Si, PtSi, Pd2Si, and PdSi, or combinations thereof.
The foregoing first sidewall may include a silicon nitride film.
The foregoing gate electrode may be made of any one of the materials selected from Al, Cu, W, Mo, Ti, Ta, WSi, MoSi2, TiSi2, TiN, and TaN, or may be formed by stacked layers made of a plurality of materials selected from these materials
The foregoing gate insulating film may be made of any one of the materials selected from SiO2, ZrO2, Zr—Si—O, Zr—Si—O—N, HfO2, Hf—Si—O, Hf—Si—O—N, SiN, TiO2, La2O3, SiON, Al2O3, SrTiO3, BaSrTiO3, Nd2O3, and Ta2O5, or may be formed by stacked layers made of a plurality of materials selected from these materials.
A method, according to the present invention, of fabricating a semiconductor device comprising a MISEFT, comprises: (a) forming a dummy gate electrode on a semiconductor substrate; (b) ion-implanting an impurity using the dummy gate electrode as a mask to form an extension diffusion layer in the semiconductor substrate; (c) forming a first sidewall made of an insulator having tubular form so as to surround a side face of the dummy gate electrode; (d) ion-implanting an impurity using the dummy gate electrode and the first sidewall as a mask and thereby forming source/drains in the semiconductor substrate in a self-aligned manner; (e) subsequent to the step (d), forming an interlayer insulating film so as to cover a surface of the semiconductor substrate; (f) selectively removing the dummy gate electrode by dry etching using the interlayer insulating film as a mask; (g) forming a gate recess in the semiconductor substrate that lies below a region from which the dummy gate electrode has been removed; (h) forming a gate insulating film in a recessed form so as to cover an inner circumferential face of the first sidewall and an inner face of the gate recess; and (i) forming a gate electrode in a self-aligned manner so as to fill an interior of the gate insulating film in the recessed form. This configuration makes it possible to realize an elevated source/drain structure without using selective growth in forming the source/drain.
The foregoing step (g) may be a step of, using the interlayer insulating film as a mask, selectively etching the semiconductor substrate lying below a region from which the dummy gate electrode has been removed, by dry etching, to form the gate recess in the semiconductor substrate.
The foregoing step (g) may include the steps of: (m) selectively oxidizing a portion below the region from which the dummy gate electrode has been removed using the interlayer insulating film as a mask; and (n) a step of removing the oxide film that has been selectively oxidized to form the gate recess in the semiconductor substrate.
The foregoing step (h) may include the steps of: (k) forming a second sidewall made of an insulator so as to cover the inner circumferential face of the first sidewall and the inner circumferential face of the gate recess; and (l) forming the gate insulating film in a recessed form so as to cover an inner circumferential face of the second sidewall and a bottom face of the gate recess.
The foregoing and other objects, features, and advantages of the present invention will be made apparent from the following detailed description of preferred embodiments when taken in conjunction with the accompanying drawings.
FIGS. 3(a) through 3(i) are cross-sectional views illustrating, step by step, a first method of fabricating the semiconductor device according to the first embodiment of the present invention.
FIGS. 4(a) through 4(d) are cross-sectional views illustrating, step by step, a second method of fabricating the semiconductor device according to the first embodiment of the present invention.
FIGS. 8(a) through 8(d) are cross-sectional views illustrating, step by step, a method of fabricating the semiconductor device according to the second embodiment of the present invention.
Hereinbelow, embodiments of the present invention are described with reference to the drawings.
Herein, the semiconductor device is a n-MISFET. As a substrate 1, an SOI substrate is used.
Referring to
The gate electrode 14 has a rectangular shape when viewed in plan, and herein, its shorter side directions are set along the gate length direction. That is, a pair of source/drains 102, 102 are formed in the Si body layer 3 so as to be on both sides of the gate electrode 14 that are along the shorter side directions when viewed in plan and be in contact with the first sidewall 9. The pair of source/drains 102, 102 are formed across the entire thickness of the Si body layer 3. Each source/drain 102 comprises a silicide layer 11 formed to have a thickness T1 and a source/drain diffusion layer 10 formed directly below the silicide layer 11. The silicide layer 11, precisely speaking, protrudes several nanometers from the surface of the Si body layer 3. The amount of the protrusion, however, takes up only a very small proportion with respect to the thickness of the SOI substrate 1, which is 700 μm, so the silicide layer 11 may be regarded as being formed substantially immediately underneath the surface of the SOI substrate 1 and the Si body layer 3. The source/drain diffusion layer 10 is formed by a high-concentration n-type region.
A pair of extension diffusion layers 8, 8 are formed between the gate recess 101 and the pair of source/drains 102, 102 (in the regions underneath the first sidewall 9 that are in contact with the pair of source/drains 102, 102 when viewed in plan). Each extension diffusion layer 8 is formed from the surface of the Si body layer 3 to a position that is lower than the bottom of the gate recess 101. Each extension diffusion layer 8 is formed by a low-concentration n-type region. A Si body region 3a is formed in a portion of the Si body layer 3 that is located below the pair of extension diffusion layers 8, 8 and the gate recess 101. The Si body region 3a is formed by a middle-concentration p-type region.
An interlayer insulating film 12 is formed so as to cover the surface of the substrate 1 in which thus, the gate electrode 14, the gate insulating film 13, the first sidewall 9, and the pair of source/drains 102, 102 are formed.
Contacts 15 piercing through the interlayer insulating film 12 are connected to the pair of source/drains 102, 102. Wiring lines, which are not shown in the drawings, are connected to the upper ends of the contacts 15. Likewise, a contact, which is not shown in the drawings, that pierces through the interlayer insulating film 12 is connected to the gate electrode 14, and a wiring line, which is not shown in the drawings, is connected to the upper end of the contact 15. It should be noted that one of the pair of source/drains 102, 102 serves as a source while the other one serves as a drain during the use of this semiconductor device.
Incidentally, if the silicide layer 11 reaches the SiO2 box layer 2, the contact area between the silicide layer 11 and the semiconductor regions (the extension diffusion layer 8, the Si body region 3a, and so forth) reduces significantly and therefore the contact resistance between the silicide layer 11 and the semiconductor regions significantly increases. To avoid this problem, it is desirable that in the present embodiment the lower end positions of the source/drain 102, the silicide layer 11, and the gate recess 101 are set so as to satisfy the following conditions.
The thickness of the silicide layer 11 is T1, as mentioned above. The thickness of the source/drain 102 (the distance from the surface of the Si body layer 3 to the lower end of the source/drain 102) is represented by T2, and the thickness of the Si body region 3a that is below the gate recess 101 (the distance from the lower end of the gate recess 101 to the lower end of the source/drain 102) is represented by T3.
In this case, it is desirable that T1, T2, and T3 are set to satisfy the following expressions:
T3<T2, and
T1<T2.
Herein, when a fully depleted SOI device is to be produced, it is desirable that:
T3<Lg/3,
where Lg is the gate length. It should be noted that because
Next, methods of fabricating the semiconductor device will be explained, which are discussed as a first fabrication method and a second fabrication method below.
{First Fabrication Method}
Firstly, a first fabrication method is explained.
FIGS. 3(a) through 3(i) are cross-sectional views illustrating, step by step, the first method of fabricating the semiconductor device of the present embodiment.
[Step of Forming a Dummy Gate (
Referring to
Next, using a resist mask formed by lithography, formation of a dummy gate 6 is carried out by means of dry etching. Herein, the dummy gate passivation film 7 may be used as a hard mask. Thereby, a rectangular parallelepiped body 103 made of the dummy insulating film 5, the dummy gate 6, and the dummy gate passivation film 7 is formed.
[Step of Forming Extension (
Next, referring to
[Step of Forming a First Sidewall (
Next, referring to
[Step of Implantation for Source/Drain (
Next, referring to
[Step of Forming Silicide (
Next, referring to
Here, it is possible to widen the area in which the silicide layer 11 is in contact with the semiconductor (that is, the area in which the silicide layer 11 is in contact with the source/drain diffusion layer 10 and with the extension diffusion layer 8) by setting the thickness T1 of the silicide layer 11 so as to satisfy the expression:
T1<T2,
and thus the effect of preventing the contact resistance from increasing can be obtained.
[Step of Forming an Interlayer Insulating Film (
Next, referring to
[Step of Removing the Dummy Gate (
Next, referring to
[Step of Forming a Gate Recess (
Next, referring to
Next, the gate recess 101 having a rectangular parallelepiped shape is formed in the Si body layer 3 by dry-etching the Si body layer 3 that is located below the interior space of the first sidewall 9. For the dry etching gas, it is desirable to use chlorine, bromine, or a mixed gas thereof. When using these gases, it is possible to selectively etch only the Si body layer 3 using the interlayer insulating film 12 as a mask. Moreover, there is an advantage that the first sidewall 9 is not etched.
Herein, when the thickness of the portion of the Si body layer 3 that is located below the gate recess 101 is T3, as mentioned previously, it is desirable to satisfy the expression:
T3<T2.
By selectively dry etching only the portion of the the Si body layer 3 that is located below the interior space of the first sidewall 9 in this way, it becomes possible to realize an elevated source/drain in a self-aligned manner without using a selective growth method.
It is also possible to carry out the steps of FIGS. 3(g) and 3(h) by a single dry etching step.
[Step of Forming Gate Insulating Film (
Next, referring to
[Step of Forming Gate Electrode Forming Step (
Next, referring to
Next, planarization is performed by CMP. Thereby, the gate electrode 14 that fills the interior space of the first sidewall 9 and the gate recess 101 is formed so that the gate insulating film 13 is interposed therebetween. In addition, the Si body region 3a made of a p-type conductive region is formed so as to be located below the extension diffusion layer 8 and the gate recess 101.
Thereafter, as shown in
The present process can form the gate recess, which is formed so as to be filled with the gate electrode 14 therein, in the Si body layer 3 in a self-aligned manner; therefore, it is possible to realize a similar structure to the elevated source/drain structure by a simplified process without using a selective growth method. As a consequence, all the problems associated with the selective growth can be resolved because the selective growth is not used. Moreover, the present process can utilize a low temperature process with a process temperature of at most about 400° C. for the steps that follow the activation annealing of the source/drain diffusion layer 10 (after the step of
Additionally, in the present embodiment, the gate electrode 14 is formed in the gate recess 101 of the Si body layer 3, and the first sidewall 9 is formed on the surface of the Si body layer 3; therefore, the thickness (T2) of the semiconductor layer below the first sidewall 9 becomes thicker than the thickness (T3) of the semiconductor layer below the gate electrode 14. For this reason, the resistance of the extension portion can be lowered in comparison with the conventional example, in which the thickness of the semiconductor layer below the gate electrode 14 is equal to the thickness of the semiconductor layer below the sidewall.
{Second Fabrication Method}
Next, a second fabrication method is explained.
FIGS. 4(a) through 4(d) are cross-sectional views illustrating, step by step, the second method of fabricating the semiconductor device of the present embodiment.
The second fabrication method differs from the first fabrication method in the method of forming the gate recess 101, but is similar to the first fabrication method in other respects. Accordingly, since the fabrication steps from the step of forming the dummy gate (
[Step 1 of Turning the Portion Below the Gate into a Thin Film (
Referring to
[Step 2 of Turning the Portion Below the Gate into a Thin Film (
Next, referring to
The step of forming a gate insulating film (
It should be noted that the fabrication steps that follow the selective oxidation of the step of forming the gate recess 1 (
It should be noted that although the semiconductor device is formed by a n-MISFET in the foregoing configuration, it is also possible to form this by a p-MISFET. This can be achieved by changing the type of impurity. Specifically, in the step of ion-implanting boron, a n-type dopant such as arsenic, phosphorus, or the like may be used in place of boron. On the other hand, in the step of ion-implanting arsenic or phosphorus, a p-type dopant such as boron may be used in place of arsenic or phosphorus.
In addition, although the SOI substrate is used as the substrate 1 in the foregoing configuration, it is also possible to employ an ordinary Si bulk substrate, in a case of which the above-described fabrication method can of course be applied in the same manner as in the case of the SOI substrate.
Furthermore, it will be apparent that it is possible to form the semiconductor device of the present embodiment by a hetero-MISFET in which the channel is made of a SiGeC layer, or a strained Si MISFET in which the channel is made of a strained Si layer on a lattice-relaxed SiGeC layer, and that the above-described fabrication method can be applied to fabricate these devices.
Next, examples in which the semiconductor device is formed by a hetero MISFET or a strained Si MISFET will be specifically described as a first modified example and a second modified example of the present embodiment.
As illustrated in
The hetero MISFET of the present modified example utilizes, as the substrate 1, a substrate in which a SiGeC channel layer 22 and a Si cap layer 23 having a thickness of about about 5 nm to 20 nm are formed successively on a Si substrate 1a using a UHV-CVD (Ultra High Vacuum Chemical Vapor Deposition) method. Then, an insulator 4 is formed so as to reach the Si substrate 1a, and an active region is formed of the Si substrate 1a, the SiGeC channel layer 22, and the Si cap layer 23 that are surrounded by the insulator 4. In the substrate 1, the gate recess 101 is formed in the Si cap layer 23 because the Si cap layer 23 is the uppermost layer. As shown in
T1<T4, and
T5<T4,
because the SiGeC channel layer 22 is thereby not turned into a silicide. In addition, in order to prevent the parasitic channel produced at the interface between the Si cap layer 23 and the gate insulating film 15, it is preferable that T5 is set within a thin range of from about 1 nm to 10 nm.
As illustrated in
The strained Si MISFET of the present modified example utilizes, as the substrate 1, a substrate in which a relaxed SiGeC layer 24 and a strained Si channel layer 25 having a thickness of about 1 μm to 4 μm are formed successively on a Si substrate 1a using a UHV-CVD method. Then, an insulator 4 is formed in the strained Si channel layer 25, and an active region is formed of a region of the strained Si channel layer 25 surrounded by the insulator 4. In the substrate 1, the gate recess 101 is formed in the strained Si channel layer 25 because the strained Si channel layer 25 is the uppermost layer. As shown in
T1<T6, and
T7<T6,
because the relaxed SiGeC layer 24 is thereby not turned into a silicide. In order to prevent the strained Si layer 25 from undergoing lattice relaxation, it is preferable that T6 be set within the range of from about 10 nm to 60 nm.
As illustrated in
Since in the present embodiment the second sidewall 16 is formed in this manner, the present embodiment has two advantages as follows. The first advantage is that it is possible to reduce the fringe capacitance between the gate and the source and between the gate and the drain. This enables a high-speed operation. The second advantage is that the gate length can be determined by the second sidewall 16. Furthermore, in addition to the fact that the gate length below the limit of lithography is possible to fabricate, an extremely ideal gate electrode 14 with very small gate length and low gate resistance and low fringe capacitance can be realized because the cross-sectional structure of the gate results in a mushroom structure.
Next, a method of fabricating the semiconductor device constructed in the above-described manner will be explained.
FIGS. 8(a) through 8(d) are cross-sectional views illustrating, step by step, the method of fabricating the semiconductor device according to the present embodiment. In FIGS. 8(a) through 8(d), the same reference numerals as used in FIGS. 3(a) through 3(j) represent the same or like parts.
An important point in the fabrication method in the present embodiment is the method of forming the second sidewall 16. The steps that precede the step of forming the second sidewall 16, up to the step of forming the gate recess, are identical to the first fabrication method in the first embodiment (see FIGS. 3(a) through 3(h)). Accordingly, the explanation thereof is omitted here, and the steps that follow the step of forming the second sidewall will be explained.
[Step of Forming a Second Sidewall (
In
[Step of Forming a Gate Insulating Film (
Next, in
[Step of Forming a Gate Electrode (FIGS. 8(c) and 8(d))]
Next, in
Next, in
It should be noted that it is of course possible to use the first fabrication method in the embodiment in the present embodiment, in place of the second fabrication method.
As has been explained thus far, the present embodiment achieves such advantageous effects as realization of a gate length that is below the processing limit by lithography, reduction in gate fringe capacitance, and moreover attaining a gate structure that is a mushroom structure.
It should be noted that in the present embodiment as well, a Si bulk substrate may be used in place of the SOI substrate. Moreover, the present embodiment may be modified in similar manners to those in the first and the second modified examples of the first embodiment.
In the first embodiment and the second embodiment, the layer that has been described as the “SiGeC layer” may be substituted by either one of a SiGe layer, which does not contain C, or a SiC layer, which does not contain Ge.
From the foregoing description, numerous improvements and other embodiments of the present invention will be readily apparent to those skilled in the art. Accordingly, the foregoing description is to be construed only as illustrative examples and as being presented for the purpose of suggesting the best mode for carrying out the invention to those skilled in the art. Various changes and modifications can be made in specific structures and/or functions substantially without departing from the scope and sprit of the invention.
The semiconductor device according to the present invention is useful as a MISFET or the like having an elevated source/drain structure.
The method of fabricating a semiconductor device according to the present invention is useful as a method of fabricating a MISFET or the like having an elevated source/drain structure.
Number | Date | Country | Kind |
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2003-124043 | Apr 2003 | JP | national |
This application is the U.S. National Phase under 35 U.S.C. § 371 of International Application No. PCT/JP2004/006157, filed on Apr. 28, 2004, which in turn claims the benefit of Japanese Application No. 2003-124043, filed on Apr. 28, 2003, the disclosure of which Applications are incorporated by reference herein.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP04/06157 | 4/28/2004 | WO | 11/9/2006 |