Claims
- 1. A method of manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with a conductor pattern which includes at least one set of conducting portions electrically connected to each other, the method comprising:
a polishing step for flattening the conducting portions together with the insulating film by chemical mechanical polishing; a chemical cleaning step for cleaning a flattened surface of the insulating film with a cleaning liquid; and a rising step for removing the cleaning liquid using a rinsing liquid; wherein the rinsing step is performed using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight as the rinsing liquid.
- 2. The method of manufacturing a semiconductor device according to claim 1, wherein the dissolved oxygen concentration of the water as the rinsing liquid is no more than 4 ppm by weight.
- 3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductor pattern is formed of Cu or a Cu alloy.
- 4. The method of manufacturing a semiconductor device according to claim 1, wherein the set of conducting portions has a surface area of no less than 500 μm.
- 5. The method of manufacturing a semiconductor device according to claim 4, wherein the set of conducting portions includes a pad, and a wiring directly connected to the pad.
- 6. The method of manufacturing a semiconductor device according to claim 5, wherein the wiring of the conducting portions has a width of no more than 1.0 μm.
- 7. The method of manufacturing a semiconductor device according to claim 4, wherein the set of the conducting portions of the one insulating film includes a plurality of wirings which are electrically connected to each other via a conductor pattern of an underlying insulating film.
- 8. The method of manufacturing a semiconductor device according to claim 7, wherein each of the wirings has a width of no more than 1.0 μm.
- 9. The method of manufacturing a semiconductor device according to claim 1, wherein the polishing step includes a first polishing treatment using a chemical slurry and a second polishing treatment using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight.
- 10. The method of manufacturing a semiconductor device according, to claim 9, wherein the dissolved oxygen concentration of the water used in the second polishing treatment is no more than 4 ppm by weight.
- 11. A method of manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with a conductor pattern which includes at least one set of conducting portions electrically connected to each other, the method comprising:
an insulating film forming step for forming an insulating film on a substrate; a pattern forming step for forming a wiring groove and a connection hole in the insulating film; a metal film forming step for applying a metal material to the insulating film to fill the wiring groove and the connection hole with the metal material; a polishing step for polishing the metal film by chemical mechanical polishing so that the metal material filled in the wiring groove and the connection hole remains as conducting portions; a cleaning step for cleaning the polished insulating film with a cleaning liquid; a rinsing step for removing the cleaning liquid with water with a dissolved oxygen concentration of no more than 6 ppm by weight; and a drying step for removing the water used in the rinsing step.
- 12. The method of manufacturing a semiconductor device according to claim 11, wherein the dissolved oxygen concentration of the water as the rinsing liquid is no more than 4 ppm by weight.
- 13. The method of manufacturing a semiconductor device according to claim 11, wherein the metal material is Cu or a Cu alloy.
- 14. The method of manufacturing a semiconductor device according to claim 11, wherein the set of conducting portions has a surface area of no less than 500 μm2.
- 15. The method of manufacturing a semiconductor device according to claim 14, wherein the set of conducting portions includes a pad, and a wiring directly connected to the pad.
- 16. The method of manufacturing a semiconductor device according to claim 15, wherein the wiring of the conducting portions has a width of no more than 1.0 μm.
- 17. The method of manufacturing a semiconductor device according to claim 14, wherein the set of the conducting portions of the one insulating film includes a plurality of wirings which are electrically connected to each other via a conductor pattern of an underlying insulating film.
- 18. The method of manufacturing a semiconductor device according to claim 17, wherein each of the wirings has a width of no more than 1.0 μm.
- 19. The method of manufacturing a semiconductor device according to claim 11, wherein the polishing step includes a first polishing treatment using a chemical slurry and a second polishing treatment using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight.
- 20. The method of manufacturing a semiconductor device according to claim 19, wherein the dissolved oxygen concentration of the water used in the second polishing treatment is no more than 4 ppm by weight.
- 21. A semiconductor device having a multilayer wiring structure comprising:
a plurality of laminated insulating films each of which is formed with a conductor pattern; the conductor pattern on each of the insulating films including a plurality of conducting portions; each of the conducting portions or a set of conducting portions electrically connected to each other on a same insulating film has a surface area of no more than 500 μm2.
- 22. The semiconductor device according to claim 21, wherein the conductor pattern is formed of Cu or a Cu alloy.
- 23. The semiconductor device according to claim 21, wherein the conductor pattern on each of the insulating films includes a wiring having a width of no more than 1.0 μm.
REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of International Application PCT/JP00/04164 filed Jun. 23, 2000.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/JP00/04164 |
Jun 2000 |
US |
Child |
10326883 |
Dec 2002 |
US |