This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-149903, filed Sep. 21, 2022, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and a method of manufacturing a semiconductor device.
As an aspect ratio increases, there is a tendency to become more difficult to embed a pattern with a predetermined film. Due to this, unintended seams and voids are formed so that product failure occurs.
Embodiments provide a semiconductor device and a method of manufacturing a semiconductor device that can prevent embedding failure.
In general, according to at least one embodiment, a semiconductor device includes a first layer including a first recess portion on an upper surface; and a second recess portion that extends from a bottom surface of the first recess portion in the first layer, and the second recess portion has a tapered shape in which a width in a first direction along a surface direction of the first layer reduces from the bottom surface of the first recess portion in a depth direction of the first layer.
Hereinafter, embodiments of the present disclosure are described with reference to the drawings. In addition, the present disclosure is not limited by the following embodiments. In addition, components in the following embodiments include those that can be easily assumed by those skilled in the art or substantially the same components.
Embodiment 1 is described in detail below with reference to the drawings.
(Configuration Example of Semiconductor Device)
In this specification, both the X direction and the Y direction are directions along a plane of a word lines WL described below, and the X direction and the Y direction are orthogonal to each other.
As illustrated in
The substrate SB is, for example, a semiconductor substrate such as a silicon substrate. The peripheral circuit CUA including a transistors TR, wiring, and the like is disposed on the substrate SB. The peripheral circuit CUA contributes to an operation of a memory cell described below.
The peripheral circuit CUA is covered with an insulating layer 60. A source line SL is disposed on the insulating layer 60. The plurality of word lines WL are stacked on the source line SL. The plurality of word lines WL are covered with an insulating layer 50. The insulating layer 50 expands around the plurality of word lines WL.
A plurality of plate-shaped contacts LI that penetrate the word lines WL in a stacking direction and extend in a direction along the X direction are located in the plurality of word lines WL. Therefore, the plurality of word lines WL are divided by the plurality of plate-shaped contacts LI in the Y direction.
The plurality of memory regions MR, the step region SR, and the through contact region TP are located between the plurality of plate-shaped contacts LI in the X direction side by side. The plurality of memory regions MR are separated from each other in the X direction with the step region SR and the through contact region TP interposed therebetween.
A plurality of pillars PL penetrating the word lines WL in the stacking direction are located in the memory region MR. In intersections between the pillars PL and the word lines WL, a plurality of memory cells are formed. Therefore, the semiconductor device 1 is configured, for example, as a three-dimensional nonvolatile memory in which memory cells are three dimensionally located in the memory region MR.
The step region SR includes step portions SP in which a plurality of word lines WL are dug down in a mortar shape in the stacking direction.
The step portion SP forms one side in a mortar shape that descends stepwise from both sides in the X direction and one side in the Y direction toward the bottom surface.
Each step of the step portions SP is configured with the word line WL in each hierarchical level. The word line WL in each hierarchical level maintains electrical connection on both sides in the X direction via the step portion SP with the step regions SR interposed therebetween. A contact CC for connecting the word line WL in each hierarchical level and upper layer wiring MX is located in a terrace portion on each step of the step portion SP.
As a result, the word lines WL stacked in multiple layers can be drawn out individually. From these contacts CC, write voltages, read voltages, and the like are applied to memory cells in the memory regions MR on both sides in the X direction via word lines WL at the same height position as the memory cells.
In this specification, the direction in which the terrace surface of each step of the step portion SP faces is defined as an upward direction.
The through contact region TP is disposed on one side of the step region SR in the X direction. A through contact C4 penetrating the plurality of word lines WL is disposed in the through contact region TP. The through contact C4 connects the peripheral circuit CUA disposed on the lower substrate SB and the upper layer wiring MX connected to the contact CC of the step portion SP. Various voltages applied from the contact CC to the memory cell is controlled by the peripheral circuit CUA via the through contact C4, the upper layer wiring MX, and the like.
Next, a specific configuration example of the semiconductor device 1 is described by using
As illustrated in
As illustrated in
The active areas AR are regions where impurities are diffused on the substrate SB and function as sources or drains of the transistors TR. The active areas AR are connected to the through contacts C4 illustrated in
The element dividing section DS has a configuration in which a groove provided in the substrate SB is filled with an insulating layer 58 such as an oxide silicon layer. The element dividing sections DS extend along the surface of the substrate SB and are located side by side at a predetermined interval in a direction intersecting the extending direction each other. Accordingly, the respective active areas AR are electrically separated.
The peripheral circuit CUA having the above configuration is covered, for example, with the insulating layer 60 such as an oxide silicon layer.
The source line SL is, for example, a conductive polysilicon layer.
The stacked body LM is located on the source line SL. The plurality of word lines WL and a plurality of insulating layers OL are alternately stacked one by one in the stacked body LM. The stacking number of the word lines WL in the stacked body LM is freely set.
The word lines WL as a plurality of conductive layers are, for example, tungsten layers or molybdenum layers. The plurality of insulating layers OL are, for example, oxide silicon layers.
The upper surface of the stacked body LM is covered with an insulating layer 52, and the insulating layer 52 configures a portion of the insulating layer 50 illustrated in
As illustrated in
The plate-shaped contacts LI are located side by side in the Y direction and extend in directions along the stacking direction of the stacked body LM and the X direction. That is, the plate-shaped contacts LI penetrate the insulating layers 52 and 51 and the stacked body LM and reach the source line SL. Also, the plate-shaped contacts LI continuously extend in the stacked body LM from one end portion to the other end portion of the stacked body LM in the X direction.
In addition, the plate-shaped contacts LI each include an insulating layer 55 and a conductive layer 21. The insulating layer 55 is, for example, an oxide silicon layer. The conductive layer 21 is, for example, a tungsten layer or a conductive polysilicon layer.
The insulating layer 55 covers side walls of the plate-shaped contacts LI in the Y direction. The conductive layer 21 fills the inside of the insulating layer 55 and is electrically connected to the source line SL. In addition, the conductive layer 21 is connected to the upper layer wiring MX via a plug VO located in the insulating layer 52. In such a configuration, the plate-shaped contacts LI function as source line contacts.
However, instead of the plate-shaped contacts LI, a plate-shaped portion filled with an insulating layer may divide the stacked body LM in the Y direction by penetrating the stacked body LM and extending in a direction along the X direction. In this case, such a plate-shaped portion does not have a function as a source line contact.
As illustrated in
The insulating layer 51 such as the oxide silicon layer is located in the step region SR to cover the upper surface of the step portion SP. The insulating layer 52 described above also covers the upper surface of the insulating layer 51.
The contacts CC penetrating the insulating layers 52 and 51 are connected to the word lines WL that configure each step of the step portion SP.
The contact CC includes an insulating layer 56 that covers an outer circumference of the contact CC and a conductive layer 22 such as a tungsten layer or a copper layer that fills the inside of the insulating layer 56. The conductive layer 22 is connected to the upper layer wiring MX via the plug VO located in the insulating layer 52. This upper layer wiring MX is connected to the through contact C4 of the through contact region TP adjacent in the Y direction, for example, via the plate-shaped contacts LI as described above.
In such a configuration, the word line WL of each layer can be electrically drawn out. That is, in the above configuration, a predetermined voltage is applied to a memory cell formed in the pillars PL (see
Here,
The plurality of columnar portions HR that penetrate the insulating layer 51 and the stacked body LM and reach the step region SR are located on the source line SL in a dispersed manner.
The plurality of columnar portions HR are located in a zigzag or a grid shape while avoiding interference with the contacts CC and the plate-shaped contacts LI. The columnar portions HR each have, for example, a circular shape, an oval shape, or an elliptical shape as a cross-sectional shape along the XY plane.
The plurality of columnar portions HR each have, for example, a configuration in which an insulating layer 54 fills in the hole penetrating the insulating layer 51 and the stacked body LM and does not contribute to the function of the semiconductor device 1. In a step of manufacturing the semiconductor device 1, the columnar portion HR has a role of supporting such a configuration when the stacked body LM is formed with a stacked body obtained by stacking sacrifice layers and insulating layers.
Meanwhile, the plate-shaped contacts LI, the contacts CC, the columnar portion HR, and the element dividing sections DS described above each have a bowing shape near an upper end portion. The bowing shape refers to a shape in which a width or a diameter becomes maximum between the upper end portion and the lower end portion. In addition, auxiliary layers 120a are provided with a predetermined depth around the upper end portions of the plate-shaped contacts LI, the contacts CC, the columnar portion HR, and the element dividing sections DS.
The auxiliary layers 120a surround each of the plate-shaped contacts LI, the contacts CC, the columnar portion HR, and the element dividing sections DS and are formed to a depth on the upper side of a position where a width or a diameter of each portion having a bowing shape becomes maximum.
The auxiliary layer 120a is, for example, LP-TEOS formed by low pressure-chemical vapor deposition (LP-CVD) and P-dTEOS formed by plasma CVD. In addition, as the auxiliary layer 120a, P—SiN, Poly-Si, and the like may be used. At least any one of these is used as the auxiliary layer 120a.
Specifically, for example, when a formation target of the auxiliary layer 120a is the contact CC, the auxiliary layer 120a further surrounds an outer circumference of the insulating layer 56 that surrounds the outer circumference portion of the contact CC and is formed, for example, in a rectangular shape, when viewed from the above.
In addition, for example, when the formation target of the auxiliary layer 120a is the columnar portion HR, the auxiliary layer 120a surrounds the outer circumference of the insulating layer 54 of the columnar portion HR and is formed, for example, in a rectangular shape when viewed from the above.
Meanwhile, for example, when the formation target of the auxiliary layer 120a is the plate-shaped contact LI, the auxiliary layer 120a surrounds the plate-shaped contact LI along the side wall of the insulating layer 55 of the plate-shaped contact LI extending in the Y direction and is formed, for example, in a rectangular shape having a long side in the Y direction, when viewed from the above.
In addition, for example, when the formation target of the auxiliary layer 120a is the element dividing section DS, the auxiliary layer 120a surrounds the insulating layer 58 along the side wall of the insulating layer 58 of the element dividing section DS extending in the X direction and is formed, for example, in the rectangular shape having the long side in the extending direction of the element dividing section DS when viewed from the above.
(Method of Manufacturing Semiconductor Device)
Next, by using
In the example of
Here, the layer to be processed 100 is a layer to be a process target when the plate-shaped contacts LI, the contacts CC, the columnar portion HR, and the element dividing sections DS are formed, which is an example of an application target in the present step. For example, when the contact CC is formed, the layer to be processed 100 is the insulating layer 51 described above. In addition, for example, when the plate-shaped contacts LI and the columnar portion HR are formed, the layer to be processed 100 is a stacked body before the insulating layer 51 and the word lines WL are formed. Also, when the element dividing section DS is formed, the layer to be processed 100 is the substrate SB.
As illustrated in
As illustrated in
At this time, for example, a method by plasma etching such as reactive ion etching (RIE) or the like is used as the etching. After performing ashing on the resist pattern 270p and the BARC layer 200, an SH process or the like may be performed.
As illustrated in
Specifically, for example, a material having lower resistance to plasma etching such as RIE than the material of the layer to be processed 100 is selected for the auxiliary layers 120a. That is, a material that has a higher etching rate and is easier to etch than the material of the layer to be processed 100 may be used as the material of the auxiliary layer 120a.
As illustrated in
As illustrated in
More specifically, a BARC layer and a resist layer (not illustrated) are formed on the upper surface of the layer to be processed 100, and a resist pattern (not illustrated) having a predetermined pattern in the region where the auxiliary layer 120a is formed when viewed from the above is formed. After the BARC layer 200 is removed, the auxiliary layer 120a and the layer to be processed 100 are etched by using the resist pattern as a mask to remove the resist pattern and the BARC layer by ashing. Accordingly, the embedding target portion 130a is formed.
At this time, after ashing the resist pattern and the BARC layer, the SH process or the like may be performed.
Here, the embedding target portion 130a has, for example, a shape different from the application targets of the present step such as the plate-shaped contact LI, the contact CC, the columnar portion HR, and the element dividing section DS. For example, when the contacts CC and the columnar portion HR are the application targets, the embedding target portion 130a has a hole shape in which the layer to be processed 100 extends in the vertical direction. In addition, for example, when the plate-shaped contact LI and the element dividing section DS are formed, the embedding target portion 130a has a groove shape extending in the paper depth direction.
As described above, in order to make the shape of the embedding target portion 130a different according to the application target, a predetermined pattern to be formed in the formation region of the auxiliary layer 120a may be set as a hole shape, a groove shape, and the like.
In
Here, an angle formed by a tapered portion with respect to the plane along the XY directions is defined as a taper angle θ.
Here, when the upper surface of the layer to be processed 100 is etched back, etching deposits such as carbon polymer may be deposited on the upper surface of the layer to be processed 100. Since the etching of the upper surface of the layer to be processed 100 is prevented, the upper end of the embedding target portion 130a can be enlarged without changing the thickness of the layer to be processed 100 in the height direction.
Next, in
Here, for example, a material of a predetermined film varies according to the application target of the present step such as the plate-shaped contact LI, the contact CC, the columnar portion HR, and the element dividing section DS. For example, when the contacts CC are formed, the predetermined films are the insulating layer 56 and the conductive layer 22. For example, when the columnar portion HR is formed, the predetermined film is the insulating layer 54. In addition, for example, when the plate-shaped contact LI is formed, the predetermined films are the insulating layer 55 and the conductive layer 21. Also, when the element dividing section DS is formed, the predetermined film is the insulating layer 58.
The semiconductor device 1 according to the embodiment is manufactured by flattening the upper surface of the layer to be processed 100 of which the predetermined film is formed by CMP and then repeating the formation of various films and processes of these films using photolithography technology and etching technology.
(Overview)
If the stacking number of the stacked body of the semiconductor device is increased, aspect ratios of patterns of a plate-shaped contact, a contact connected to a word line, a columnar portion supporting a stacked body, and the like may be increased. Also, due to the increase of the stacking number of the stacked body, the number of the memory cells formed in the stacked body also increases, and the number of transistors in the peripheral circuit increases. Accordingly, the density of the transistors in the peripheral circuit increases, and the element dividing sections have to be located densely in a narrow area, so that the aspect ratio of the element dividing section tends to also increase. For example, when the predetermined film is embedded in the pattern as described above having the bowing shape, before the inside of the pattern is filled with the predetermined film, the upper end of the pattern is blocked by the predetermined film to obstruct the embedding of the inside the pattern, so that cavities or the like may be formed in the pattern.
In this manner, if the predetermined film that is a filling material has cavities in the pattern, a stress may be caused in the predetermined film or in configurations in the periphery thereof. Due to such a stress, for example, a positional deviation may occur when various configurations are further formed on the stacked body, inclination may be formed in the pattern in which the predetermined film is embedded or in configurations in the periphery thereof, or warpage may occur in the substrate SB. Also, the embedded predetermined film may be peeled off due to tensile stress, to cause a decrease in the yield of the semiconductor device.
In order to resolve such an embedding failure, for example, a step of opening a blocked portion by etching the pattern in which the embedding failure occurs again and forming the predetermined film again has been repeated.
However, since the step including etching is repeated, not only the blocked upper end of the pattern or the like but also a region to which etching is not required, such as a region in which a pattern is not formed, may be damaged. In addition, due to the increase in the number of steps, a processing cost increases, and a time cost required for constructing such a complicated process also increases.
In the semiconductor device 1 according to Embodiment 1, by including the auxiliary layers 120a having a low etching resistance that fill the recess 110a of the upper surface of the layer to be processed 100, the embedding target portion 130a has a forwardly tapered shape in which a width and a diameter in the XY direction decrease toward the depth direction of the layer to be processed 100. Accordingly, an embedding failure in a pattern having a high aspect is prevented, so that the predetermined film can be easily filled.
(Modification 1)
Next, by using
In order to obtain the configuration illustrated in
As illustrated in
Meanwhile, in the example illustrated in
In addition,
The process of
The semiconductor device according to Modification 1 includes auxiliary layers that are shared between a plurality of configurations. By using such auxiliary layers, it is not necessary to precisely dispose recess portions for forming the auxiliary layers to individual configurations and it is possible to obtain a configuration including the auxiliary layers more simply.
In the semiconductor device according to Modification 1, the same effect as in the method of manufacturing the semiconductor device 1 according to Embodiment 1 described above is also exhibited.
(Modification 2)
Next, by using
The auxiliary layer 120a illustrated in
As illustrated in
An auxiliary layer 120b illustrated in
As illustrated in
An auxiliary layer 120c illustrated in
By using a film that is etched much more difficultly than the auxiliary layer 120b as the auxiliary layer 120c, the embedding target portion 130c having a taper angle θc smaller than the taper angle θb is obtained.
That is, at this time, a following relationship provided below is satisfied between the taper angles θa to θc.
θa>θb>θc
In this manner, the taper angles θa to θc, that is expansion statuses of the upper ends of the embedding target portions 130a to 130c when being etched back by using different types of films as the auxiliary layers 120a to 120c may be changed. Accordingly, it is possible to easily embed a predetermined film to embedding target portions having different depths and widths with the embedding failure prevented.
According to the semiconductor device of Modification 2, the same effect as in the method of manufacturing the semiconductor device 1 according to Embodiment 1 as described above is exhibited.
In addition, the auxiliary layers 120a to 120c illustrated in
Otherwise, the recesses (not illustrated) for filling the auxiliary layers 120a to 120c illustrated in
In this case, since it is not necessary to protect other recesses except for the recesses to be formation targets of any of the auxiliary layers 120a to 120c with the resist layers or the like, a step that depends on the thickness of the resist layer or the like is not formed at the boundary between the region in which the recess is formed and the region that is protected by the resist layer or the like.
If such a step is formed, etching ions cannot reach a lower portion of the step, and film residues are formed in the auxiliary layers 120a to 120c to cause dust in subsequent steps.
By independently forming the recesses (not illustrated) to be filled with the auxiliary layers 120a to 120c whenever forming each of the auxiliary layers 120a to 120c, it is possible to prevent generation of film residues and dusts as described above.
Further, even when layers of the same kind are used, the auxiliary layers 120a to 120c having different etching resistances may be formed, for example, by changing the film deposition temperature. For example, even P-dTEOS, which is relatively easily etched, the layer becomes denser by raising the film deposition temperature, so that a film quality that is difficultly to be etched can be obtained.
(Modification 3)
Next, the semiconductor device according to Modification 3 of Embodiment 1 is described with reference to
Also, in the description of
As illustrated in
As illustrated in
As illustrated in
That is, at this time, a following relationship is satisfied between the taper angles θa, θd, and θe.
θa>θd>θe
In this manner, by using the auxiliary layers 120a, 120d, and 120e having different widths and depths, the taper angles θa, θd, and θe at the time of being etched back, that is, the expansion statuses of the upper ends of the embedding target portions 130a, 130d, and 130e may be changed. Accordingly, the predetermined films can be easily embedded to the embedding target portions in a tapered shape having different depths and widths at an upper end portion with embedding failure prevented.
In addition, the auxiliary layers 120a, 120d, and 120e illustrated in
That is, for example, by changing the exposure dose and the depth of focus during formation of the resist pattern, the size of the resist pattern opening is changed so that the shape of the recess may be adjusted.
Further, for example, when performing the recess etching process, the shape of the recess may be adjusted by increasing or decreasing a side wall protecting layer deposited on the processing surface of the layer to be processed 100 that is the process target, that is, the deposition amount of the by-product by the plasma reaction. For example, if the side wall protecting layer becomes thick, the shape of the recess becomes the tapered shape, and if the side wall protecting layer is thin, the shape of the recess becomes a straight shape or a bowing shape.
In addition, for example, after the completion of etching and asking the layer to be processed 100, dilute hydrogen fluoride (DHF) or buffered hydrogen fluoride (BHF) washing is performed, the shape of the recess may be adjusted by the processing time. For example, if the processing time is extended, the recess expands horizontally, and if the processing time is shortened, the expansion of the recess can be reduced.
Embodiment 2 is described in detail below with reference to the drawings. Embodiment 2 is different from Embodiment 1 described above in that an auxiliary layer is formed by etching back, instead of the CMP.
First, the procedure illustrated in
As illustrated in
As illustrated in
At this time, by forming the auxiliary layers 120a, for example, by a CVD method, the auxiliary layer 120a is formed in a substantially uniform thickness along the bottom surface and side walls of the recess 110h and the upper surface of the layer to be processed 100. Therefore, a new recess 112h having a size corresponding to the shape of the recess 110h is formed in the recess 110h on the front surface of the auxiliary layer 120a. That is, the width and depth of the recess 112h is different from the width and the depth of the recess 110h and the thickness of the auxiliary layer 120a. For example, if the recess 110h of the layer to be processed 100 is shallow, the width and depth of the recess 112h on the front surface of the auxiliary layer 120c becomes small, and if the recess 110h of the layer to be processed 100 is deep, the width and depth of the recess 112h on the front surface of the auxiliary layer 120a becomes large. In addition, for example, if the thickness of the auxiliary layer 120a is thick, the width and depth of the recess 112h becomes small, and if the thickness of the auxiliary layer 120a is thin, the width and depth of the recess 112h becomes large.
After forming the auxiliary layer 120a having the recess 112h on the front surface, the entire upper surface of the auxiliary layer 120a is etched back by using the auxiliary layer 120a as the process target.
Than, as illustrated in
Next, the layer to be processed 100 is etched back as the process target. Then, a portion in which the layer to be processed 100 is exposed in the recess 110h is gradually removed by etching in the depth direction of the layer to be processed 100. At this time, the auxiliary layer 120a remaining on the side wall of the recess 110h plays a role of a mask, and an etching shape such as a hole shape or a groove shape is obtained according to the shape of the recess 110h formed on the layer to be processed 100 in the layer to be processed 100. However, as described above, a material having a low etching resistance is used for the auxiliary layer 120a. Therefore, as etching advances in the depth direction of the layer to be processed 100, a portion in the auxiliary layer 120a remaining on the side wall of the recess 110h is etched, and the embedding target portion 130a in which the upper end portion is enlarged in the XY direction is formed as illustrated in
Next, the procedure of
As illustrated in
Next, a BARC layer and a resist layer (not illustrated) are formed on the upper surface of the layer to be processed 100 again, and a resist pattern (not illustrated) is formed at the position D by performing the exposure and development process. Also at this point, the position C is kept being covered with the BARC layer and the resist layer (not illustrated). By performing etching and ashing by using the layer to be processed 100 as the process target, a recess 110j as illustrated in
As illustrated in
At this time, a new recess 112j having a size corresponding to the shape of the recess 110h is formed in the recess 110j. Therefore, the depth of the recess 112j is shallower than the depth of the recess 112h formed in
The entire upper surface of the auxiliary layer 120c is etched back by using the auxiliary layer 120c as the process target.
Then, as illustrated in
Next, the layer to be processed 100 is used as the process target and etched back. Then, the embedding target portion 130f in which the upper end portion is enlarged in the XY direction is formed as illustrated in
In this manner, the embedding target portions having different taper angles can be formed on the same layer to be processed 100.
In the method of manufacturing the semiconductor device according to Embodiment 2, by providing the recesses 110h and 110j of different types on the same layer to be processed 100, the auxiliary layers 120a having different widths and depths can be formed. Accordingly, it is possible to fill the embedding target portions of different types with the predetermined film at once, while the embedding failure is prevented.
In the method of manufacturing the semiconductor device according to Embodiment 2, the same effect as the method of manufacturing the semiconductor device 1 of Embodiment 1 described above is exhibited.
Hereinafter, Embodiment 3 is described in detail below with reference to the drawings. Embodiment 3 is different from Embodiment 1 described above in that the auxiliary layer is removed by a wet process.
First, the procedure of
As illustrated in
A spin on carbon (SOC) layer 230 covers the entire upper surface of the layer to be processed 100. The SOC layer 230 is an organic layer formed by the spin coating method. Next, a spin on glass (SOG) layer 250 that covers the SOC layer 230 is formed. The SOG layer 250 is a silicon oxide layer formed by the spin coating method. Also, by forming the resist layer that covers the SOG layer 250, the resist pattern 270p is formed by performing the exposure and development process. Accordingly, a three-layer resist structure to be a mask at the time of processing the layer to be processed 100 is formed.
In
Next, by using the auxiliary layer 120a in which the embedding target portion 130g is formed as the process target, a chemical treatment using a treatment liquid such as hydrofluoric acid is performed. Accordingly, the auxiliary layer 120a is dissolved by the treatment liquid and removed.
In
Next, the procedures of
As illustrated in
In
In
The auxiliary layer 120a is removed by performing a chemical treatment using hydrofluoric acid or the like.
In
In addition, in Embodiment 3 described above, in order to form the resist pattern 270p, the stacked structure of the SOC layer 230 and the SOG layer 250 is used, but the present disclosure is not limited thereto. That is, a stacked film of a carbon film, an SiCN film, and the like formed by the CVD method may be formed on the lower layer of the resist pattern 270p.
According to the method of manufacturing the semiconductor device of Embodiment 3, after forming the embedding target portions 130g and 130h, the auxiliary layer 120a is removed, and the recesses 110h and 110j are exposed. If the layer to be processed 100 is etched back from the upper surfaces of the exposed recesses 110h and 110j, a portion in the recesses 110h and 110j is etched, and the embedding target portion of which the upper end portion expands in the XY direction is formed. Accordingly, the embedding failure is prevented, and it is possible to easily fill the predetermined film.
In the method of manufacturing the semiconductor device according to Embodiment 3, the same effect as the method of manufacturing the semiconductor device 1 according to Embodiment 1 described above is exhibited.
In Embodiments 1 and 2 and the modifications thereof described above, the BARC layer 200 is used for forming the resist pattern 270p. However, the present disclosure is not limited thereto. In Embodiments 1 and 2 described above, for example, the three-layer resist structure according to Embodiment 3 may be used as a mask. Also, at this time, a carbon film and an SiCN film formed by the CVD method may be provided on the lower layer of the resist pattern 270p.
In Embodiments 1 to 3 and the modifications thereof described above, the formation targets of the auxiliary layer 120a are described by using the plate-shaped contact LI, the contact CC, the columnar portion HR, and the element dividing section DS. However, the present disclosure is not limited thereto. The configurations of these embodiments can be applied to a groove that prevents an inflow of a removing liquid of the insulating layer to the through contact region TP when the through contact region TP is interposed from the both sides in the Y direction, and then the word lines WL are formed in the stacked body.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
Number | Date | Country | Kind |
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2022-149903 | Sep 2022 | JP | national |