Semiconductor device and method of manufacturing the same

Abstract

According to the present invention, it is possible to isolate elements from each other without formation of STI and integrate the elements at a high density. A step is formed on a surface of a silicon substrate so as to provide different surfaces. Transistors are formed on the respective different surfaces. The transistors are insulated from each other by a silicon layer and an insulating sidewall. Since no STI is formed between the transistors, it is possible to integrate the transistors at a high density.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view explanatory of a conventional manufacturing process of a semiconductor device with use of STI;

FIG. 2 is a view explanatory of a process to be performed after the process shown in FIG. 1;

FIG. 3 is a view explanatory of a process to be performed after the process shown in FIG. 2;

FIG. 4 is a view explanatory of a process to be performed after the process shown in FIG. 3;

FIG. 5 is a cross-sectional view explanatory of a semiconductor device manufactured with use of conventional STI technology;

FIG. 6 is a plan view of the semiconductor device shown in FIG. 5;

FIG. 7 is a view showing a schematic arrangement of a semiconductor device according to an embodiment of the present invention;

FIG. 8 is a plan view explanatory of a semiconductor device according to the present invention;

FIG. 9 is a cross-sectional view of the semiconductor device taken along line C-C of FIG. 8;

FIG. 10 is a view explanatory of a process in a method of manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 11 is a view explanatory of a process to be performed after the process shown in FIG. 10;

FIG. 12 is a view explanatory of a process to be performed after the process shown in FIG. 11;

FIG. 13 is a view explanatory of a process to be performed after the process shown in FIG. 12;

FIG. 14 is a view explanatory of a process to be performed after the process shown in FIG. 13;

FIG. 15 is a view explanatory of a semiconductor device according to an embodiment of the present invention;

FIG. 16 is a view explanatory of a process in a method of manufacturing a semiconductor device according to another embodiment of the present invention;

FIG. 17 is a view explanatory of a process to be performed after the process shown in FIG. 16; and

FIG. 18 is a view explanatory of a process to be performed after the process shown in FIG. 17.

Claims

1. A semiconductor device comprising: a first transistor formed on a first silicon surface; anda second transistor formed on a second silicon surface located at a height different from a height of the first silicon surface, said first transistor and said second transistor being insulated from each other.

2. The semiconductor device as recited in claim 1, further comprising a silicon substrate having a surface forming the first silicon surface; anda silicon layer formed on a surface of said silicon substrate by epitaxial growth, said silicon layer having a surface forming the second silicon surface located higher than the first silicon surface.

3. The semiconductor device as recited in claim 1, including no STI provided between said first transistor and said second transistor.

4. The semiconductor device as recited in claim 2, further comprising: a lower transistor group including a plurality of said first transistors; andan upper transistor group including a plurality of said second transistors,wherein the first silicon surface and the second silicon surface are arranged alternately in a row direction and a column direction perpendicular to each other in a plan view,wherein said first transistors on the first silicon surface and said second transistors on the second silicon surface are staggered in the plan view.

5. The semiconductor device as recited in claim 4, further comprising a sidewall of an insulator film between a region for said second transistor formed on the second silicon surface and a region for said first transistor formed on the first silicon surface.

6. The semiconductor device as recited in claim 5, wherein each of said first transistor and said second transistor comprises a MOS transistor having the same conductivity.

7. The semiconductor device as recited in claim 6, wherein each of said first transistors in said lower transistor group includes a first gate portion having stacked partial gates, wherein each of said second transistors in said upper transistor group includes a second gate portion having a single-stage structure.

8. The semiconductor device as recited in claim 7, wherein an upper surface of said first gate portion in each of said first transistors and an upper surface of said second gate portion in each of said second transistors are located on substantially the same plane.

9. The semiconductor device as recited in claim 8, further comprising a common gate electrode formed on the same plane as said upper surfaces of said first gate portions and said second gate portions so as to interconnect said first gate portions and said second gate portions of said first transistors and said second transistors arranged alternately in the column direction.

10. The semiconductor device as recited in claim 9, wherein said silicon substrate comprises a p-type silicon substrate, wherein each of said first transistors and said second transistors comprises an NMOS transistor.

11. The semiconductor device as recited in claim 5, wherein said first transistors and said second transistors comprise CMOS transistors formed by different conductive types of transistors.

12. The semiconductor device as recited in claim 11, wherein each of said first transistors in said lower transistor group includes a first gate portion having stacked partial gates, wherein each of said second transistors in said upper transistor group includes a second gate portion having a single-stage structure.

13. The semiconductor device as recited in claim 12, wherein an upper surface of said first gate portion in each of said first transistors and an upper surface of said second gate portion in each of said second transistors are located on substantially the same plane.

14. The semiconductor device as recited in claim 13, further comprising a common gate electrode formed on the same plane so as to interconnect said first gate portions and said second gate portions of said first transistors and said second transistors arranged alternately in the column direction.

15. The semiconductor device as recited in claim 14, wherein said silicon substrate comprises a p-type silicon substrate, wherein each of said first transistors comprises an NMOS transistor,wherein each of said second transistors comprises a PMOS transistor.

16. A semiconductor device comprising: a silicon substrate;a first transistor formed on said silicon substrate;a silicon layer formed adjacent to said first transistor on a surface of said silicon substrate by selective epitaxial growth; anda second transistor formed on said silicon layer so as to be isolated from said first transistor by said silicon layer.

17. The semiconductor device as recited in claim 16, further comprising a sidewall of an insulator film formed on a side surface of said silicon layer.

18. The semiconductor device as recited in claim 17, wherein a first distance between an edge of a first gate portion of said first transistor and said sidewall is substantially the same as a second distance between an edge of a second gate portion of said second transistor and said sidewall.

19. The semiconductor device as recited in claim 18, further comprising: a first insulator film covering said first transistor; anda second insulator film covering said first transistor and said second transistor and having substantially the same height as a height of said first insulator film.

20. A method of manufacturing a semiconductor device, said method comprising: forming a first silicon surface and a second silicon surface located at different heights on a silicon substrate;forming a first transistor on the first silicon surface; andforming a second transistor on the second silicon surface.

21. The method as recited in claim 20, wherein said forming process of the first silicon surface and the second silicon surface includes performing selective epitaxial growth on the silicon substrate defining the first silicon surface so as to form the second silicon surface located higher than the first silicon surface.

22. The method as recited in claim 20, wherein said forming process of the first silicon surface and the second silicon surface includes arranging the first silicon surface and the second silicon surface alternately in a row direction and a column direction perpendicular to each other in a plan view.

23. The method as recited in claim 22, further comprising forming an insulator film for insulating the first transistor formed on the first silicon surface and the second transistor formed on the second silicon surface from each other.

24. The method as recited in claim 20, wherein said forming process of the first transistor includes: forming a first gate portion on the first silicon surface, andforming source and drain regions on the first silicon surface,wherein said forming process of the second transistor includes:forming a second gate portion on the second silicon surface, andforming source and drain regions on the second silicon surface.

25. The method as recited in claim 24, wherein said forming process of the first gate portion of the first transistor includes: forming a lower gate part,forming a contact plug on the lower gate part, andforming an upper gate part on the contact plug,wherein said forming process of the second gate portion of the second transistor is performed during said forming process of the upper gate part of the first gate portion.

26. The method as recited in claim 22, wherein said arranging process of the first silicon surface and the second silicon surface includes: forming a lower gate part including a gate insulator film, a gate electrode, and a cover insulator film on a surface of the silicon substrate,forming source and drain diffusion layers on the surface of the silicon substrate,forming a first insulator film on an entire surface of the silicon substrate so as to cover the lower gate part with the first insulator film, anddry-etching the first insulator film until the surface of the silicon substrate is exposed with the lower gate part being embedded in the first insulator film.

27. The method as recited in claim 26, wherein said dry-etching process of the first insulator film includes etching the first insulator film deeper than a height of the source and drain diffusion layers formed on the surface of the silicon substrate.

28. The method as recited in claim 27, further comprising forming a sidewall of an insulator film on a side surface of the first insulator film after said dry-etching process of the first insulator film.

29. The method as recited in claim 28, wherein the sidewall of the insulator film includes a single layer of a silicon nitride film or a silicon oxide film or a two-layer film of a silicon nitride film and a silicon oxide film formed on the silicon nitride film.