This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2010-211377, filed Sep. 21, 2010, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and a method of manufacturing the same.
In order to manufacture semiconductor chips, semiconductor chips are formed on a substrate through a common process, and then they are divided. Such a dividing step is called dicing, for example. A boundary area is provided between chips and is called a dicing line, or a dicing area, for example. The dicing lines generally include no components formed therein. The dicing involves irradiation of the dicing line with a laser beam to cause damage, i.e., faults, in the dicing line in the substrate, on which target patterns are generally formed as marks for correct alignment of the laser. The damage caused by the irradiation of the laser deteriorates the mechanical strength of the substrate in the dicing line. Mechanical stress is then applied to the substrate to produce a crack that originates at the laser cut faults, which allows for chips to be divided.
In order to satisfy the need to manufacture more chips from a substrate, a size of a dicing line is continuously being required to be made smaller. However, decreasing the dicing line size makes it more difficult to control the dicing.
In general, according to one embodiment, a semiconductor device includes a semiconductor substrate which includes a first chip area and a second chip area. An insulation film is formed over the substrate. An electrical circuit is formed in the first chip area and is electrically independent from any component in another chip area. The electrical circuit includes an electrical element and an interconnect on the substrate and in the insulation film. Boundary patterns are formed in the insulation film between the first and second chip areas, are electrically independent from the electrical circuit, and have a gap therebetween. One of the boundary patterns surrounds the first chip area.
Embodiments of the present invention will now be described with reference to the drawings. In the following, the same components are indicated with the same reference numbers throughout the figures, and repetitive description will be given only when required. Note that the drawings are merely illustrative and a ratio of the relation between a thickness and a plane size and thicknesses among layers differs from an actual one. Therefore, a specific thickness and size should be determined in light of the following description. Moreover, the drawings naturally include portions which differ in size or a size relative to another portion among drawings.
As shown in
The upper surface of the substrate 1 is covered with an inter-layer film 11 of an insulation material. A specific material of the inter-layer film 11 is known for a person skilled in the art. The interconnect 5 is located on the inter-layer film 11, and the plug 6 extends through the inter-layer film 11 and electrically connects a source/drain area of the transistor 4 and the interconnect 5.
A pair of boundary patterns 12 is provided on the inter-layer film 11 in each dicing line 3. The boundary patterns 12 comprise the same layer as the interconnect 5, and are patterned by the same process as the interconnect 5. For this reason, the boundary patterns 12 are typically flush with the interconnect 5. The plane shapes (the shape along the surface of the substrate 1) of the boundary patterns 12 extend along the both ends of each dicing line 3. The boundary patterns 12 make no contribution to transmission of electrical signals, and therefore are electrically independent from any components. The boundary patterns 12 may also be formed from a material different from the interconnect 5.
The upper surface of the inter-layer film 11 is covered with an inter-layer film 13 of an insulation material. A specific material of the inter-layer film 13 is known for a person skilled in the art. Between each pair of boundary patterns 12 extending along the both ends of each dicing line 3, the inter-layer film 13 is not buried and there are voids. One boundary pattern 12 surrounds one chip area 2, and a slit 14 is formed between boundary patterns 12 in each dicing line 3 as shown in
The entire surface of the inter-layer film 13 is covered with a passivation film 15 of an insulation material. A specific material of the passivation film 15 is known for a person skilled in the art. In the passivation film 15, a pad 16 of a conductive material is formed. The passivation film 15 has an opening which reaches the pad 16. In the inter-layer film 13, a plug 17 is provided. The plug 17 connects the pad 16 and the interconnect 5.
A process for producing the structure of
The transistor 4 (not shown) is formed on the substrate 1 through ion implantation, film deposition, and patterning of the film by lithography and etching as shown in
Over the entire upper surface of the structure thus formed so far, the inter-layer film 13 is then deposited as shown in
A mask 21 is then formed on the inter-layer film 13 as shown in
The inter-layer film 13 is then patterned by etching through the mask 21 as shown in
Over the entire upper surface of the structure thus formed so far, a conductive film is then deposited as shown in
A mask 22 is then formed on the passivation film 15 as shown in
A laser is then irradiated to the substrate 1 as shown in
A breaking step is then performed as shown in
As described, the first embodiment involves forming one pair of boundary patterns 12, which form the slit 14 between them, in one dicing line 3 in the inter-layer film 13. Since the breaking starts from the slit 14 in the inter-layer film 13, the breaking track in the inter-layer film 13 coincides with the dicing line 13. In other words, even dicing with the laser can cut up chips at a desired position at least in a region between the substrate 1 and the inter-layer film 13. The breaking track in turn can be prevented from entering the chip area 2 in the inter-layer film 13, which eliminates the necessity for providing a margin for the dicing line width in preparation for such invasion. Therefore, the dicing line 3 can be narrow.
The boundary patterns 12 can also be used for alignment upon dicing. Since the boundary patterns 12 can be seen through a microscope, rough alignment is possible using the boundary patterns 12. This can reduce the time taken for the dicing.
Since the breaking of the chip can be performed more easily than with only laser-cut faults, the number of repetitions of laser irradiations can be decreased. With such decreased number of repetitions, a reduction in manufacturing costs can be expected and a risk of damage to components in the chips which may be caused by the laser can be decreased. In particular, when the semiconductor device is a solid state imaging device, it is an advantage that damage to sensitive components which constitute the solid state imaging device can be avoided.
The second embodiment involves providing boundary patterns and slits also in the passivation film 15.
As for a manufacturing process, the same steps are performed as the first embodiment up to formation of the via for plug 17 in the inter-layer film 13 in
The conductive film is then patterned by etching through the mask into the pad 16 and the boundary patterns 41 as shown in
The passivation film 15 is deposited over the entire upper surface of the structure thus formed so far, as shown in
A mask 22 is then formed on the passivation film 15 as shown in
The laser cutting is the same as that of the first embodiment. It is however different from the first embodiment in that breaking in the passivation film 15 starts from the slit 42. Features not described above are all the same as in the first embodiment.
As described, the second embodiment involves forming one pair of boundary patterns 12, which form the slit 14 between them, in one dicing line 3 in the inter-layer film 13. This provides the same advantages as the first embodiment. In addition, the second embodiment also involves forming one pair of boundary patterns 41, which form the slit 42 between them, in one dicing line 3 in the passivation film 15. Since the breaking in the passivation film 15 starts from the slit 42, the breaking track extends along the dicing line 3 in the passivation film 15 as well as in the inter-layer film 13. Therefore, the breaking can be performed with improved accuracy in a region between the substrate 1 and the passivation film 15.
The third embodiment involves forming a slit, which penetrates through the inter-layer film 13 and the passivation film 15.
Slits 52 are formed above the slits 42 in the passivation film 15. Each slit 52 has a plane shape which extends along the corresponding slit 42, and its cross-sectional structure extends between the upper surface of the passivation film 15 and the corresponding slit 42. Therefore, a set of slits 12, 42, 51, and 52 form a slit, which penetrates from the surface of the passivation film 15 to the surface of the substrate 1.
A manufacturing process is similar to the second embodiment.
The inter-layer film 13 is then patterned by etching through the mask 53 as shown in
A conductive film is then deposited over the entire upper surface of the structure thus formed so far, as shown in
The passivation film 15 is then deposited over the entire upper surface of the structure thus formed so far, as shown in
A mask 54 is then formed on the passivation film 15 as shown in
The laser cutting is the same as in the first embodiment. However, the inter-layer film 13 and the passivation film 15 were already divided into separate chip areas 2 at the time of breaking. Therefore, the substrate 1 is the only target of the breaking. Features not described above are all the same as in the first and second embodiments.
As described, the third embodiment involves forming one pair of boundary patterns 12, which form the slit 14 between them, in one dicing line 3 in the inter-layer film 13. One pair of boundary patterns 41, which form the slit 42 between them, are also formed in one dicing line 3 in the passivation film 15 as in the second embodiment. Therefore, the same advantages as in the first and second embodiments are obtained. In addition, the third embodiment also involves forming a slit from the slits 51 and 52, which penetrates through the inter-layer film 13 and the passivation film 15. This means that the inter-layer film 13 and the passivation film 15 are already divided into separate chip areas 2 at the time of the breaking. For this reason, the breaking track in the inter-layer film 13 and the passivation film 15 can be prevented from entering the chip area 2. Therefore, the breaking can be performed with improved accuracy in a region between the substrate 1 and the passivation film 15.
The fourth embodiment is performed additionally to the first to third embodiments, and involves forming a slot in a substrate along each dicing line.
The contact hole for the plug 6 is formed and a slot 62 is formed in the surface area of the substrate 1 in the dicing line 3 by etching through the mask 61 as shown in
As the following steps, steps of one or more of the first to third embodiments are performed. The laser cutting and breaking are also performed as described for the first embodiment. The breaking of the substrate 1, however, starts from the slot 62 as well as the laser-cut faults. Features not described above are all the same as in the first and third embodiments.
As described above, the fourth embodiment involves forming the slot 62 in the surface region of the substrate 1 in one dicing line 3. The slot 62 serves as the starting point of the breaking on the substrate 1 as well as the laser-cut faults 31. For this reason, the breaking can be performed for the substrate 1 with improved accuracy. This eliminates the necessity for providing the margin for the dicing line width, and can narrow the dicing line 3. Since the fourth embodiment is combined with one of the first to third embodiments, the same advantages as the combined embodiment can also be obtained.
The fifth embodiment is performed additionally to the first to third embodiments, and involves forming a slot in a conductive material on the substrate 1 along each dicing line.
As the following steps, steps of one or more of the first to fourth embodiments are performed. The laser cutting and breaking are also performed as described for the first embodiment. Features not described above are all the same as in the first and third embodiments.
As described above, the fifth embodiment is combined with one or more of the first to fourth embodiments. Therefore, the same advantage as the combined embodiment can be obtained.
When mechanical stress is applied to the substrate 101 after the laser cutting, a breaking track may deviate from a corresponding dicing line in an inter-layer film 104 and a passivation film 105 as shown in
This is because the laser-cut faults are not formed in the inter-layer film 104 or the passivation film 105 and the breaking in them is only performed with the mechanical stress but without assistance of laser-cut faults. With the deviation of the breaking track 107 from a desired position in the inter-layer film 104 and the passivation film 105, interconnects and plugs may be deformed to result in loss of electrical connection. One possible measure to avoid such intrusion by the breaking track 107 into a chip area is to widen the dicing line. This measure enables the widened margin to serve as an area used as a buffer to prevent the breaking track which has entered the chip area from reaching electrical components. This technique is, however, counter to the request to reduce a dicing line width. Thus, there is a need for a countermeasure other than widening the dicing line to provide the margin.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2010-211377 | Sep 2010 | JP | national |