Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the attached drawings.
The semiconductor device according to an embodiment of the present invention will be described by exemplifying a memory cell transistor in DRAM as a semiconductor device 10. The memory cell transistor in the DRAM is required to have a high threshold voltage. Also, it is required to have a low leakage current in an OFF state of the memory cell transistor.
The semiconductor device 10 has a silicon substrate 101, device separating oxide films 102, a gate insulating film 110, a gate electrode 104 and contacts 111. A convex portion 109 is provided on the silicon substrate 101. The convex portion 109 may be stacked on the substrate 101 or formed as a part of the substrate 101. The convex portion 109 is provided to extend in a first direction, as shown in
The device separating oxide films 102 are formed on both sides of the convex portion 109 on the silicon substrate 101 to extend in the first direction. The height of the device separating oxide film 102 is lower than the height of the convex portion 109. Therefore, the upper portion of the convex portion 109 upwardly protrudes from the device separating oxide films 102. The height H of the convex portion 109 protruding from the device separating oxide film 102 is in a range of 10 and 100 nm. The device separating oxide film 102 is a silicon oxide film.
An impurity doped layer 106 is formed in a surface portion i.e., side surface portions and an upper surface portion, of the convex portion 109 protruding from the device separating oxide films 102 between source and drain regions 112. The impurity doped layer 106 is a semiconductor layer in which N-type impurity such as P+ and As+ is doped. An amount of the N-type impurity doped in the impurity doped layer 106 is determined in accordance with a required threshold voltage.
The gate insulating film 110 is provided to cover a part of the surface portion of the convex portion 109, i.e., the side surfaces portions and the upper surface portion of the convex portion 109. The convex portion 109 on the silicon substrate 101 is exposed on both sides of the gate insulating film 110 in the first direction. The exposed portions of the convex portion 109 serve as the source and drain regions 112 in which P-type impurity is doped. A silicon oxide film 103 is formed on the impurity doped layer 106 to cover the surface portion of the convex portion 109 and a silicon nitride film 105 is laminated on the silicon oxide film 103. Thus, the gate insulating film 110 has a 2-layer structure, as shown in
The gate electrode 104 is provided on a part of the convex portion 109 through the gate insulating film 100 to cover the part of the gate insulating film 100. The length of the gate electrode 104 in the first direction is shorter than the length of the gate insulating film 110. That is, the gate insulating film 110 is configured to project from the both sides of the gate electrode 104 in the first direction. It should be noted that the length L of the gate electrode 104 is in a range of 10 and 100 nm, for example. The gate electrode 104 is a P-type polysilicon film in which boron ions are doped.
Each of the contacts 111 is connected onto one of the gate electrode 104 and the source and drain regions 112. It should be noted that the contacts 111 are formed to be embedded in an inter-layer insulating film (not shown).
The semiconductor device 10 according to this embodiment is a FinFET having the above convex (fin) portion. The P-type polysilicon film is used as the gate electrode 104, and the impurity doped layer 106 of the N-type is provided between an active region and the gate insulating film 110. Thus, the threshold voltage can be set to a desirable value depending on the impurity concentration of the impurity doped layer 106. At this time, the conductive type of the impurity doped layer 106 is opposite to that of the region outside the impurity doped layer 106. Therefore, the width of a depletion layer formed when a bias is applied to the gate electrode can be made wider. Thus, while maintaining the desirable threshold voltage, it becomes easy to deplete the channel region. Also, when the P-type polysilicon is used for the gate electrode 104, there is a fear that the impurity ions doped into the gate electrode 104 diffuse through the gate insulating film into the channel region to vary the threshold voltage. However, since the structure of the gate insulating film 110 is devised, the diffusion is suppressed.
Next, a method of manufacturing the semiconductor device according to this embodiment will be described.
The device separating oxide films 102 are formed on the silicon substrate 101 as silicon oxide films and removed to dig down by etching, so that a part of the silicon substrate is protruded from the device separating oxide films 102 to form a fin structure. Thus, the convex portion 109 is formed.
A thermal process (annealing) is carried out in hydrogen atmosphere. Consequently, the corner of the convex portion 109 is rounded. In this way, since the corner is rounded, the convergence of the electric field can be protected.
Subsequently, the surface portion of the convex portion 109 is oxidized. A sacrifice oxide film 113 is formed to have the film thickness of several nm (step S13). The sacrifice oxide film 113 is preferably formed through In-Situ Steam Generation (ISSG) oxidization in which the plane direction dependence of an oxidization rate is very small, or plasma oxidization. Since the oxidization is performed by such a method, the sacrifice oxide film 113 can be uniformly formed on the top surface and side surfaces of the convex portion 109.
Subsequently, the P-type impurity ions are implanted into the convex portion 109. Thus, a P-type well layer (P-type semiconductor layer) is formed in the convex portion 109 (step S14).
Subsequently, the N-type impurity ions are implanted into the upper surface portion and side surface portions of the convex portion 109. Consequently, the impurity doped layer 106 is formed. At this time, the N-type impurity ions are preferably implanted at a certain angle with respect to the surface of the substrate 101, and the N-type impurity ions are not implanted from a vertical direction. Since the impurity ions are implanted at the certain angle, the impurity doped layer 106 can be uniformly formed on the upper surface portion and side surface portions of the convex portion 109.
Subsequently, a wet etching is carried out to remove the sacrifice oxide film 113. Then, the silicon oxide film 103 is deposited to cover the upper surface and side surfaces of the convex portion 109 and the surfaces of the device separating oxide film 102. Several nm are exemplified as the film thickness of the silicon oxide film 103. The oxidization at this time is preferably performed by the ISSG oxidization or plasma oxidization, similarly to the formation of the sacrifice oxide film as mentioned above, in order to attain the uniform formation of the convex portion 109.
Subsequently, the silicon oxynitride film 105 is formed on the silicon oxide film 103. The silicon oxynitride film is formed by a substrate bias plasma nitriding method. The substrate bias plasma nitriding method is a method of applying the bias to the silicon substrate 101 and depositing the silicon oxynitride film 105. In a usual plasma nitriding method, since the bias is not applied to the substrate side, it is difficult to uniformly oxynitride the upper and side surfaces of the convex portion 109. However, through the application of the bias to the substrate side, the silicon oxide nitride film can be uniformly deposited.
In the process of S32, the silicon oxynitride film 105 may be replaced with the silicon nitride film having the film thickness of several nm formed by an atomic layer deposition (ALD method). If the gate electrode side of the gate insulating film 110 is formed from the silicon nitride film or silicon oxynitride film, it is possible to suppress the diffusion of the impurity (boron) ions doped into the gate electrode. Also, since the ALD method is excellent in the covering property, the silicon nitride film can be uniformly deposited in the convex portion 109.
Subsequently, a non-doped polysilicon film is deposited on the gate insulating film 110. About 100 nm is exemplified as its thickness of the polysilicon film. Then, as the P-type impurity, the boron ions are implanted into the non-doped polysilicon film. Consequently, the P-type polysilicon film is formed.
A mask oxide film 114 is formed on the P-type polysilicon film deposited by the process of S41. The film thickness of the mask oxide film 114 is exemplified between 10 nm and 100 nm. After the deposition of the mask oxide film 114, a lithography technique is used to pattern the mask oxide film 114, and only the mask oxide film 114 is left on the convex portion 109 in the first direction.
Subsequently, the patterned mask oxide film 114 is used as the mask, and the P-type polysilicon film is dry-etched. Consequently, the gate electrode 104 is formed.
It should be noted that after the formation of the gate electrode 104, the oxidizing process may be performed to form a bird's beak where the thickness of the gate insulating film at end portions of the gate electrode is relatively thick. Through the formation of the bird's beak, electric field in the drain end on the operation can be relaxed.
Next, the gate insulating film 10 is removed on the both sides in the first direction. Then, a mask oxide film is form as a mask by the lithography technique. The N-type impurity ions are implanted into the portions of the convex portion 109 from which the gate insulating film is removed, to form the source and drain regions on both the sides of the gate electrode 104 in the first direction. It should be noted that the implantation of the N-type impurity ions at this time is not required to be the ion implantation. For example, plasma doping can be also used.
Also, at a step S51, the ion implantation of a relatively low concentration is firstly performed. Subsequently, the nitride film of several 10 nm is deposited and etched back, and then the ion implantation of a high concentration is performed. Thus, it is possible to get a lightly doped drain (LDD) structure in which the low concentration regions are formed between the respective source and drain regions and the channel region. In this way, through employment of the LDD structure, it is possible to relax the electric field in the end portions.
Moreover, after the inter-layer insulating film is grown, the contacts are connected to the gate electrode and the respective source and drain regions, and the FinFET is obtained.
As mentioned above, according to this embodiment, the P-type polysilicon film is used as the gate electrode, and the N-type impurity doped layer is provided between the gate insulating film and the channel region, to adjust the threshold voltage. Thus, in addition to the achievement of the desirable threshold voltage, the channel region can be easily depleted.
Also, since the gate insulating film includes the silicon nitride film or silicon oxide film, it is possible to suppress the diffusion of the impurity ions when the P-type polysilicon film is used.
Number | Date | Country | Kind |
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2006-133413 | May 2006 | JP | national |