BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
FIG. 1 is a plan view schematically showing the configuration of a semiconductor device in accordance with a first and second embodiments of the present invention;
FIG. 2 is a diagram showing an equivalent circuit of the semiconductor device in accordance with the first and second embodiments of the present invention;
FIGS. 3A and 3B are sectional views schematically showing part of a method of manufacturing a semiconductor device in accordance with the first embodiment of the present invention;
FIGS. 4A and 4B are sectional views schematically showing part of a method of manufacturing a semiconductor device in accordance with the first embodiment of the present invention;
FIGS. 5A and 5B are sectional views schematically showing part of a method of manufacturing a semiconductor device in accordance with the first embodiment of the present invention;
FIGS. 6A and 6B are sectional views schematically showing part of a method of manufacturing a semiconductor device in accordance with the first embodiment of the present invention;
FIGS. 7A and 7B are sectional views schematically showing part of a method of manufacturing a semiconductor device in accordance with the first embodiment of the present invention;
FIG. 8 is an energy band diagram illustrating a memory cell operation in accordance with the first and second embodiments;
FIG. 9 is an energy band diagram illustrating a memory cell operation in accordance with the first and second embodiments;
FIG. 10 is an energy band diagram illustrating a memory cell operation in accordance with the first and second embodiments;
FIG. 11 is an energy band diagram illustrating a memory cell operation in accordance with the first and second embodiments;
FIG. 12 is a sectional view schematically showing the configuration of a semiconductor device in accordance with the second embodiments of the present invention;
FIG. 13 is a sectional view schematically showing the configuration of a semiconductor device in accordance with a variation of the second embodiment of the present invention;
FIG. 14 is a diagram showing a memory card comprising a NAND type flash memory; and
FIG. 15 is a diagram showing a memory card comprising a NAND type flash memory; and
FIG. 16 is a diagram showing a memory card comprising a NAND type flash memory.