Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device having reduced pitting may be formed from isolation layer patterns on a semiconductor substrate defining an active region, a tunnel oxide layer on the active region, the tunnel oxide layer having a nitrified surface, a floating gate on the tunnel oxide layer, a dielectric layer on the floating gate, and a control gate on the dielectric layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail example embodiments thereof with reference to the attached drawings, in which:

FIGS. 1 to 7 illustrate cross-sectional views of stages in a method of manufacturing a semiconductor device in accordance with example embodiments of the present invention;

FIG. 8A is an electron photomicrograph of a surface of a floating gate in a related art semiconductor device obtained using a scanning electron microscope (SEM);

FIG. 8B is an electron photomicrograph of the surface of the floating gate in the related art semiconductor device obtained using an atomic force microscope (AFM);

FIG. 9A is an electron photomicrograph of a surface of a floating gate in a semiconductor device obtained using an SEM according to an example embodiment of the present invention;

FIG. 9B is an electron photomicrograph of the surface of the floating gate in the semiconductor device obtained using an AFM according to an example embodiment of the present invention;

FIGS. 10A to 10E are electron photomicrographs of cross-sections of floating gates in a related art semiconductor device; and

FIGS. 11A to 11E are electron photomicrographs of cross-sections of floating gates in a semiconductor device according to example embodiments of the present invention.

Claims

1. A semiconductor device, comprising: isolation layer patterns on a semiconductor substrate defining an active region;a tunnel oxide layer on the active region, the tunnel oxide layer having a nitrified surface;a floating gate on the tunnel oxide layer;a dielectric layer on the floating gate; anda control gate on the dielectric layer.

2. The semiconductor device as claimed in claim 1, wherein the floating gate comprises a first floating gate pattern and a second floating gate pattern.

3. The semiconductor device as claimed in claim 2, wherein the first floating gate pattern has a thickness of about 50 Å to about 100 Å, and the second floating gate pattern has a thickness of about 100 Å to about 200 Å.

4. The semiconductor device as claimed in claim 2, wherein the first floating gate pattern includes amorphous silicon having a first impurity concentration and the second floating gate pattern includes amorphous silicon having a second impurity concentration substantially different from the first impurity concentration.

5. The semiconductor device as claimed in claim 2, wherein the first floating gate pattern comprises amorphous silicon without impurities and the second floating gate pattern includes amorphous silicon doped with impurities.

6. The semiconductor device as claimed in claim 2, wherein the first and the second floating gate patterns together have a U shape.

7. The semiconductor device as claimed in claim 2, wherein a thickness ratio between the first floating gate pattern and the second floating gate pattern is in a range of about 1.0:1.0 to about 1.0:4.0.

8. The semiconductor device as claimed in claim 1, wherein the dielectric layer comprises oxide, nitride or metal oxide.

9. The semiconductor device as claimed in claim 1, wherein the dielectric layer comprises an oxide/nitride/oxide (ONO) structure.

10. The semiconductor device as claimed in claim 1, wherein the control gate comprises polysilicon doped with impurities, or metal silicide.

11. A method of manufacturing a semiconductor device, comprising: forming isolation layer patterns on a semiconductor substrate to define an active region;forming a tunnel oxide layer on the active region;nitrifying a surface of the tunnel oxide layer;forming a floating gate on the tunnel oxide layer;forming a dielectric layer on the floating gate; andforming a control gate on the dielectric layer.

12. The method as claimed in claim 11, wherein the tunnel oxide layer is formed by a thermal oxidation process.

13. The method as claimed in claim 11, wherein the nitrified surface of the tunnel oxide layer is formed by a plasma nitration process using a nitrogen-containing plasma.

14. The method as claimed in claim 11, wherein forming the floating gate comprises: forming a first floating gate pattern on the tunnel oxide layer using polysilicon substantially without impurities; andforming a second floating gate pattern on the first floating gate pattern using polysilicon doped with impurities.

15. The method as claimed in claim 14, wherein the first floating gate pattern is formed at a first temperature under a first pressure, and the second floating gate pattern is formed at a second temperature under a second pressure.

16. The method as claimed in claim 15, wherein the first temperature and the first pressure are substantially the same as the second temperature and the second pressure, respectively.

17. The method as claimed in claim 16, wherein the first and the second temperatures are in a range of about 450° C. to about 550° C., and the first and the second pressures are in a range above about 130 Pa.

18. The method as claimed in claim 14, wherein forming the first floating gate pattern and forming the second floating gate pattern are performed in-situ.

19. The method as claimed in claim 14, wherein forming the floating gate further comprises forming a filling layer on the second floating gate pattern.

20. The method as claimed in claim 14, wherein the filling layer is formed using oxide or organic polymer.