The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.
Existing silicon-based transistors have limitations in improving the operating characteristics and scaling down. For example, when an operating voltage and current characteristics are measured in the case of existing silicon-based transistors, a subthreshold swing (SS) value is determined according to the equation below, and it is known that the SS value is limited to about 60 mV/dec.
In this equation, kB indicates a Boltzmann constant, T indicates an absolute temperature, q indicates an elementary charge, CD indicates a capacitance of a depletion layer, and Cins indicates a capacitance of a gate insulator.
With a decrease in the size of a transistor, a power density increases because it is difficult to lower the operating voltage to about 0.8 V or less. Accordingly, there is a limit in scaling down a device.
Provided are a semiconductor device and a method of manufacturing the semiconductor device.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to an aspect of an embodiment, a semiconductor device includes a substrate on which a channel layer is provided; an insulation layer provided on the substrate; a ferroelectric layer provided on the insulation layer; a fixed charge region provided in the ferroelectric layer and containing charges of a predetermined polarity; and a gate provided on the ferroelectric layer, wherein an absolute value of a charge density in the fixed charge region is greater than 0 and less than 5 μC/cm2.
The absolute value of the charge density in the fixed charge region may be greater than 2 μC/cm2 and less than 3 μC/cm2.
A thickness of the fixed charge region may be 1 Å to 10 Å.
The ferroelectric layer may have a dopant concentration gradient in its thickness direction, and the fixed charge region may be defined by a dopant concentration collecting region in the ferroelectric layer.
The dopant may include at least one selected from Al, P, Ca, Sc, V, Cr, Sr, Y, Nb, Mo, Tm, Yb, Lu, Ta, W, B, and Mg.
The ferroelectric layer may have an oxygen vacancy concentration gradient in its thickness direction, and the fixed charge region may be defined by an oxygen vacancy concentration collecting region in the ferroelectric layer.
The fixed charge region may be disposed on an interface between the ferroelectric layer and the insulation layer.
The fixed charge region may be disposed within the ferroelectric layer. The fixed charge region may be disposed adjacent to the interface between the ferroelectric layer and the insulation layer.
The fixed charge region may have a negative (−) charge density in a semiconductor device of a PMOS structure, and have a positive (+) charge density in a semiconductor device of an NMOS structure.
The ferroelectric layer may include a fluorite-based material, a perovskite, aluminum nitride, or magnesium oxide.
The channel layer may include at least one of Si, Ge, SiGe, a Groups III-V semiconductor, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) material, quantum dots, and an organic semiconductor.
A threshold voltage of the semiconductor device may be controlled by adjusting a work function of the gate.
According to an aspect of another embodiment, a semiconductor device includes a substrate on which a channel layer is provided; an insulation layer provided on the substrate; a ferroelectric layer provided on the insulation layer; a dopant concentration collecting region provided in the ferroelectric layer; and a gate provided on the ferroelectric layer, wherein a dopant concentration in the dopant concentration collecting region is greater than 0 and less than 3.1×1013/cm2.
The ferroelectric layer may have a dopant concentration gradient in its thickness direction.
The dopant may include at least one selected from Al, P, Ca, Sc, V, Cr, Sr, Y, Nb, Mo, Tm, Yb, Lu, Ta, W, B, and Mg.
The dopant concentration collecting region may be disposed on an interface between the ferroelectric layer and the insulation layer or within the ferroelectric layer.
According to an aspect of another embodiment, a semiconductor device includes a substrate on which a channel layer is provided; an insulation layer provided on the substrate; a ferroelectric layer provided on the insulation layer; an oxygen vacancy concentration collecting region provided in the ferroelectric layer; and a gate provided on the ferroelectric layer, wherein an oxygen vacancy concentration in the oxygen vacancy concentration collecting region is greater than 0 and less than 1.55×1013/cm2.
The ferroelectric layer may have an oxygen vacancy concentration gradient in its thickness direction.
The oxygen vacancy concentration collecting region may be disposed on an interface between the ferroelectric layer and the insulation layer or within the ferroelectric layer.
The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
Exemplary embodiments will now be described more fully with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements, and, in the drawings, the sizes of elements may be exaggerated for clarity and for convenience of explanation. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein.
When a layer is referred to as being “”on” another layer or substrate, it can be directly on/below/on the left side of/on the right side of the other layer or substrate, or intervening layers may also be present. An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context. The terms “comprises” and/or “comprising” or “includes” and/or “including” when used in this specification, specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements.
The use of the terms “a” and “an” and “the” and similar referents are to be construed to cover both the singular and the plural. The operations that constitute a method described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context, but embodiments are not limited to the stated order.
The terms “unit”, “-er (-or)”, and “module” when used in this specification refers to a unit in which at least one function or operation is performed, and may be implemented as hardware, software, or a combination of hardware and software.
The connecting lines, or connectors shown in the various figures presented are intended to represent exemplary functional relationships and/or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may be present in a practical device.
The use of any and all examples, or exemplary language provided herein, is intended merely to better illuminate the inventive concept and does not pose a limitation on the scope of the present disclosure unless otherwise claimed.
Referring to
The source 121 may be electrically connected to one side of the channel layer 115, and the drain 122 may be electrically connected to the other side of the channel layer 115. The source and drain 121 and 122 may be formed by implanting impurities into different regions of the substrate 110, and a region of the substrate 110 between the source 121 and the drain 122 may be defined as the channel layer 115. The substrate 110 integrally formed with the channel layer 115 may be, for example, a semiconductor substrate including Si, Ge, SiGe, or Group III-V semiconductor.
The insulation layer 130, the ferroelectric layer 140, and the gate 150 are sequentially stacked on the substrate 110. The insulation layer 130 is provided on the substrate 110(in detail, the channel layer 115). The insulation layer 130 may include, for example, silicon oxide, silicon nitride, or the like, but embodiments are not limited thereto.
The ferroelectric layer 140 is provided on the insulation layer 130. The ferroelectric layer 140 may include ferroelectrics, such as a fluorite-based material, a perovskite, aluminum nitride, or magnesium oxide. The ferroelectrics have a spontaneous dipole (electric dipole), namely, spontaneous polarization, because a charge distribution within a unit cell is non-centrosymmetric in a crystallized material structure. The ferroelectrics also have a remnant polarization due to a dipole even in a state where there are no external electric fields. In the ferroelectrics, a direction of polarization may be switched in units of domain by an external electric field.
The gate 150 is provided on the ferroelectric layer 140. The gate 150 may be disposed opposite to the channel layer 115 of the substrate 110. The gate 150 may include, for example, a conductive metal.
In the semiconductor device 100 of
Referring to
As the remnant polarization Pr or the coersive electric field EC increases in the Q-EFE graph of the “S” curved shape, the negative capacitance effect may be increased. Accordingly, performance of the semiconductor device may be more improved by further lowering the SS. As such, the physical property of ferroelectrics, such as the remnant polarization Pr or the coersive electric field EC, is improved by adjusting a method of depositing ferroelectrics or a method of annealing ferroelectrics, leading to an increase in the negative capacitance effect.
Referring to
Referring to
In the semiconductor device 100 of
Referring to
The source 221 may be electrically connected to one side of the channel layer 215, and the drain 222 may be electrically connected to the other side of the channel layer 215. The source and drain 221 and 222 may be formed by implanting impurities into different regions of the substrate 210, and a region of the substrate 210 between the source 221 and the drain 222 may be defined as the channel layer 215.
The substrate 210 and the channel layer 215 may include Si. However, this is merely an example, and the substrate 210 and the channel layer 215 may include, for example, Ge, SiGe, or Group III-V semiconductor. However, embodiments of the disclosure are not limited thereto. As will be described later, the channel layer 215 may not be formed as a portion of the substrate 210 but may be formed a material layer separate from the substrate 210.
When a p-type semiconductor substrate is used as the substrate 210 and the source and drain 221 and 222 include n-type impurities, a semiconductor device 200 of a NMOS structure may be implemented. When an n-type semiconductor substrate is used as the substrate 210 and the source and drain 221 and 222 include p-type impurities, a semiconductor device 200 of a PMOS structure may be implemented.
The insulation layer 230, the fixed charge region 270, the ferroelectric layer 240, and the gate 250 are sequentially stacked on the substrate 210. The insulation layer 230 is provided on the substrate 210 (in detail, the channel layer 215). The insulation layer 230 may include a paraelectric material or a high-k material. For example, the insulation layer 230 may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, or zirconium oxide or may include a 2D insulator such as h-BN. However, this is merely an example.
The fixed charge region 270 and the ferroelectric layer 240 are sequentially provided on the insulation layer 230. The ferroelectric layer 240 may include ferroelectrics, such as a fluorite-based material, a perovskite, aluminum nitride, or magnesium oxide. The perovskite may include, for example, PZT, BaTiO3, or PbTiO3. The fluorite-based material may include, for example, at least one oxide selected from Hf, Si, Al, Zr, Y, La, Gd, and Sr.
For example, the ferroelectric layer 240 may include at least one of HfO, ZrO, and HfZrO. HfO, ZrO or HfZrO constituting the ferroelectric layer 240 may have a crystal structure of an orthorhombic crystal system. On the other hand, HfO, ZrO or HfZrO constituting the high-k material may have a crystal structure of a monoclinic crystal system. The aforementioned materials are only an example, and various other materials may be used to form the ferroelectric layer 240.
The ferroelectric layer 240 may have a thickness of about 10 Å or greater. For example, in a logic semiconductor device, a ferroelectric layer may have a thickness of about 10 Å to 20 Å, but embodiments are not limited thereto.
The fixed charge region 270 including charges of a predetermined polarity may be provided between the insulation layer 230 and the ferroelectric layer 240. The fixed charge region 270 may have a positive (+) polarity or a negative (−) polarity.
As will be described later, the fixed charge region 270 is provided on an interface between the insulation layer 230 and the ferroelectric layer 240 and thus adjusts the negative capacitance region due to the level of a charge density of the fixed charge region 270, thereby generating a negative capacitance effect in the inversion state of the semiconductor device 200 (in detail, the channel layer 215). To this end, an absolute value of the charge density in the fixed charge region 270 may be greater than 0 and less than 5 μC/cm2. For example, the absolute value of the charge density in the fixed charge region 270 may be greater than 2 μC/cm2 and less than 3 μC/cm2.
The fixed charge region 270 may have, for example, a predetermined positive (+) charge density or a predetermined negative (−) charge density. In detail, the fixed charge region 270 of the semiconductor device 200 of a PMOS structure may have a negative (−) charge density. The negative (−) charge density may be greater than about −5 μC/cm2 and less than 0. For example, the negative (−) charge density may be greater than −3 μC/cm2 and less than −2 μC/cm2. The fixed charge region 270 of the semiconductor device 200 of an NMOS structure may have a positive (+) charge density. The positive (+) charge density may be greater than 0 and less than +5 μC/cm2. For example, the positive (+) charge density may be greater than +2 μC/cm2 and less than +3 μC/cm2. The fixed charge region 270 may have a thickness of approximately 1 Å to 10 Å. For example, the fixed charge region 270 may have a thickness of approximately 1 Å to 5 Å (e,g., 1 Å to 3 Å). However, embodiments are not limited thereto
As will be described later, the fixed charge region 270 may be formed by depositing a dopant including charges of a predetermined polarity on a surface of the insulation layer 230. The dopant may include at least one selected from, for example, Al, P, Ca, Sc, V, Cr, Sr, Y, Nb, Mo, Tm, Yb, Lu, Ta, W, B, and Mg. However, embodiments are not limited thereto. In this case, a dopant concentration in the fixed charge region 270 may be greater than 0 and less than 3.1×1013/cm2. The dopant concentration refers to the number of dopant particles per unit area.
The fixed charge region 270 may be formed by creating oxygen vacancy by treating the surface of the insulation layer 230. In this case, an oxygen vacancy concentration in the fixed charge region 270 may be greater than 0 and less than 1.55×1013/cm2. The oxygen vacancy concentration refers to the number of oxygen vacancies per unit area.
The gate 250 is provided on the ferroelectric layer 240. The gate 250 may be disposed opposite to the channel layer 215 of the substrate 210. The gate 250 may include, for example, a conductive metal.
Referring to
Referring to
Referring to
As described above, the semiconductor device 200 of
As a result of measuring the operating voltage of a ferroelectric (Hf) according to the charge density of the fixed charge region 270 in the semiconductor device 200 of a PMOS structure shown in
A case where the fixed charge region 270 has a negative (−) charge density to generate the negative capacitance effect in an inversion state of the semiconductor device 200 when the semiconductor device 200 is a semiconductor device of a PMOS structure has been described with reference to
Referring to
As described above, the semiconductor device 200 according to an embodiment may adjust the negative capacitance region according to a state of the semiconductor device 200 by changing the charge density of the fixed charge region 270. For example, voltage amplification may be maximized by generating the negative capacitance effect in an inversion state of the semiconductor device 200 by using the fixed charge region 270, and thus performance of the semiconductor device 200 may be more improved.
Because the threshold voltage of the semiconductor device 200 may be controlled by adjusting the work function of the gate 250, the threshold voltage of the semiconductor device 200 may be constantly maintained as a desired value by adjusting the work function of the gate 250. The remnant polarization Pr or the coersive electric field Ec of ferroelectrics is increased by adjusting a method of depositing ferroelectrics or a method of annealing ferroelectrics, leading to an improvement in the negative capacitance effect.
The charge density in the fixed charge region 270 may be calculated, for example, using a measurement method using an S-curve, which represents a correlation between the charge Q of the ferroelectric and the electric field EFE applied to the ferroelectric. The measurement method using the S-curve is well known to those skilled in the art, and is described in detail in, for example, Michael Hoffmann et al: “Unveiling the double-well energy landscape in a ferroelectric layer”, Supplementary Information, Nature (2019).
Referring to
The substrate 310 may include, for example, Si, Ge, SiGe, or Group III-V semiconductor, but embodiments are not limited thereto. The channel layer 315 is provided on an upper surface of the substrate 310. The channel layer 315 may be provided as a material layer separate from the substrate 310. The channel layer 315 may include, for example, Si, Ge, SiGe, or Group III-V semiconductor. The channel layer 315 may include, for example, at least one of an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a 2D material, quantum dots, and an organic semiconductor. The oxide semiconductor may include, for example, InGaZnO, the 2D material may include, for example, transition metal dichalcogenide (TMD) or graphene, and the quantum dots may include colloidal QDs, a nanocrystal structure, or the like. However, this is merely an example, and embodiments of the present disclosure are not limited thereto.
A source 321 and a drain 322 may be formed on both sides of the channel layer 315, respectively. The source 321 may be provided to be connected to one side of the channel layer 315, and the drain 322 may be provided to be connected to the other side of the channel layer 315. The source and drain 321 and 322 may include a conductive material. The insulation layer 330, the fixed charge region 370, the ferroelectric layer 340, and the gate 350 are sequentially stacked on the channel layer 315. This has been described above, and thus a detailed description thereof will be omitted.
Referring to
The substrate 210 and the channel layer 215 may include Si. However, this is merely an example, and the substrate 210 and the channel layer 215 may include, for example, Ge, SiGe, or Group III-V semiconductor. However, embodiments of the present disclosure are not limited thereto, and the material of the substrate 210 may vary. The time point when the source 221 and the drain 222 are formed may vary. For example, after the gate 250 of
As shown in
Next, the insulation layer 230 is formed on an upper surface of the channel layer 215 of the substrate 210. The insulation layer 230 may be formed by depositing a predetermined insulating material on the upper surface of the channel layer 215 of the substrate 210 by using, for example, Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). The insulation layer 230 may include a paraelectric material or a high-k material. For example, the insulation layer 230 may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, or zirconium oxide or may include a 2D insulator such as h-BN. However, this is merely an example.
Referring to
In a semiconductor device of an NMOS structure, the fixed charge region 270 may have a positive (+) charge density, and, in a semiconductor device of a PMOS structure, the fixed charge region 270 may have a negative (−) charge density. For example, in a semiconductor device of a PMOS structure, the fixed charge region 270 may have a negative (−) charge density greater than −5 μC/cm2 and less than 0, and, in a semiconductor device of an NMOS structure, the fixed charge region 270 may have a positive (+) charge density greater than 0 and less than +5 μC/cm2.
The fixed charge region 270 may be formed by depositing a dopant including charges of a predetermined polarity on a surface of the insulation layer 230. The dopant may include at least one selected from, for example, Al, P, Ca, Sc, V, Cr, Sr, Y, Nb, Mo, Tm, Yb, Lu, Ta, W, B, and Mg. However, embodiments of the present disclosure are not limited thereto. The fixed charge region 270 may be formed by processing the upper surface of the insulation layer 230. For example, when the upper surface of the insulation layer 230 is damaged by plasma, ion beams, or the like, an oxygen vacancy is formed on the upper surface of the insulation layer 230, and thus the fixed charge region 270 including charges of a predetermined polarity may be formed.
Referring to
The ferroelectric layer 240 may include ferroelectrics, such as a fluorite-based material, a perovskite, aluminum nitride, or magnesium oxide. The perovskite may include, for example, PZT, BaTiO3, or PbTiO3. The fluorite-based material may include, for example, at least one oxide selected from Hf, Si, Al, Zr, Y, La, Gd, and Sr.
For example, the ferroelectric layer 240 may include at least one of HfO, ZrO, and HfZrO. However, the aforementioned materials are only an example, and various other materials may be used to form the ferroelectric layer 240.
Referring to
Although it has been described above that annealing is performed both when forming the ferroelectric layer 240 and when forming the gate 250, annealing is performed after a predetermined dielectric material and a predetermined conductive metal are deposited on the fixed charge region 270, and thus the ferroelectric layer 240 and the gate 250 may be simultaneously formed.
As described above, an operation of adjusting the work function of the gate 250 may be further performed after the semiconductor device 200 is completed. As described above, when the work function of the gate 250 is adjusted, the threshold voltage of the semiconductor device 200 may be controlled to have a desired value.
In the semiconductor device 200 shown in
Referring to
The ferroelectric layer 740 may include a predetermined dopant. The dopant may include at least one selected from, for example, Al, P, Ca, Sc, V, Cr, Sr, Y, Nb, Mo, Tm, Yb, Lu, Ta, and W, but embodiments are not limited thereto. The ferroelectric layer 740 may have a dopant concentration gradient in its thickness direction. In this case, the fixed charge region 770 may be defined by a region in the ferroelectric layer 740 where the concentration of the dopant collects (i.e., a dopant concentration collecting region).
An absolute value of the charge density in the fixed charge region 770 may be greater than 0 and less than 5 μC/cm2. When this absolute value of the charge density is converted to a dopant concentration, the dopant concentration in the fixed charge region 770, which is defined as the dopant concentration collecting region, may be greater than 0 and less than 3.1×1013/cm2. A thickness of the fixed charge region 770 defined as the dopant concentration collecting region may be approximately 1 Å to 10 Å (e.g., 1 Å to 3 Å). However, embodiments are not limited thereto.
The ferroelectric layer 740 may include oxygen vacancy. The ferroelectric layer 740 may have an oxygen vacancy concentration gradient in its thickness direction. In this case, the fixed charge region 770 may be defined by a region where the concentration of the oxygen vacancy collects (i.e., an oxygen vacancy concentration collecting region).
The absolute value of the charge density in the fixed charge region 770 may be greater than 0 and less than 5 μC/cm2. When this absolute value of the charge density is converted to an oxygen vacancy concentration, the oxygen vacancy concentration in the fixed charge region 770, which is defined as the oxygen vacancy concentration collecting region, may be greater than 0 and less than 1.55×1013/cm2. A thickness of the fixed charge region 770 defined as the oxygen vacancy concentration collecting region may be approximately 1 Å to 10 Å (e.g., 1 Å to 5 Å or 1 Å to 3 Å). However, embodiments are not limited thereto.
A case where the fixed charge region 770 is provided on an interface of the ferroelectric layer 740 in contact with the insulation layer 230 has been described above. However, embodiments are not limited thereto. As will be described later, a fixed charge region may be provided within a ferroelectric layer.
Referring to
The ferroelectric layer 440 may include a predetermined dopant. The ferroelectric layer 440 may have a dopant concentration gradient in its thickness direction. In this case, the fixed charge region 470 may be defined by a region in the ferroelectric layer 440 where the concentration of the dopant collects (i.e., a dopant concentration collecting region). The dopant concentration in the fixed charge region 470, which is defined as the dopant concentration collecting region, may be greater than 0 and less than 3.1×1013/cm2. A thickness of the fixed charge region 470 defined as the dopant concentration collecting region may be approximately 1 Å to 10 Å (e.g., 1 Å to 3 Å). However, embodiments are not limited thereto.
The ferroelectric layer 440 may include oxygen vacancy. The ferroelectric layer 440 may have an oxygen vacancy concentration gradient in its thickness direction. In this case, the fixed charge region 470 may be defined by a region where the concentration of the oxygen vacancy collects (i.e., an oxygen vacancy concentration collecting region). The oxygen vacancy concentration in the fixed charge region 470, which is defined as the oxygen vacancy concentration collecting region, may be greater than 0 and less than 1.55×1013/cm2. A thickness of the fixed charge region 470 defined as the oxygen vacancy concentration collecting region may be approximately 1 Å to 10 Å (e.g., 1 Å to 5 Å or 1 Å to 3 Å). However, embodiments are not limited thereto.
The fixed charge region 470 defined as the dopant concentration collecting region or the oxygen vacancy concentration collecting region may be provided inside the ferroelectric layer 440. In this case, the fixed charge region 470 may be formed adjacent to an interface between the ferroelectric layer 440 and the insulation layer 230.
In detail, when the fixed charge region 470 is disposed inside the ferroelectric layer 440, a location of the fixed charge region 470 capable of generating a negative capacitance effect in the inversion state may be calculated as follows.
For example, assuming that a controllable charge density in the channel layer 215 including Si is 3 μC/cm2, a location of the fixed charge region 470 with a charge density of 5 μC/cm2 capable of controlling the charge density in the channel layer 215 by 3 μC/cm2, that is, a maximum distance t of the fixed charge region 470 away from from the interface between the insulating layer 230 and the ferroelectric layer 440, may be calculated using the following Equation 1.
5 μC/cm2×(TFE−t)=3μC/cm2×TFE . . . Equation 1
It may be seen from Equation 1 that t=0.4×TFE, and, accordingly, it may be seen that, when the fixed charge region 470 is located at a position corresponding to 40% of the thickness TFE of the ferroelectric layer 440 from the interface between the insulation layer 230 and the ferroelectric layer 440, the charge density in the channel layer 215 may be controlled by 3 μC/cm2. For example, when the thickness TFE of the ferroelectric layer 440 is 15 Å, the fixed charge region 470 may be located at a position that is 6 Å away from the interface between the insulation layer 230 and the ferroelectric layer 440.
Referring to
Referring to
A plurality of channel holes are formed to pass through the stacked structure 602, and a ferroelectric layer 640, a gate insulation layer 630, and a channel layer 615 are sequentially arranged in a concentric circle shape inside each of the channel holes to thereby form a memory cell string 603. The ferroelectric layer 640 may be formed to have a thickness of approximately 10 nm to 30 nm (e.g., 10 nm to 20 nm, or 20 nm to 30 nm). The interior of each channel hole may be filled with a dielectric filler 605. The memory cell string 603 is surrounded by the insulation layers 660 and the gates 650. The ferroelectric layer 640, the gate insulation layer 630, and the channel layer 615 may all extend in the Z axis direction and intersect the insulation layers 660 and the gates 650. A plurality of memory cell strings 603 are formed, and may be arranged on the substrate 601 in a 2D manner.
A fixed charge region 670 is provided on an interface between the gate insulation layer 630 and the ferroelectric layer 640 or within the ferroelectric layer 640. Because the fixed charge region 670 has been described above, a detailed description thereof will be omitted.
s described above, a semiconductor device according to an embodiment may adjust a negative capacitance region according to a state of the semiconductor device by adjusting the charge density of a fixed charge region. In other words, voltage amplification may be maximized by generating a negative capacitance effect in an inversion state of the semiconductor device by using the fixed charge region having a predetermined charge density, and thus performance of the semiconductor device may be more improved.
Because the threshold voltage of the semiconductor device may be controlled by adjusting the work function of a gate, the threshold voltage of the semiconductor device may be constantly maintained as a desired value by adjusting the work function of the gate. The remnant polarization Pr or the coersive electric field Ec of ferroelectrics is increased by adjusting a method of depositing ferroelectrics or a method of annealing ferroelectrics, leading to an improvement in the negative capacitance effect.
It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.
Number | Date | Country | Kind |
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10-2021-0036079 | Mar 2021 | KR | national |
10-2021-0040542 | Mar 2021 | KR | national |
This application is a continuation-in-part to U.S. application Ser. No. 17/496,300, filed Oct. 7, 2021, which is based on and claims priority under 35 U.S.C. §119 to Korean Patent Application Nos. 10-2021-0036079, filed on Mar. 19, 2021, and 10-2021-0040542, filed on Mar. 29, 2021, in the Korean Intellectual Property Office, the disclosures of each of which are incorporated by reference herein in their entirety.
Number | Date | Country | |
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Parent | 17496300 | Oct 2021 | US |
Child | 18502545 | US |