Claims
- 1. A semiconductor device comprising:an insulator layer formed on a wafer, a single crystalline semiconductor layer formed on said insulator layer, and a MOS field effect transistor formed on said single crystalline semiconductor layer, wherein said single crystalline semiconductor layer comprises a first conductivity type region and a second conductivity type region being opposite conductivity type to said first conductivity type region, wherein said first conductivity type region functions as one of a source region and a drain region of said MOS field effect transistor, wherein a lower surface of said first conductivity type region is formed apart from said insulator layer, wherein a recombination center region is formed inside said second conductivity type region and contacting a lower surface of said first conductivity type region, and wherein an edge of said recombination center region is positioned apart from an edge of said first conductivity type region, and contacting both said first conductivity type region and said second conductivity type region.
- 2. A semiconductor device according to claim 1, wherein a lower surface of said recombination center region contacts an upper surface of said insulator layer.
- 3. A semiconductor device according to claim 1, wherein a lower surface of said recombination center region is separate from an upper surface of said insulator layer.
- 4. A semiconductor device according to claim 1, wherein said recombination center region is of the second conductivity type.
- 5. A semiconductor device according to claim 1, wherein said recombination center region is a non-single crystalline region.
- 6. A semiconductor device according to claim 1, wherein a portion of said single crystalline semiconductor layer between said first conductivity type region and said insulator layer becomes a depletion layer when a voltage is applied to said first conductivity type region.
- 7. A semiconductor device according to claim 1, wherein a pair of said first conductivity type regions are provided, functioning as the source and drain regions of said MOS filed effect transistor, and wherein a pair of said recombination center regions are provided, one contacting both the source region and the second conductivity type region and the other contacting both the drain region and the second conductivity type region.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9-196206 |
Jul 1997 |
JP |
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Parent Case Info
This is a continuation of parent application Ser. No. 09/381,399 filed Sep. 20, 1999 now U.S. Pat. No. 6,538,268, which is a PCT/JP98/03249 filed Jul. 21, 1998 the entire disclosure of which is hereby incorporated by reference.
US Referenced Citations (5)
Foreign Referenced Citations (4)
Number |
Date |
Country |
62-274778 |
Nov 1987 |
JP |
2-186677 |
Jul 1990 |
JP |
9-116112 |
May 1997 |
JP |
9-139434 |
May 1997 |
JP |
Non-Patent Literature Citations (4)
Entry |
Ohno et al. “Suppression of the Parasitic Bipolar Effect In Ultra-Thin-Film nMOSFETs/SIMOX by Ar Ion Implantation into Source/Drain Regions” 1995 IEEE, 12/10-13/95. |
Ploeg et al., “Elimination of Bipolar-Induced Breakdown in Fully-Developed SOI MOSFETs” 1992 IEEE. 12/13-16/92. |
Horiuchi, Semiconductor Device and Its Method of Manufacture (English translation of Japanese patent application JP-9-139434). |
Extended Abstracts (The 2nd Spring Meeting, 1995) the Japan Society of Applied Physics and Related Societies, p. 755. |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/381399 |
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US |
Child |
10/260656 |
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US |