Patent Application
20230384378
In recent years, in LSI designs which have become highly integrated, large-scale, and high-speed, it has become indispensable to apply scan test (especially at-speed scan testing), which is one of the test methods for semiconductor integrated circuits, from the viewpoint of reducing the cost required for specification assurance and testing (test).
However, in scan testing, a very large amount of power is consumed in comparison with the function operation (in normal operation). Therefore, it is required to reduce the power consumption during the scan test, and the influence of the peak power and the importance of the reduction are also increasing rapidly.
There are disclosed techniques listed below.
For example, Patent Document 1 aims to reduce the peak power during capture mode in scan testing. For a plurality of circuit blocks, including scan chains and combination circuits, with no data path dependence among them, each block is assigned with a clock selection logic. The clock selection logic can switch between internal PLL clock and a particular scan clock generated by an additional scan clock control logic. The scan clock control logic can generate shift clocks, switching in the same timing, for all blocks during shift mode in scan testing, and generate capture clocks, switching in different timings, for all blocks during capture mode in scan testing. In Patent Document 1, all clocks generated by the scan clock control logic are called block scan clocks.
Furthermore, Non-Patent Document 1 discloses a method to reduce peak power during shift mode in scan testing, in SoC (System on Chip) designs. As shown in
In Non-Patent Document 1, all blocks in a SoC design are divided into adjacent (sharing power supply) and non-adjacent (not sharing power supply) blocks. By assigning different phase shift clocks to all adjacent blocks, peak shift power caused by simultaneous shifting of all blocks can be reduced.
In Non-Patent Document 2, in order to reduce the power supply voltage drop in the shift mode of scan testing, MD-SCAN (Multi Duty-Scan) technique is proposed.
The prior art disclosed in Non-Patent Document 1 can prevent all adjacent blocks in the SoC product from using the same phase shift clock, yet test may still fail, in the case of a group contains only one block, and the peak power consumption caused by only testing this block still across the critical line.
Other issues and novel features will be explained in the description of this specification and the accompanying drawings.
According to one embodiment, a semiconductor device is equipped with a clock operator circuit that can shift the phase of the ATE clock signal (ATE_Clk) into several different variations and distribute the phase shifted clock to scan chains scan testing based on external control signals.
According to the one embodiment, a semiconductor device can reduce the peak shift power during scan testing, reducing over-kill and improving the yield.
Hereinafter, a semiconductor device according to an embodiment will be described in detail by referring to the drawings. In the specification and the drawings, the same or corresponding form elements are denoted by the same reference numerals, and a repetitive description thereof is omitted. In the drawings, for convenience of description, the configuration may be omitted or simplified. Also, at least some of the embodiments may be arbitrarily combined with each other.
In the first embodiment, as an example of a semiconductor device, microcomputer 1 will be described. Microcomputer 1 as a semiconductor device, for example, a semiconductor substrate (semiconductor chip) such as a single-crystal silicon, is formed using a known CMOS manufacturing process. Microcomputer 1 includes a plurality of scan chains S1, S2, S3, S4, and Clock Operator 11 to shift the phase of ATE clock signal 14 (ATE_Clk) supplied from a tester (not shown) and distributing the signals to the scan chains.
Shift Clock Duty Shifter 111 is controlled by shift control signal 13 (ShifterEN), if shift control signal 13 (ShifterEN) is ON, the phase of the supplied ATE clock signal 14 (ATE_Clk) will be shifted. On the other hand, when shift control signal 13 (ShifterEN) is OFF, it outputs ATE clock signal 14 (ATE_Clk) without changing its phase.
Shift Clock Selector 112 is controlled by clock sort signal 12 (Clk_Sort[x:0]) and selects the input ATE clock signal 14 (ATE_Clk) in the defined order and outputs it to the clock port of each scan chain. Here, the value of x is determined by the number of the phase shifted clocks c (c>1) and the number of scan chains s; More specifically, x=(√c)*s.
(Operation of the Shift Clock Duty Shifter)
In the example shown in
As the truth table of
(Operation of Shift Clock Selector)
In the example illustrated in
The truth table of
(Explanation of Design Flow 1)
For the pre-DFT netlist (gate level) of microcomputer 1 in
The above steps generate a post DFT netlist of microcomputer 1 (step S704), and for the generated post DFT netlist (step S705), a clock tree is implemented by clock tree synthesis. Here, as an application condition of the present invention, the sub clock trees from Clock Operator 11 to each scan chain or scan chain group need to be independent from each other. After clock tree synthesis, P&R (Place & Route) is executed for the netlist and a post-layout netlist is generated (step S706). Finally, the scan chain grouping considering the layout information which can maximize the reduction of the peak shift power is calculated, and the grouping result is applied through the external control in the scan testing.
(Explanation of Design Flow 2)
In
For a post scan netlist implemented with scan design-based DFT circuit of microcomputer 1, the connection between clock source (Clk source) and the clock input of each scan FF is first deleted (step S802). Then, clock operator module with clock outputs (Clk_Sx (x=1, 2, . . . , n)) are generated and implemented in accordance with the number of scan chains, n (step S803). Here, clock source (Clk source), Clk_Sort and shift control signal (ShifterEN) are connected to the inputs of Clock Operator 11 (step S804). Further, as the output side of Clock Operator 11, each clock output (Clk_Sx) is connected to clock input (clk_in) of all scan FF of scan chain Sx (step S805). The above steps generate a post DFT netlist of microcomputer 1.
(Effect of the First Embodiment)
During the shift operation of the scan test, in microcomputer 1, it is possible to reduce the peak power consumption caused instantaneously by the toggle timing to shift the scan FF belonging to each scan chain.
Furthermore, On/Off of the phase shift function of the shift clock can be controlled by shift control signal (ShifterEN).
In addition, in order to realize the function of independently controlling the clocks of each scan chain, the sub clock trees fanning out from the Clock Operator to each scan chain must be independent from each other.
In the second embodiment, the semiconductor device shows a configuration capable of coping with a design having a plurality of clock domains.
As shown in
Clock Operator 1 (92A) has shift control signal 1 (ShifterEN1) and ATE clock signal 1 (ATE_Clk1). Clock Operator 2 (92B) has shift control signal 2 (ShifterEN2) and ATE clock signal 2 (ATE_Clk2).
Furthermore, in order to control the clock of scan chain, the clock sort signal (Clk_Sort[x:0]) of the first embodiment is divided into clock sort signal 1 (Clk_Sort1[y:0]) and clock sort signal 2 (Clk_Sort2 [x:y]), being assigned to Clock Operator 1 (92A) and Clock Operator 2 (92B), respectively. In the second embodiment, but this is not a limitation for applying the present invention.
During the shift operation in scan testing, it is not always necessary to input the same clock to ATE clock signal 1 (ATE_Clk1) and ATE clock signal 2 (ATE_Clk2). By shifting the phase of ATE clock signal 1 (ATE_Clk1) and ATE clock signal 2 (ATE_Clk2) in advance, the variation of clocks generated from Clock Operator 1 (92A) and Clock Operator 2 (92B) can be increased. As a result, the structure of Clock Operators can be simplified, and it is possible to increase the degree of freedom in performing scan chain grouping.
In addition, since the values of clock sort signal 1 (Clk_Sort1) and clock sort signal 2 (Clk_Sort2) can be changed by external control, it is also possible to change them by the test pattern (wafer test, assembly test, different tester types, etc.). Thus, even after semiconductor products are manufactured, shift power consumption reduction can be realized according to the actual situation, dynamically.
Furthermore, when microcomputer 1 is a SoC, the control of shift control signal 1 (ShifterEN1) and shift control signal 2 (ShifterEN2) also allows control in block units as in the prior art.
(Effect of the Second Embodiment)
The second embodiment can accommodate a larger scale design compare to the first embodiment. In addition, it can correspond to more complicated clock designs.
In microcomputer 10, there is an optimization area Z that is particularly sensitive to voltage drop (V-drop), scan chains S1, S2, S3 and their output cones C1, C2, C3. The optimization area Z is an LSI design-dependent region, for example, the central area of the chip where the power supply is weak, the area where the logic paths are dense, the area where there is a critical path which is hard to meet the timing constraint, or other reasons. The output cone refers to all logic paths from the output port of the FF belonging to each scan chain to the input port of any FF or the output port of the circuit. Output cones C1, C2, C3 overlap with the optimization area Z, respectively. In the overlapped areas switching activity can occur during shift operation.
During shift operation, if the Clock Operator is “On” (e.g. shift control signal (ShifterEN) is “1”), the generated two shift clocks need to be assigned to scan chain S1, S2, S3. As a result, it is necessary to group the scan chains.
After scan chain grouping, the overlap area of each scan chain group should be minimized to suppress the voltage drop (V-drop) of the optimization area Z. Such grouping is the most suitable one.
As shown in
On the other hand,
As a result, the reduction effect of peak shift power can be maximized with less shift clock variations.
In examples of
Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment described above, and it is needless to say that various modifications can be made without departing from the gist thereof.
