Patent Application
20070075317
The entire disclosure of Japanese Patent Application No. 2005-288877, filed Sep. 30, 2005 is expressly incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor device manufacturing method and, more particularly, to ones suitable for application to an SOI (Silicon On Insulator) transistor provided with a back gate electrode.
2. Description of the Related Art
A field-effect transistor formed on an SOI (Silicon On Insulator) substrate is attracting attention for its usefulness in terms of ease of element isolation, freedom from latch-up, small source/drain junction capacitances, and the like.
For example, JP-A-10-261799 discloses a method of irradiating an amorphous or polysilicon layer formed on an insulating film with ultraviolet light beams in a pulsed manner to form, on the insulating film, a polysilicon film having almost-cubic single-crystal grains arranged in a grid and planarize the surface of the polysilicon film by CMP (Chemical Mechanical Polishing), in order to form a silicon thin film with good crystallinity and uniformity on a large-area insulating film.
However, a silicon thin film formed on an insulating film has grain boundaries, microtwins, and various other microdefects. For this reason, a field-effect transistor formed on such a silicon thin film is inferior in transistor characteristics to a field-effect transistor formed in complete single-crystal silicon.
Also, when field-effect transistors formed on respective silicon thin films are to be stacked, a field-effect transistor is present in a lower layer. Accordingly, the planarity of an underlying insulating film on which a silicon thin film of an upper layer is formed deteriorates, and restrictions are imposed on, e.g., annealing conditions at the time of forming the silicon thin film of the upper layer. As a result, the crystallinity of the silicon thin film of the upper layer is inferior to that of the silicon thin film of the lower layer.
Additionally, in a conventional semiconductor integrated circuit, as the channel length of a transistor decreases along with its miniaturization, the rising characteristics of a drain current in a subthreshold region deteriorate. This interferes with low-voltage operation of the transistor and increases an off-leak current. Such an off-leak current not only increases the power consumed during operation or standby but also may constitute a major factor in a breakdown of the transistor.
Under the circumstances, the present invention has as its object to provide a semiconductor device and a semiconductor device manufacturing method which allow improvement in threshold value controllability by a back gate electrode while suppressing a deterioration in the crystallinity of the semiconductor layer, in which the field-effect transistor is formed.
In order to solve the above-described problems, a semiconductor device according to one aspect of the present invention comprises: a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer; a second insulating layer formed on the first single-crystal semiconductor layer and having a film thickness smaller than a film thickness of the first insulating layer; a second single-crystal semiconductor layer formed on the second insulating layer; a gate electrode formed on the second single-crystal semiconductor layer; and source and drain layers that are formed in the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.
This configuration makes it possible to increase flexibility in the arrangement of a back gate electrode and arrange a back gate electrode in a part where concentration of an electric field occurs, without being limited by the arrangement of a gate electrode, source and drain contacts, and the like. Accordingly, it becomes possible to increase flexibility in the design of a field-effect transistor, and an increase in the withstand voltage of a field-effect transistor can be ensured.
Arrangement of a back gate electrode on the back side of a single-crystal semiconductor layer makes it possible to provide shielding from a drain potential using the back gate electrode. Accordingly, even if a drain potential is applied from the surface of a Si thin film of an SOI, a high voltage can be prevented from being applied to the interface between a drain offset layer or high-concentration impurity diffusion layer and a buried oxide film. As a result, a locally high electric field can be prevented from being produced at the interface between the drain offset layer or high-concentration impurity diffusion layer and the buried oxide film, and an increase in the withstand voltage of a SOI transistor can be ensured.
It becomes possible to control the potential of an active region of an SOI transistor with a back gate electrode, thus allowing an improvement in the rising characteristics of a drain current in a subthreshold region. In addition, an electric field at a channel end on the drain side can be lessened. Accordingly, it becomes possible to decrease an off-leak current while allowing low-voltage operation of the transistor. This makes it possible to decrease the power consumed during operation or standby and increase the withstand voltage of the SOI transistor.
It becomes possible to decrease a parasitic capacitance between a back gate electrode and a substrate while allowing increase in a coupling capacitance between a back electrode and a channel region by making the film thickness of the second insulating layer smaller than that of the first insulating layer under the back gate electrode. Accordingly, it becomes possible to improve the threshold value controllability by the back gate electrode. This makes it possible to decrease the power consumed during operation or standby and realize a high speed operation of the SOI transistor.
Further, a semiconductor device according to one aspect of the present invention comprises: a back gate electrode composed of a first single-crystal semiconductor layer formed on a semiconductor substrate via a cavity portion; a second insulating layer formed on the first single-crystal semiconductor layer; a second single-crystal semiconductor layer formed on the second insulating layer; a gate electrode formed on the second single-crystal semiconductor layer; and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.
This makes it possible to connect a back gate electrode to a channel region via the second insulating layer, and connect the back gate electrode to the semiconductor substrate via the cavity portion. In addition, the parasitic capacitance between the back gate electrode and the substrate can be reduced while increasing the coupling capacitance between the back gate electrode and the channel region. Accordingly, it becomes possible to improve the threshold value controllability by the back gate electrode. This makes it possible to decrease the power consumed during operation or standby and realize a high speed operation of the SOI transistor.
Further, a semiconductor device according to one aspect of the present invention comprises: a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer; a second insulating layer formed on the first single-crystal semiconductor layer and having a relative dielectric constant larger than a relative dielectric constant of the first insulating layer; a second single-crystal semiconductor layer formed on the second insulating layer; a gate electrode formed on the second single-crystal semiconductor layer; and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.
Accordingly, it becomes possible to connect the back gate electrode and the channel region via a high dielectric material and connect the back gate electrode and the semiconductor substrate via a low dielectric material. This makes it possible to decrease the parasitic capacitance between the back gate electrode and the substrate while increasing the coupling capacitance between back gate electrode and the channel region. Accordingly, it becomes possible to improve the threshold value controllability by the back gate electrode. This makes it possible to decrease the power consumed during operation or standby and realize a high speed operation of the SOI transistor.
A semiconductor device according to the one aspect of the present invention further comprises a wiring layer that electrically connects the back gate electrode and the gate electrode.
This configuration makes it possible to control the back gate electrode and gate electrode such that they are at the same potential and increase control over the potential of deep part of the channel region. Accordingly, an off-leak current can be decreased while suppressing an increase in chip size. This makes it possible to decrease power consumed during operation or standby and ensure an increase in the withstand voltage of a field-effect transistor.
A semiconductor device manufacturing method according to one aspect of the present invention comprises: a step of forming a first single-crystal semiconductor layer on a single-crystal semiconductor substrate; a step of forming a second single-crystal semiconductor layer whose etching rate is lower than an etching rate of the first single-crystal semiconductor layer on the first single-crystal semiconductor layer; a step of forming a third single-crystal semiconductor layer having the same composition as composition of the first single-crystal semiconductor layer and a film thickness smaller than a film thickness of the first single-crystal semiconductor layer on the second single-crystal semiconductor layer; a step of forming a fourth single-crystal semiconductor layer having the same composition as composition of the second single-crystal semiconductor layer on the third single-crystal semiconductor layer; a step of forming a first trench extending through the first to fourth single-crystal semiconductor layers to expose the single-crystal semiconductor substrate; a step of forming, in the first trench, a support supporting the second and fourth single-crystal semiconductor layers on the single-crystal semiconductor substrate; a step of forming a second trench that exposes at least part of the first and third single-crystal semiconductor layers, on which the support is formed, from the second and fourth single-crystal semiconductor layers; a step of selectively etching the first and third single-crystal semiconductor layers through the second trench to form first and second cavity portions obtained by removing the first and third single-crystal semiconductor layers; and a step of thermally oxidizing the semiconductor substrate and the second and fourth single-crystal semiconductor layers to form respective buried oxide films that fill in the first and second cavity portions.
This configuration makes it possible to bring an etchant into contact with the first and third single-crystal semiconductor layers through the second trench even if the second and fourth single-crystal semiconductor layers are stacked on the first and third single-crystal semiconductor layers, respectively. It becomes possible to remove the first and third single-crystal semiconductor layers while leaving the second and fourth single-crystal semiconductor layers intact and form respective buried oxide films that fill in the first and second cavity portions under the second and fourth single-crystal semiconductor layers. Formation of the support that fills in the first trench makes it possible to support the second and fourth single-crystal semiconductor layers on the single-crystal semiconductor substrate even if the first and second cavity portions are formed under the second and fourth single-crystal semiconductor layers, respectively. A film thickness of the third single-crystal semiconductor layer smaller than a film thickness of the first single-crystal semiconductor layer makes it possible to make a film thickness of the buried oxide film on a back gate electrode smaller than a film thickness of the buried oxide film under the back gate electrode composed of the second single-crystal semiconductor layer.
For this reason, it becomes possible to arrange the second and fourth single-crystal semiconductor layers on the buried oxide films while decreasing the occurrence of defects in the second and fourth single-crystal semiconductor layers. It becomes possible to reduce the parasitic capacitance between the back gate electrode and the substrate while increasing the coupling capacitance between the back gate electrode and the channel region and form an SOI transistor in the fourth single-crystal semiconductor layer without using a SOI substrate. As a result, it becomes possible to improve the threshold value controllability by the back gate electrode while suppressing an increase in cost. This makes it possible to decrease the power consumed during operation or standby and realize a high speed operation of the SOI transistor.
A semiconductor device manufacturing method according to one aspect of the present invention comprises: a step of forming a first single-crystal semiconductor layer on a single-crystal semiconductor substrate; a step of forming a second single-crystal semiconductor layer whose etching rate is lower than an etching rate of the first single-crystal semiconductor layer on the first single-crystal semiconductor layer; a step of forming a third single-crystal semiconductor layer having the same composition as composition of the first single-crystal semiconductor layer and a film thickness smaller than a film thickness of the first single-crystal semiconductor layer on the second single-crystal semiconductor layer; a step of forming a fourth single-crystal semiconductor layer having the same composition as composition of the second single-crystal semiconductor layer on the third single-crystal semiconductor layer; a step of forming a first trench extending through the first to fourth single-crystal semiconductor layers to expose the single-crystal semiconductor substrate; a step of forming, in the first trench, a support supporting the second and fourth single-crystal semiconductor layers on the single-crystal semiconductor substrate; a step of forming a second trench that exposes at least part of the first and third single-crystal semiconductor layers, on which the support is formed, from the second and fourth single-crystal semiconductor layers; a step of selectively etching the first and third single-crystal semiconductor layers through the second trench to form first and second cavity portions obtained by removing the first and third single-crystal semiconductor layers; and a step of thermally oxidizing the semiconductor substrate and the second and fourth single-crystal semiconductor layers to form surface oxide films on the upper and lower surfaces of the first cavity portion and form a buried oxide film that fills in the second cavity portion.
This configuration makes it possible to arrange a cavity portion between a back gate electrode composed of the second single-crystal semiconductor layer and the substrate while reducing the occurrence of defects in the second and fourth single-crystal semiconductor layers and arrange the buried oxide film between a back gate electrode and a channel region. For this reason, it becomes possible to decrease the parasitic capacitance between the back gate electrode and the substrate while increasing the coupling capacitance between back gate electrode and the channel region, and a SOI transistor can be formed in the fourth single-crystal semiconductor layer without using a SOI substrate. As a result, it becomes possible to improve the threshold value controllability by the back gate electrode while suppressing an increase in cost. This makes it possible to decrease the power consumed during operation or standby and realize a high speed operation of the SOI transistor.
A semiconductor device manufacturing method according to one aspect of the present invention comprises: a step of forming a first single-crystal semiconductor layer on a single-crystal semiconductor substrate; a step of forming a second single-crystal semiconductor layer whose etching rate is lower than an etching rate of the first single-crystal semiconductor layer on the first single-crystal semiconductor layer; a step of forming a third single-crystal semiconductor layer having the same composition as composition of the first single-crystal semiconductor layer on the second single-crystal semiconductor layer; a step of forming a fourth single-crystal semiconductor layer having the same composition as composition of the second single-crystal semiconductor layer on the third single-crystal semiconductor layer; a step of forming a first trench extending through the first to fourth single-crystal semiconductor layers to expose the single-crystal semiconductor substrate; a step of forming, in the first trench, a support supporting the second and fourth single-crystal semiconductor layers on the single-crystal semiconductor substrate; a step of forming a second trench that exposes at least part of the first and third single-crystal semiconductor layers, on which the support is formed, from the second and fourth single-crystal semiconductor layers; a step of selectively etching the first and third single-crystal semiconductor layers through the second trench to form first and second cavity portions obtained by removing the first and third single-crystal semiconductor layers; a step of forming a first buried insulating layer that fills in the first cavity portion; and a step of forming a second buried insulating layer that fills in the second cavity portion and that has a relative dielectric constant larger than a relative dielectric constant of the first buried insulating layer.
This configuration makes it possible to arrange a low dielectric material between a back gate electrode composed of the second single-crystal semiconductor layer and a substrate while reducing the occurrence of defects in the second and fourth single-crystal semiconductor layers. It also becomes possible to arrange a high dielectric material between a back gate electrode and a channel region. For this reason, it becomes possible to decrease the parasitic capacitance between the back gate electrode and the substrate while increasing the coupling capacitance between the back gate electrode and the channel region, and a SOI transistor can be formed in the fourth single-crystal semiconductor layer without using a SOI substrate. As a result, it becomes possible to improve the threshold value controllability by the back gate electrode while suppressing an increase in cost. This makes it possible to decrease the power consumed during operation or standby and realize a high speed operation of the SOI transistor.
In the semiconductor device manufacturing method according to the one aspect of the present invention, the single-crystal semiconductor substrate and the second and fourth single-crystal semiconductor layers are made of Si, and the first and third single-crystal semiconductor layers are made of SiGe.
This configuration makes it possible to make etching rates of the first and third single-crystal semiconductor layers higher than etching rates of the single-crystal semiconductor substrate and the second and fourth single-crystal semiconductor layers while lattice matching the single-crystal semiconductor substrate and the first to fourth single-crystal semiconductor layers to each other. Accordingly, it becomes possible to form the second and fourth single-crystal semiconductor layers with good crystalline quality on the first and third single-crystal semiconductor layers, respectively, and ensure insulation between the second and fourth single-crystal semiconductor layers and the single-crystal semiconductor substrate without impairing the qualities of the second and fourth single-crystal semiconductor layers.
A semiconductor device and its manufacturing method according to embodiments of the present invention will be explained below with reference to the drawings.
In
A gate electrode 17a is formed on the single-crystal semiconductor layer 15a via a gate insulating film 16a, and side walls 18a are formed on side walls of the gate electrode 17a. A source layer 19a and a drain layer 20a which are arranged such that the gate electrode 17a is sandwiched between them are also formed in the single-crystal semiconductor layer 15a. A gate electrode 17b is formed on the single-crystal semiconductor layer 15b via a gate insulating film 16b, and side walls 18b are formed on side walls of the gate electrode 17b. A source layer 19b and a drain layer 20b which are arranged such that the gate electrode 17b is sandwiched between them are also formed in the single-crystal semiconductor layer 15b.
This configuration makes it possible to form respective SOI transistors in the single-crystal semiconductor layers 15a and 15b and arrange a back gate electrode on the back side of each SOI transistor. Accordingly, it becomes possible to increase flexibility in the arrangement of the back gate electrode and arrange the back gate electrode in a part where concentration of an electric field occurs without being limited by the arrangement of the gate electrodes 17a and 17b, source and drain contacts, and the like. Accordingly, it becomes possible to increase flexibility in the design of a SOI transistor, and an increase in the withstand voltage of the SOI transistor can be ensured.
The arrangement of the back gate electrode on the back sides of the single-crystal semiconductor layers 15a and 15b makes it possible to provide shielding from drain potentials using the back gate electrodes. Accordingly, even if a drain potential is applied from the surface of the Si thin film of each SOI, a high voltage can be prevented from being applied to the interface between the corresponding one of the drain layers 20a and 20b and the buried oxide film 14. As a result, a locally high electric field can be prevented from being produced at the interface between each of the drain layers 20a and 20b and the buried oxide film 14, and an increase in the withstand voltage of each SOI transistor can be ensured.
It becomes possible to control the potential of an active region of each SOI transistor with the back gate electrode, thus allowing an improvement in the rising characteristics of a drain current in a subthreshold region. In addition, electric fields at channel ends on the drain layers 20a and 20b sides can be lessened. Accordingly, it becomes possible to decrease an off-leak current while allowing low-voltage operation of the SOI transistor. This makes it possible to decrease the power consumed during operation or standby and increase the withstand voltage of the SOI transistor.
The parasitic capacitance between the back gate electrode and the single-crystal semiconductor substrate 11 can be reduced while increasing the coupling capacitance between the back gate electrode and the channel region, by making the film thickness TBOX1 of the buried oxide film 12 under the back gate electrode larger than the film thickness TBOX2 of the buried oxide film 14 on the back gate electrode. As a result, it becomes possible to improve the threshold value controllability by the back gate electrode. This makes it possible to decrease the power consumed during operation or standby and realize a high speed operation of the SOI transistor.
In
A gate electrode 117 is formed on the single-crystal semiconductor layer 115 via a gate insulating film 116, and side walls 118 are formed on side walls of the gate electrode 117. A source layer 119 and a drain layer 120 which are arranged such that the gate electrode 117 is sandwiched between them are also formed in the single-crystal semiconductor layer 115.
This makes it possible to connect a back gate electrode to a channel region via the buried oxide films 114a and 114b, and connect the back gate electrode to the single-crystal semiconductor substrate 111 via the cavity portion 112b. In addition, the parasitic capacitance between the back gate electrode and the single-crystal semiconductor substrate 111 can be reduced while increasing the coupling capacitance between the back gate electrode and the channel region. Accordingly, it becomes possible to improve the threshold value controllability by the back gate electrode. This makes it possible to decrease the power consumed during operation or standby and realize a high speed operation of the SOI transistor.
In
An underlying oxide film 53 is formed on the surface of the single-crystal semiconductor layer 35 by thermally oxidizing the single-crystal semiconductor layer 35. An oxidation-resistant film 54 is formed all over the underlying oxide film 53 by CVD or the like. Note that, for example, a silicon nitride film can be used as the oxidation-resistant film 54.
As shown in
The oxidation-resistant film 54, underlying oxide film 53, single-crystal semiconductor layers 35 and 52 are further patterned using a photolithography technique and etching technique, thereby forming trenches 37, each of which is located so as to overlap a corresponding one of the trenches 36 and wider than the trench 36. The position where each trench 37 is located can be made to correspond to an element isolation region of the semiconductor layer 35.
As shown in
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As shown in
The support 56 formed in the trenches 36 and 37 makes it possible to support the single-crystal semiconductor layers 33 and 35 on the single-crystal semiconductor substrate 31 even if the single-crystal semiconductor layers 51 and 52 are removed. Also, the trenches 38 formed separately from the trenches 36 and 37 make it possible to bring an etchant into contact with the single-crystal semiconductor layers 51 and 52 respectively arranged under the single-crystal semiconductor layers 33 and 35. Accordingly, insulation between the single-crystal semiconductor layers 33 and 35 and the single-crystal semiconductor substrate 31 can be ensured without impairing the crystalline qualities of the single-crystal semiconductor layers 33 and 35.
Note that if the single-crystal semiconductor substrate 31 and single-crystal semiconductor layers 33 and 35 are made of Si, and the single-crystal semiconductor layers 51 and 52 are made of SiGe, hydrofluoric-nitric acid is preferably used as an etchant for the single-crystal semiconductor layers 51 and 52. This makes it possible to obtain a selectivity of about 1:100 to 1:1000 as one between Si and SiGe and remove the single-crystal semiconductor layers 51 and 52 while suppressing overetching of the single-crystal semiconductor substrate 31 and single-crystal semiconductor layers 33 and 35.
As shown in
The film thicknesses of the single-crystal semiconductor layers 33 and 35 after element isolation can be respectively defined by the film thicknesses of the single-crystal semiconductor layers 33 and 35 at the time of epitaxial growth and the film thicknesses of the buried oxide films 32 and 34 formed at the time of thermally oxidizing the single-crystal semiconductor layers 33 and 35. Accordingly, it becomes possible to control the film thicknesses of the single-crystal semiconductor layers 33 and 35 with high precision and thus the single-crystal semiconductor layers 33 and 35 can be formed to be thin while decreasing variation in the film thickness of each of the single-crystal semiconductor layers 33 and 35. The provision of the oxidation-resistant film 54 on the single-crystal semiconductor layer 35 makes it possible to form the buried oxide films 34 on the back side of the single-crystal semiconductor layer 35 while preventing the surface of the single-crystal semiconductor layer 35 from being thermally oxidized.
The film thickness of the single-crystal semiconductor layer 51 larger than that of the single-crystal semiconductor layer 52 makes it possible to make the interval of cavity portions 57a larger than the interval of cavity portions 57b. Thus, it becomes possible to leave part of cavity portions 57a between the surface oxide films 32c and 32a, while making it possible to make the cavity portions 57b thoroughly filled with the buried oxide film 34.
Note that in the method shown in
In
As a material of the insulating layer filled in the cavity portions 57a and 57b, for example, a FSG (fluoride silicate glass) film, a silicon nitride film, and the like, may be arranged to be used besides the silicon oxide film. As the insulating layer filled in the cavity portions 57a and 57b, besides a SOG (Spin On Glass) film, a PSG film, a BPSG film, an organic low k film, such as a PAE (poly aryleneether) based film, a HSQ (hydrogen silsesquioxane) based film, a MSQ (methyl silsesquioxane) based film, a PCB based film, CF based film, a SiOC based film, and a SiOF based film, or a porous film made of these films may be arranged to be used.
The relative dielectric constant of the buried insulating layer filled in the cavity portion 57a is preferably smaller than the relative dielectric constant of the buried insulating layer filled in the cavity portion 57b.
As shown in
As shown in
As shown in
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As shown in
This configuration makes it possible to arrange the single-crystal semiconductor layers 33 and 35 on the buried oxide films 32 and 34 while decreasing the occurrence of defects in the single-crystal semiconductor layers 33 and 35. For this reason, it becomes possible to decrease the parasitic capacitance between the back gate electrode and the substrate while increasing the coupling capacitance between back gate electrode and the channel region, and a SOI transistor can be formed in the single-crystal semiconductor layer 35 without using a SOI substrate. As a result, it becomes possible to improve the threshold value controllability by the back gate electrode while suppressing an increase in cost. This makes it possible to decrease the power consumed during operation or standby and realize a high speed operation of the SOI transistor.
Note that the gate electrode 42 and single-crystal semiconductor layer 35 may be electrically connected to each other through the back gate contact electrodes 45a and 45b. This configuration makes it possible to control the back gate electrodes and gate electrode 42 such that they are at the same potential and increase control over the potential of a channel region. Accordingly, an off-leak current can be decreased while suppressing an increase in chip size. This makes it possible to decrease power consumed during operation or standby and ensure an increase in the withstand voltage of a field-effect transistor.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-288877 | Sep 2005 | JP | national |
