SEMICONDUCTOR DEVICE HAVING A REDUCED CONCENTRATION OF CARBON VACANCIES AND ITS MANUFACTURING METHOD

Abstract

The present disclosure relates to a semiconductor device (1) comprising at least one epitaxial layer (2) made from a first semiconductor material comprising carbon and having a [0001] crystallographic axis. At least one implantation area (4) is formed at a sidewall (3a) of the epitaxial layer (2), wherein a normal direction of the sidewall (3a) is perpendicular to the [0001] crystallographic axis. At least one part of the epitaxial layer (2) has a reduced concentration of carbon vacancy (VC) with respect to the first semiconductor material of the at least one epitaxial layer (2) as-grown. The present disclosure further relates to a method for manufacturing a semiconductor device (1), wherein ions are implanted through at least one sidewall (3a) of at least one epitaxial layer (2).

Description

The present disclosure relates to semiconductor devices comprising at least one epitaxial layer made from a first semiconductor material comprising carbon, in particular silicon carbide, wherein at least one part of the epitaxial layer has a reduced concentration of carbon vacancies with respect to the first semiconductor material of the at least one epitaxial layer as-grown. The present disclosure further relates to methods for manufacturing such semiconductor devices.

U.S. Pat. No. 7,754,589 B2 relates to a method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal.

Embodiments of the disclosure relate to improved semiconductor devices and methods for their manufacturing. Exemplarily, there is a need for semiconductor devices that have an improved lifetime, low defect density and/or can be manufactured in a flexible way using conventional semiconductor processing steps.

According to a first aspect, a semiconductor device comprising at least one epitaxial layer made from a first semiconductor material comprising carbon, in particular silicon carbide, and having a [0001] crystallographic axis is provided. At least one implantation area is formed at a sidewall of the epitaxial layer, a normal direction of the sidewall being perpendicular to the [0001] crystallographic axis. At least one part of the epitaxial layer has a reduced concentration of carbon vacancies with respect to the first semiconductor material of the at least one epitaxial layer as-grown.

By providing an implantation area at a sidewall of an epitaxial layer, implantation can be performed independent of other processing steps, which are typically performed in parallel to the [0001] crystallographic axis, e.g. on or through the front face of the epitaxial layer. At the same time, motility of an implanted species is improved, which simplifies a later annealing of the at least one epitaxial layer and results in a reduced concentration of carbon vacancies therein.

According to at least one embodiment, the at least one implantation area is formed on one of a plurality of sidewalls of at least one semiconductor chip comprising the at least one epitaxial layer. Implanting a species through a sidewall of a semiconductor chip allows the reduction of carbon vacancies on already separated, almost finished semiconductor circuit component.

According to at least one embodiment, the semiconductor device comprises at least one trench having two sidewalls formed in the at least one epitaxial layer. The at least one implantation area is formed on at least one of the two sidewalls of the at least one trench. The at least one part of the epitaxial layer corresponds to a sublayer extending in a plane perpendicular to the [0001] crystallographic axis, wherein a thickness of the sublayer corresponds to or exceeds a depth of the at least one trench. Use of trenches allows the implantation of a species on a vertical side-wall of an epitaxial layers having a relatively large spatial extent.

In at least one embodiment, the semiconductor device further comprises at least one electrode formed on a top or bottom surface of the at least one epitaxial layer, thereby forming an electrically active area, wherein the at least one implantation area is formed outside of an electrically active area. For example, the at least one implantation area may be formed in spatial proximity to the electrically active area of the semiconductor device. Such a spatial arrangement allows the reduction of carbon vacancies in the electrically active area without disturbing any elements within the electrically active area implementing a function of the semiconductor device.

For example, the first semiconductor material may comprise one of n-type 4H-SiC or n-type 6H-SiC semiconductor material. For example, the at least one implantation area may comprises an implanted species, comprising at least one of carbon ions, aluminum ions and silicon ions. For example, the at least one implantation area may comprises an implantation defect area, comprising amorphous silicon. For example, the at least one part of the epitaxial layer may have a concentration of carbon vacancy Z_1/2 of below 10¹⁰/cm³.

According to different embodiments, the semiconductor device may comprise different power electronic components, such as a PIN diode, a BJT, an IGBT, or a JBS diode.

According to a second aspect of the disclosure, a method for manufacturing a semiconductor device is provided. The method comprises growing at least one epitaxial layer made from a first semiconductor material comprising carbon, in particular silicon carbide, and having a [0001] crystallographic axis, and implanting ions through at least one sidewall of the at least one epitaxial layer to form at least one implantation area in a plane perpendicular to the [0001] crystallographic axis, thereby reducing a concentration of carbon vacancies in the first semiconductor material with respect to the at least one epitaxial layer as-grown.

The above steps enable the manufacturing of a semiconductor device according to first aspect. They enable an improved degree of flexibility during manufacturing. In particular, the step of implanting ions can be performed towards the end of the manufacturing process after other steps negatively affecting carbon vacancies of the at least one epitaxial layer have been completed.

According to at least one embodiment, the method further comprises at least one of annealing or proton irradiating the at least one epitaxial layer to further reduce the concentration of carbon vacancies in the first semiconductor material with respect to the at least one epitaxial layer after implanting ions. Annealing or proton irradiation helps to diffuse generated carbon interstitials.

According to at least one embodiment, before implanting ions through at least one sidewall, the method further comprises: performing a plurality of processing steps to form at least one semiconductor circuit component comprising at least parts of the at least one epitaxial layer; and separating the at least one semiconductor circuit component to obtain a semiconductor chip having a top surface perpendicular to the [0001] crystallographic axis and a plurality of sidewalls perpendicular to the top surface. Implanting ions through sidewalls of semiconductor chips enables the reduction of carbon vacancies in a separated, essentially finished semiconductor component.

According to another embodiment, the method further comprises forming at least one trench having two sidewalls within the at least one epitaxial layer, wherein implanting ions through at least one sidewall comprises plasma immersion ion implanting (PIII) of at least one of boron (B) ions, carbon (C) ions, aluminum (Al) ions, germanium (Ge) ions, nitrogen (N) ions, phosphorus (P) ions, arsenic (As) ions, oxygen (O) ions, sulfur (S) ions, hydrogen (H) ions, argon (Ar) ions or silicon (Si) ions through the two sidewalls of the at least one trench.

Further aspects, embodiments and advantages of the present invention are disclosed in the following detailed description of embodiments as well as the attached set of claims.

The method for manufacturing a semiconductor device according to the second aspect described above is particularly suitable for manufacturing the semiconductor device according to the first aspect. Features and advantages described in connection with the semiconductor device can therefore be used in the manufacturing method and vice versa.

Thus, every feature described with respect to one of the aspects is also disclosed herein with respect to the other aspect, even if the respective feature is not explicitly mentioned in the context of the specific aspect.

The accompanying figures are included to provide a further understanding. In the figures, elements of the same structure and/or functionality may be referenced by the same reference signs. It is to be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

FIG. 1 shows, in a schematic manner, a semiconductor device according to an embodiment of the disclosure.

FIG. 2 shows, in a schematic manner, a method for manufacturing a semiconductor device according to an embodiment of the disclosure.

FIG. 3 shows DLTS spectra of an epitaxial layer according to FIG. 1 before and after implanting and annealing.

FIGS. 4 to 6 show steps for manufacturing a PIN diode according to an embodiment of the disclosure.

FIGS. 7 to 10 show steps for manufacturing a BJT according to an embodiment of the disclosure.

FIGS. 11 and 12 show steps for manufacturing an IGBT according to an embodiment of the disclosure.

FIG. 13 shows, in a schematic manner, a semiconductor device comprising a trench according to an embodiment of the disclosure.

FIG. 14 shows DLTS spectra of an epitaxial layer according to FIG. 13 before and after implantation and annealing.

FIGS. 15 to 19 show steps for manufacturing a JBS diode according to another embodiment of the disclosure.

FIGS. 20 to 22 show steps for manufacturing a BJT according to another embodiment of the disclosure.

FIGS. 23 to 25 show steps for manufacturing an IGBT according to another embodiment of the disclosure.

FIG. 26 shows, in a schematic manner, a method for producing a semiconductor device according to an embodiment of the disclosure.

FIG. 27 shows, in a schematic manner, the removal of carbon vacancies through a top surface of a semiconductor device.

While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the figures and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure defined by the appended claims.

Before various embodiments of the present disclosure are described in more detail, at first some challenges encountered in conventional silicon carbide semiconductor materials and their processing are discussed.

The so-called carbon vacancy (V_C) is a technologically relevant, electrically active point defect in n-type 4H silicon carbide (4H-SiC). The presence of carbon vacancy gives rise to two levels in the bandgap of the semiconductor material, referred to as Z_1/2 and EH_6/7, located at 0.65 eV and 1.6 eV below the conduction band edge (E_C), respectively. As the level of Z_1/2 defects is particularly close to the conduction band edge, it acts as a recombination center, affecting the lifetime, forward voltage drop of bipolar devices and leakage current in unipolar devices formed from such semiconductor materials.

In principle, it is possible to remove a carbon vacancy from an epitaxial layer as-grown as shown in FIG. 27.

A semiconductor device 1 comprises a 4H-SiC epitaxial layer 2 grown on a surface of a substrate 5 in a [0001] crystallographic axis direction X, as defined by Miller-Bravais indices. The [0001] crystallographic axis typically corresponds to the normal direction of the surface of the substrate 5. As-grown, the epitaxial layer 2 will comprise a number of carbon vacancies V_C throughout the 4H-SiC epitaxial layer 2. To reduce the concentration of carbon vacancy V_C, a top surface area 4a is either oxidized at a temperature of 1050 to 1400° C. Alternatively, a shallow carbon ions may be implanted into the top surface area 4a of SiC epitaxial layer 2. Either approach will in the introduction of carbon interstitials C_I into the 4H-SiC epitaxial layer 2. Then, the epitaxial layer 2 is annealed at a temperature in excess of 1500° C., resulting in a diffusion of the carbon interstitials C_I throughout the epitaxial layer 2. The carbon interstitials C_I can then recombine with the carbon vacancies V_C. Consequently, the epitaxial layer 2 will have a reduced carbon vacancy concentration.

As shown in FIG. 27, Carbon implantation is performed parallel to the [0001] crystallographic axis. After diffusion of carbon interstitials C_I, reactive ion etching (RIE) or chemical mechanical polishing (CMP) is used in order to remove the C-implanted layer formed in the top surface area 4a. A similar situation would occur if oxidation is employed for carbon vacancy V_C reduction, where the oxide layer needs to be removed using hydrofluoric acid (HF).

Thus, the method for reducing carbon vacancy described above can only be carried out relatively early in a manufacturing processes, e.g. on the epitaxial layer 2 as-received. While this results in a 4H-SiC epitaxial layer 2 having a reduced concentration of carbon vacancies V_C towards the start of the manufacturing of a semiconductor device 1, subsequent processing steps such as activation of a highly doped p+ area or annealing of electrodes of an semiconductor circuit component, result in a regeneration of carbon vacancies V_C in the epitaxial layer 2. Once the carbon vacancies V_C have been re-generated, a second Carbon ion implantation cannot be performed, as this would require implanting Carbon into electrically active areas of the semiconductor device, such as an anode area or electrode. Moreover, oxidation cannot be performed, as this would consume parts of the active circuit structures in case of relatively thick epitaxial layers 2, e.g. epitaxial layers 2 having a thickness of 100 μm or more.

The present disclosure aims to describe alternative methods and devices having a reduced carbon vacancy concentration as compared to an epitaxial layer as-grown.

FIG. 1 shows a semiconductor device 1 according to an embodiment of the present disclosure. Steps S1 to S3 of a method for reducing carbon vacancy V_C of an epitaxial layer 2 of the semiconductor device 1 are shown in FIG. 2.

In a step S1, the epitaxial layer 2 is grown on a substrate 5 or other epitaxial layer (not shown). Initially, the epitaxial layer 2 will comprise a relatively high concentration of carbon vacancy V_C. For example, untreated n-type 4H-SiC semiconductor material of the epitaxial layer 2 may have comprise 10¹² Z_1/2 defects per cm³.

Thus, in step S2, ions, for example carbon (C) ions, aluminum (Al) ions or silicon (Si) ions, are implanted through a sidewall 3a to form an implantation area 4 in the semiconductor material. Contrary to the situation shown in FIG. 27, in the embodiment shown in FIG. 1, ions are implanted through sidewalls 3a to form implantation areas 4 in a plane perpendicular to a top surface of the semiconductor device. That is to say, the implantation direction is perpendicular to the [0001] crystallographic axis direction X of the epitaxial layer 2. The side implantation may be performed at room temperature.

In the embodiment shown in FIG. 1, carbon ions are implanted through two opposite sidewalls 3a to form carbon interstitial C_I in two implantation areas 4. It is also possible to implant ions through a single sidewall 3a to form a single implantation area 4, or to implant ions through three or four sidewalls 31, for example all sidewalls of a rectangular semiconductor chip. In the described embodiment, side implantation of Carbon on a 3-5×10¹⁶ cm⁻³ N-doped epitaxial layer 2 was carried out. One or more side implantation energies can be chosen so that the implantation profile will be outside the active electric area of the semiconductor device 1. For example, three different implantation stages with energies in the range of 10 to 200 keV may be used. Side implantation doses can range from 10¹⁰ to 10¹⁶ cm⁻².

As shown in FIG. 1, step S2 may be carried out immediately after growing the epitaxial layer S1. However, it is also possible to form the implantation areas 4 towards the end of manufacturing the semiconductor device 1 as later described with regard to various specific semiconductor devices.

Side implantation can be followed by an optional, separate diffusion step S3. For example, the epitaxial layer 2 may be annealed at temperatures in excess of 1000° C. for periods between 1 minute and 10 hours depending on the thickness of the epitaxial layer 2. The thickness of the epitaxial layer 2 may lie in a range of 5 to 150 μm for example. In the described embodiment, the epitaxial layer 2 a relatively short annealing step is carried out at a temperature of 1500° C. for a period of 5 minutes. During this period, the generated carbon interstitials C_I further diffuse throughout the epitaxial layer 2. Alternatively or in addition, proton irradiation may be used to further diffuse the generated carbon interstitials C_I. For example, proton irradiation at or below 10 keV may be used.

Alternatively, side implantation with no subsequent diffusion step can be carried out on a finished semiconductor component. For example, after implantation of carbon with energies equal or higher than 300 keV, sufficient diffusion of carbon interstitials C_I takes place without an additional diffusion step.

It has been found that point defects in crystal structure of the epitaxial layer 2 can migrate quickly and thus a relatively long distances perpendicular to the [0001] crystallographic axis direction X. For example, carbon interstitials can diffuse long distances perpendicular to [0001] direction after 10 keV proton irradiation even at room temperature. This in turn significantly reduces carbon vacancy V_C throughout the epitaxial layer 2. For example, using the parameters described above, a horizontal diffusion length of several millimeters can be achieved, resulting in a significant reduction of carbon vacancy V_C throughout the entire width of the epitaxial layer 2 of a semiconductor chip having an edge length of 5 mm, for example. For example, a concentration of carbon vacancies V_C may be reduced by two or more orders of magnitude as compared with the epitaxial layer 2 as-grown.

FIG. 3 shows the result of deep level transient spectroscopy (DLTS) analysis of the semiconductor device 1 according to FIG. 1. Therein, the curve with reference sign A shows a DLTS spectrum of untreated n-type 4H-SiC epitaxial layer 2 as-grown after step S1. The curve shows with reference sign B shows the DLTS spectrum of the epitaxial layer 2 after implantation of carbon ions in step S2 and annealing in step S3. As can be seen, after step S1, the untreated semiconductor device 1 comprises a relatively high concentration of carbon vacancy. Exemplarily, it comprises a concentration of Z_1/2 defects in the order of 10¹²/cm³. As detailed above, the defect level Z_1/2 is very close to the conduction band edge E_C and would therefore negatively affect the performance of a finished semiconductor device 1.

After implantation of carbon ions in step S2 and annealing of the epitaxial layer in step S3, no detectable amount of Z_1/2 defects are present in the semiconductor device 1. In addition, as can be seen in FIG. 3, the presence of so-called deep level ON1 and ON2 peaks that lie 0.84 eV and 1.1 eV below the conduction band edge E_C, respectively, can be detected. ON1 and ON2 levels are associated with carbon diffusion and typically detected after the implantation of carbon ions as described above with regard to FIG. 27. Accordingly, side implantation of carbon ions through sidewalls 3a of a semiconductor device greatly reduce the concentration of carbon vacancy V_C of an epitaxial layer 2 with respect to the concentration of carbon vacancies V_C in the same epitaxial layer 2 as-grown.

In the following, manufacturing processes for various semiconductor devices 1 are described in more detail. The described processing steps will make apparent that a side implementation as described above with regard to FIGS. 1 and 2 provides an enhanced degree of flexibility in the manufacturing of semiconductor devices 1.

At first, processing steps for manufacturing a PIN diode 20 are shown with respect to FIGS. 4 to 6. In a first processing step shown in FIG. 4, an n-type 4H-SiC epitaxial layer 2 is grown on a substrate 5. As described above, the epitaxial layer 2 will have a relatively high concentration of carbon vacancies V_C. In a next processing step shown in FIG. 5, the epitaxial layer 2 is implanted with aluminum ions to form a highly doped p-type anode area 21. This is followed by a high temperature annealing step (not shown). During the annealing, further carbon vacancies V_C are generated, even in the case carbon vacancies V_C had been previously removed.

FIG. 6 shows the final p+-i-n structure of the PIN diode 20, further comprising implanted field relaxation layers 22 formed by conventional ion implantation. In addition, a metal anode electrode 23 and a metal cathode electrode 24 are formed on a top and bottom surface of the anode area 21 and the substrate 5, respectively. The anode electrode 23 and the cathode electrode 24 may be formed by electron-beam deposition. Forming of the field relaxation layers 22, the anode electrode 23 and the cathode electrode 24 may result in the generation of further carbon vacancies V_C in the epitaxial layer 2 acting as an intrinsic drift layer of the PIN diode 20.

To improve the performance of the PIN diode 20, and exemplarily of the n-type epitaxial layer 2, two implantation areas 4 are formed on the sidewalls 3a of the PIN diode 20 (also shown in FIG. 6). Implantation of Carbon or other ions in the implantation areas 4 and optional subsequent annealing of the epitaxial layer 2 will result in a reduced carbon vacancy V_C concentration in the epitaxial layer 2 acting as a drift layer. This is indicated in FIG. 6 by the lighter shading of the epitaxial layer 2.

As detailed above with FIG. 3, the side implantation and subsequent annealing will also generate ON1 and ON2 levels. However, the presence of ON1 and ON2 levels in the epitaxial layer 2 does not influence the performance of the PIN diode 20.

In the described embodiment, forming of the field relaxation areas 22 is performed by frontside processing of the epitaxial layer 2 on a wafer or other substrate 5. Similarly, formation of the electrodes 23 and 24 is implemented by conventional metallization procedures from the front and back surfaces of the semiconductor device 1. For efficiency, typically a relatively large number of semiconductor devices 1, such as PIN diodes 20 are formed together on a common wafer or other substrate 5.

To implant ions in the vertical implantation areas 4, an area of the wafer or other substrate 5 corresponding to the PIN diode 20 may be separated from similar semiconductor circuit components grown on the same wafer or other substrate 5 by dicing. Thereby, individual semiconductor chips are formed, which may then be installed with the [0001] crystallographic axis pointing sideways into an ion implantation system to implant carbon ions through the sidewalls 3a of the individual semiconductor chips. For this purpose, a modified target holder carrying one or more semiconductor chips may be employed. During implantation, a first implantation direction 25 for implanting ions into the field relaxation area 22 of the epitaxial layer 2 is orthogonal to a second implantation direction 26 for implanting ions into the implantation area 4. Moreover, due to the side implantation, the implantation area 4 extends over the entire side surface of the semiconductor material, comprising the substrate 5 and the epitaxial layer 2.

FIGS. 7 to 10 show processing steps for manufacturing a bipolar junction transistor (BJT) 30, exemplarily an NPN transistor, according to an embodiment of the present disclosure. In a first step shown in FIG. 7, an n-type collector 31 made from a semiconductor material comprising carbon, such as 4H-SiC or 6H-SiC, is provided. Subsequently, a p-type base 32 is epitaxially grown on the n-type collector 31 (FIG. 8). Then, an n-type emitter layer 33 is epitaxially grown on the p-type base 32 (FIG. 9).

Subsequently, selected areas of the emitter 33 and corresponding top parts of the base 32 are etched to allow for the formation of gate electrodes as shown in FIG. 10. At the base of the etched trenches, highly doped p-type layers 34 are formed in the p-type base 34. Thereafter, a gate electrode 35 is formed on a top surface of the highly doped p-type layer 34, an emitter electrode 36 is formed on a top surface of the n-type emitter 33, and a collector electrode 36 is formed on a bottom surface of the n-type collector 31.

The semiconductor material of both the n-type collector 31 as well as the n-type emitter 33 will comprise an increased concentration of carbon vacancies V_C present in the respective epitaxial layers 2 as-grown and/or further processed during a processing of the BJT 30. To reduce the carbon vacancy V_C in the collector 31 and emitter 33, implantation areas 4 are formed on sidewalls 3a of the BJT 30 as described above. The presence of the implantation areas 4 will result in the formation of carbon interstitials C_I and thus a reduction of the carbon vacancy V_C.

While the manufacturing method shown in FIGS. 7 to 10 has been described with respect to formation of an NPN BJT, similarly, a PNP BJT may be formed using the disclosed side implantation method, comprising a n-type base with a reduced carbon vacancy V_C after annealing with respect to the epitaxial layer later forming the base as-grown.

FIGS. 11 and 12 show two stages of manufacturing an insulated-gate bipolar transistor (IGBT) 40. Initially, an n-type base 42 made from 4H-SiC or 6H-SiC is epitaxially grown on a p-type collector 41, as shown in FIG. 11.

As shown in FIG. 12, within the n-type base 42, two p-type base wells 43 are formed by ion implantation through a top surface of the n-type base 42. Therein, a total of four n-type areas 44 are formed by either plasma immersion ion implantation (PIII) or conventional ion implantation. Thereafter, an oxide layer 45, serving as electrical insulator, is formed in the central area of the n-type base 42 between right (inner) n-type area 44 of the left p-type base well 43 and the left (inner) n-type area 44 of the right p-type base well 43. On top of the oxide layer 45, an insulated gate electrode 46 is formed. Moreover, one or more emitter electrodes 47 are formed on top surface of the n-type areas 44. On the back surface of the p-type collector 41, a collector electrode 47 is formed. The electrodes 46, 47 and 48 may be formed by e-beam deposition.

Although not shown in FIG. 12, a buffer layer can be present at the interface between the n-type base 42 and the p-type collector 41.

As detailed above, the n-type base layer 42 will have a high carbon vacancy V_C concentration after forming the IGBT 40. To reduce the unwanted point defects, implantation areas 4 are formed on sidewalls 3a of the IGBT 40 before annealing the n-type base 42. As described above, this will remove carbon vacancy V_C from the base 42 and result in the generation of ON1 and ON2 in the n-type layers 42 and 44. However, the generated ON1 and ON2 are not harmful for the manufactured semiconductor device, e.g. the IGBT 40. Moreover, although the process has been described for an IGBT 40 comprising an n-type base layer 42, the same applies for an IGBT fabricated starting from an n-type collector layer and having a p-type base layer.

It is noted that in the examples described above with reference to FIGS. 4 to 12, it is not necessary to remove the implantation areas 4 after device manufacturing. In each case, the implantation area 4 is placed outside an electrically active area of the respective semiconductor device 1. Thus, no additional RIE or CMP step is required as part of the disclosed manufacturing method, and the finished semiconductor device 1 may comprise a high concentration of the implanted species, such as carbon, in the implantation area 4. Even in the case that an part of the implantation area 4 comprising the implanted species is removed after annealing, for example by RIE or CMP of the sidewalls 3a of the finished semiconductor chip, a remaining implantation defect area of the implantation area 4 will still contain amorphous silicon indicative of the previous side implantation step. Similarly, compared to the oxidation method detailed above with respect to FIG. 27, no long oxidation time and no long HF etching time are required.

The described methods and devices have further advantages. For example, carbon vacancy V_C can be reduced in epitaxial layers 2 of any thickness. The process is especially suited for very thick drift layers of more than 50 μm thickness. The method can be applied to both unipolar and bipolar devices. Some processing steps, such as annealing, can be carried out at lower temperatures compared to prior art methods.

The above steps for implanting ions through one or more sidewalls 3a of an individual semiconductor device 1 are particularly useful if the electrically active area of the finished device does not exceed the diffusion length of the implanted species. This will be the case for many typical power components, such as the PIN diode 20, the BJT 30 and the IGBT 40 described above. However, in the case of relatively large electrically active areas or in the case that carbon vacancy V_C removal is required before separation of individual semiconductor circuit component, an implantation through a sidewall of the epitaxial layer 2 can also be achieved using one or more trenches formed in an epitaxial layer 2 as described in further detail below. This may also be used in semiconductor devices, in which trenches are formed throughout a normal manufacturing process anyhow.

FIG. 13 schematically shows a cross-sectional view of a semiconductor device 1 according to an embodiment of the disclosure. The semiconductor device 1 comprises an epitaxial layer 2 of a reduced concentration of carbon vacancy V_C.

The semiconductor device 1 comprises, besides the epitaxial layer 2, a trench 3 extending in the epitaxial layer 2. The trench 3 comprises an implantation layer 4 in form of an implanted carbon layer, which is provided on the trench sidewalls 3a and a trench bottom 3b. Instead of carbon (C), one of boron (B), aluminum (Al), germanium (Ge), nitrogen (N), phosphorus (P), arsenic (As), oxygen (O), sulfur (S), hydrogen (H), argon (Ar) or silicon (Si) may be implanted.

For example, the implantation may be performed by plasma immersion ion implantation (PIII). PIII can also be performed on the top surface of the epitaxial layer 2, e.g. the main or front surface of the epitaxial layer 2, at which the trench 3 opens. Thus, PIII can also be performed parallel to the [0001] crystallographic axis (not shown in FIG. 13). If PIII is applied at the front surface of the epitaxial layer 2, the formed PIII sublayer needs to be removed later by dry etching. However, as detailed below, this is not necessary for surfaces within the trench 3.

The epitaxial layer 2 comprises an epitaxial sublayer 2a of a reduced concentration of carbon vacancy V_C. As shown, the epitaxial sublayer 2a of the reduced concentration of carbon vacancy V_C extends perpendicular to a [0001] crystallographic axis and parallel to this axis, and a thickness of the epitaxial sublayer 2a of the reduced carbon vacancy at least corresponds to a depth D_T of the trench 3.

Without any treatment, the epitaxial layer 2 based on Silicon Carbon (SiC) comprises an amount of electrically active levels, corresponding to the carbon vacancy (V_C) concentration, which cannot be neglected. In FIG. 13, unfilled circles in the epitaxial layer are shown to illustrate the occurrence of carbon vacancy V_C as detailed above.

The inventors have found that after plasma immersion ion implantation of a suitable species, such as B, Al, C, Si, Ge, N, P, As, O, S, F, H or Ar, and annealing the implantation area at 1600° C., carbon vacancies V_C can be removed in an area of the epitaxial layer 2 below the implantation surface, for example a sublayer of 100 μm thickness along the [0001] crystallographic axis. However, as detailed above, in a direction perpendicular to the [0001] crystallographic axis, carbon vacancies V_C can be removed over a much larger distance. For example, a horizontal diffusion length of several millimeters can be achieved. The PIII implanted species are confined in a relatively small space, for example a sublayer having a thickness of less than 50 nm. This causes stress that releases C_I.

According to the exemplary embodiment of FIG. 13, the epitaxial layer 2 comprises the trench 3 with the implantation layer 4. The carbon layer 4, for example, has a thickness of less than 50 nm. As detailed above, the PIII carbon in the trench sidewalls 3a and trench bottom 3b provides carbon interstitials C_I, which are defects, and which can migrate perpendicular to the [0001] crystallographic axis and recombine with the electrically active defects providing the carbon vacancy V_C as detailed above. In FIG. 13, filled circles in the epitaxial layer 2 are shown to illustrate the carbon interstitials C_I.

In FIG. 13, the trench 3 extends parallel to or along the [0001] crystallographic axis of the epitaxial layer 2. The trench 3 may also extend at an angle α relative to the [0001] crystallographic axis. In such case, the thickness of the epitaxial sublayer 2a and the depth of the trench 3 are defined by L=D cos (α).

In this context, L is a length of the PIII carbon layer 4 from a trench inlet to a trench ending. In the exemplary embodiment of FIG. 13, L corresponds to the trench depth D_T. D is a distance, which is measured parallel to the [0001] crystallographic axis, from a beginning of the implantation layer 4 to an ending of the implantation layer 4 in the trench 3. In the exemplary embodiment of FIG. 13, D corresponds to the trench depth D_T. α is an angle between L and D. In the exemplary embodiment of FIG. 13, α is zero.

FIG. 14 schematically shows a deep level transient spectroscopy (DLTS) spectrum of an epitaxial layer 2 being treated by a method according to an embodiment. The epitaxial layer 2 is made of 4H-SiC. The DLTS spectrum is shown for the epitaxial layer 2 with and without Carbon diffusion perpendicular to the [0001] crystallographic axis. The curve indicated by the reference sign A represents the DLTS spectrum in untreated material, that means the level Z_1/2 is in a range of 10¹² 1/cm³. The curve indicated by the reference sign B represents the DLTS spectrum after implantation. It can be seen that no level Z_1/2 defects can be detected. Thus, as the FIG. 14 shows, after diffusion, the concentration of the level Z_1/2, that means the negative charge state of the electrically active defects providing the carbon vacancy V_C, is below a detection limit.

A manufacturing method according to an embodiment will be explained based on the flow diagram of FIG. 26 and specific embodiments as shown in FIGS. 15 to 19. The manufacturing method is suitable for providing a semiconductor device 1 with an epitaxial layer 2 with a reduced concentration of electrically active carbon levels in the epitaxial layer 2. The semiconductor device 1 produced according to the steps shown in FIGS. 3 to 7 is a Junction Barrier Schottky (JBS) diode 50.

According to a step S12, the method comprises providing an epitaxial layer 2 on a substrate 5 (see FIG. 26 and FIG. 15). The embodiment of FIG. 15 shows an n-type 4H-SiC epitaxial layer 2 with a doping concentration in a range from 10¹⁴ 1/cm³ to 10¹⁶ 1/cm³ being grown on a 4H-SiC substrate with a doping concentration of 10¹⁸ 1/cm³. The epitaxial layer thickness and doping are selected according to a voltage class of the semiconductor device 1.

According to a step S12, the method comprises providing a photoresist layer 51 on the epitaxial layer 2 (see FIG. 26 and FIG. 16) and exposing the photoresist layer 51 with electromagnetic radiation using a mask (not depicted). For example, the photoresist layer 51 being deposited on the epitaxial layer surface is patterned by photolithography according to the desired shape/dimensions of the trenches 3 which are provided in a subsequent step.

According to a step S13, the method comprises providing two trenches 3 in the epitaxial layer 2 (see FIG. 26 and FIG. 16). For example, the epitaxial layer 2 is etched by reactive ion etching (RIE) in order to form the trenches 3. The trenches 2 can have any cross section, such as square, round, rectangular, or polygonal. If D_T is the depth of the trench 3 and l the width of the cross section, deep trenches 3 (D_T>>l) can also be formed.

According to a step S14, the method comprises implanting carbon or another suitable species in each of the trenches 3 (see FIG. 26 and FIG. 17). In the described example, the trench sidewalls 3a and the trench bottom 3b of the trenches 3 are implanted with Carbon by plasma immersion ion implantation (PIII) to obtain the maximum doping concentration but not exceeding a solubility limit.

According to a step S15, the method comprises filling the trenches 3 with p-type polysilicon 52 (see FIG. 26 and FIG. 18). The step of filling the trenches 3 with p-type polysilicon 52 may be, alternatively, carried out after removing the photoresist layer 51 (see description in the context of step S16 below). As detailed later, filling the trenches 3 may assist in forming contacts, and generally will improve the mechanical stability of the finished semiconductor device 1.

According to a step S16, the method comprises carrying out an annealing process such that carbon ion diffusion from the at least one trench 3 perpendicular and/or parallel to a crystallographic [0001] axis of the at least one epitaxial layer 2 is induced (see FIG. 26; the diffusion process is not illustrated in FIG. 18; FIG. 13 illustrates the diffusion process of the carbon interstitials C_I). For example, Carbon is diffused by annealing at a temperature of less than 1600° C. for a time in the range from 5 minutes to 600 minutes. Subsequently, oxygen plasma ashing is, for example, employed to remove the photoresist layer 51.

Alternatively, the photoresist layer 51 can be removed after PIII in steps S14, and a graphitic cap is then formed on the epitaxial layer surface so to ensure low surface roughness on the trench walls 3a during activation. After annealing, a graphitic cap can be removed by oxygen plasma ashing.

Following Carbon diffusion, the epitaxial layer 2 has a V_C concentration below the detection limit.

According to a step S17, the method comprises providing contact layers 53 according to a functioning of the semiconductor device 1. In the exemplary embodiment, metal is deposited on an epitaxial layer surface and on a backside for Schottky/ohmic contact formation.

The manufacturing method according to the embodiment of FIG. 26 will also be described based on the FIGS. 20 to 22. The semiconductor device 1 produced according to the steps shown in FIGS. 20 to 22 is a Bipolar Junction Transistor (BJT) 30. In the exemplary embodiment, the BJT 30 is an NPN transistor.

FIG. 20 schematically shows a first step of the method for producing the BJT 30. Two epitaxial layers 2 are provided, which are grown on a substrate 5. The FIG. 20 shows an upper n-type 4H-SiC epitaxial layer 2 with a doping concentration in a range from 10¹⁴ 1/cm³ to 10¹⁶ 1/cm³. It is grown on a middle epitaxial p-type epitaxial layer 2 with a doping concentration in a range from 10¹⁴ 1/cm³ to 10¹⁶ 1/cm³ on top of a 4H-SiC substrate 5 with a doping concentration of 10¹⁸ 1/cm³. The layer thicknesses and doping concentrations are selected according to the voltage class of the BJT 30.

FIG. 21 schematically shows a second step of the method for producing the BJT 30. The epitaxial layers 2 are etched by reactive ion etching (RIE) in order to form two trenches 3. The trenches 3 can have any cross section, such as square, round, rectangular, or polygonal. Carbon is implanted in the trenches 3 by PIII and later diffused by annealing. After Carbon diffusion the upper epitaxial layer 2 corresponding to the n-type emitter 33 as well as the substrate 5 corresponding to the n-type collector 31 have a low carbon vacancy concentration. Trench sidewalls 3a and an epitaxial layer top can be protected by a graphitic cap.

FIG. 22 schematically shows a third step of a method for producing the BJT 30. In this step, oxygen plasma ashing is employed to remove the graphitic cap. Last, high-doped p-type layers 34 are formed and metal is deposited for providing gate electrodes 35, emitter electrodes 36, and collector electrodes 37.

The manufacturing method according to the embodiment of FIG. 26 will also be described based on the FIGS. 11 to 13. The semiconductor device 1 produced according to the steps shown in FIGS. 23 to 25 is an insulated-gate bipolar transistor (IGBT) 40.

FIG. 23 schematically shows a first step of the method for producing the IGBT 40. The FIG. 23 shows an n-type 4H-SiC epitaxial layer 2 with a doping concentration in a range from 10¹⁴ 1/cm³ to 10¹⁶ 1/cm³ on top of a 4H-SiC substrate 5 with a doping concentration of 10¹⁸ 1/cm³. The epitaxial layer and substrate thicknesses and doping concentrations are selected according to the voltage class of the IGBT 40.

FIG. 24 schematically shows a second step of the method for producing the IGBT 40. The epitaxial layer 2 is etched by reactive ion etching (RIE) in order to form two trenches 3. In this example, a depth D_T of the trenches 3 corresponds to a thickness of the epitaxial layer 2. A relatively deep trench 3 as shown in FIG. 24 assists in removing carbon vacancies throughout a relatively thick epitaxial layer 2. The trenches 3 can have any cross section, such as square, round, rectangular, or polygonal. Carbon is implanted in the trenches 3 by PIII and later diffused by annealing. After Carbon diffusion the epitaxial layer 2 comprising an n-type base 42 has a low carbon vacancy concentration. The trench sidewalls 3a and an epitaxial layer top can be protected by a graphitic cap.

FIG. 25 schematically shows a third step of the method for producing the IGBT 40. In this step, oxygen plasma ashing is employed to remove the graphitic cap. Two p-type base well 43 are formed by ion implantation and a total of four n-type areas 44 are formed inside them by either PIII or by ion implantation. Ion implantation would be carried out in a state, in which the device manufacturing is in the state shown in FIG. 24. At last, a gate electrode 46, an emitter electrode 47, and a collector electrode 48 are formed by e-beam deposition. The gate electrode 48 is provided with an oxide layer 45, which insulated the gate from the epitaxial layer 2 with the active electrical areas formed therein. A buffer layer can also be provided at the base/collector interface (not shown in FIG. 25).

The embodiments shown in the FIGS. 1 to 26 as stated represent exemplary embodiments of improved semiconductor devices and methods for their manufacturing. Therefore, they do not constitute a complete list of all embodiments according to the improved methods. Actual devices and methods may vary from the embodiments shown in terms of specific semiconductor material, doped areas and electrical electrodes, for example. In particular, while the embodiments described above are based on n-type 4H-SiC or n-type 6H-SiC semiconductor materials, other crystal types, such as 3C-SiC, or semiconductor types, such as p-type SiC, may also be used.

REFERENCE SIGNS

• • 1 semiconductor device
  • 2 epitaxial layer
  • 2 a epitaxial sublayer
  • 3 trench
  • 3 a sidewall
  • 3 b trench bottom
  • 4 implantation area
  • 4 a top surface area
  • 5 substrate
  • 20 PIN diode
  • 21 anode area
  • 22 field relaxation area
  • 23 anode electrode
  • 24 cathode electrode
  • 25 first implantation direction
  • 26 second implantation direction
  • 30 BJT
  • 31 collector
  • 32 base
  • 33 emitter
  • 34 highly doped p-type layer
  • 35 gate electrode
  • 36 emitter electrode
  • 37 collector electrode
  • 40 IGBT
  • 41 collector
  • 42 base
  • 43 p-type base well
  • 44 n-type area
  • 45 oxide layer
  • 46 gate electrode
  • 47 emitter electrode
  • 48 collector electrode
  • 50 JBS diode
  • 51 photoresist layer
  • 52 p-type polysilicon
  • 53 contact layer
  • A DLTS spectrum of untreated epitaxial layer
  • B DLTS spectrum of annealed epitaxial layer
  • C_I carbon interstitials
  • D_T trench depth
  • V_C carbon vacancy
  • X [0001] crystallographic axis direction

Claims

1. A semiconductor device, comprising: at least one epitaxial layer made from a silicon carbide semiconductor material and having a [0001] crystallographic axis; andat least one implantation area formed at a sidewall of the epitaxial layer, a normal direction of the sidewall being perpendicular to the [0001] crystallographic axis, the at least one implantation area comprising an implanted species, comprising at least one of carbon ions or silicon ions;wherein at least one part of the epitaxial layer has a reduced concentration of carbon vacancies (VC) with a concentration of carbon vacancy Z1/2 of below 1010/cm3.

2. The semiconductor device of claim 1, comprising at least one semiconductor chip comprising the at least one epitaxial layer, wherein the at least one implantation area is formed on at least one of a plurality of sidewalls of the at least one semiconductor chip.

3. The semiconductor device of claim 1, comprising at least one trench having two sidewalls formed in the at least one epitaxial layer, wherein the at least one implantation area is formed on at least one of the two sidewalls of the at least one trench,the at least one part of the epitaxial layer corresponds to a sublayer extending in a plane perpendicular to the [0001] crystallographic axis, anda thickness of the sublayer corresponds to or exceeds a depth (DT) of the at least one trench.

4. The semiconductor device of claim 1, further comprising: at least one electrode formed on a top or bottom surface of the at least one epitaxial layer, thereby forming an electrically active area, wherein the at least one implantation area is formed outside of the electrically active area.

5. The semiconductor device of claim 1, wherein the silicon carbide semiconductor material comprises at least one of n-type 4H-SiC or n-type 6H-SiC semiconductor material.

6. The semiconductor device of claim 1, wherein the at least one implantation area comprises an implantation defect area, comprising amorphous silicon.

7. The semiconductor device of claim 1, wherein the at least one part of the epitaxial layer has a concentration of deep peak levels, in particular ON1 or ON2, exceeding 1012/cm3.

8. The semiconductor device of claim 1, wherein the semiconductor device comprises at least one of: a PIN diode comprising a drift layer, wherein the at least one epitaxial layer comprises the drift layer;a BJT comprising an emitter, a collector and a base, wherein the at least one epitaxial layer comprises at least one of the emitter, the collector or the base;an IGBT comprising a base formed from the silicon carbide semiconductor material, wherein the at least one epitaxial layer comprises the base; ora JBS diode comprising a semiconductor body formed from the silicon carbide semiconductor material, wherein the at least one epitaxial layer comprises the semiconductor body.

9. A method for manufacturing a semiconductor device, comprising: growing at least one epitaxial layer, the at least one epitaxial layer made from a silicon carbide semiconductor material having a [0001] crystallographic axis; andimplanting ions, comprising at least one of carbon ions and silicon ions, through at least one sidewall of the at least one epitaxial layer to form at least one implantation area in a plane perpendicular to the [0001] crystallographic axis, thereby reducing a concentration of carbon vacancies (VC) in the first semiconductor material with respect to the at least one epitaxial layer as-grown.

10. The method of claim 9, further comprising at least one of: annealing the at least one epitaxial layer to further reduce a concentration of carbon vacancies (VC) in the silicon carbide semiconductor material with respect to the at least one epitaxial layer after implanting ions; orproton irradiating the at least one epitaxial layer to further reduce a concentration of carbon vacancies (VC) in the silicon carbide semiconductor material with respect to the at least one epitaxial layer after implanting ions.

11. The method of claim 9, before implanting ions through at least one sidewall, the method further comprises: performing a plurality of processing steps to form at least one semiconductor circuit component comprising at least parts of the at least one epitaxial layer; andseparating the at least one semiconductor circuit component to obtain a semiconductor chip having a top surface perpendicular to the [0001] crystallographic axis and a plurality of sidewalls perpendicular to the top surface.

12. The method of claim 11, comprising: forming a plurality of semiconductor circuit components on a carrier substrate carrying the at least one epitaxial layer;separating the plurality of semiconductor circuit components by dicing the carrier substrate carrying the at least one epitaxial layer along at least one cut surface perpendicular to the [0001] crystallographic axis; andimplanting the ions through the at least one cut surface.

13. The method of claim 11, wherein forming at least one semiconductor circuit component comprises implanting at least one first species through a surface of the at least one epitaxial layer in a first implantation direction parallel to the [0001] crystallographic axis before separating the at least one semiconductor circuit component; andimplanting ions through at least one sidewall comprises implanting at least one second species through the at least one sidewall of the at least one epitaxial layer in a second implantation direction orthogonal to the first implantation direction after separating the at least one semiconductor circuit component.

14. The method of claim 9, further comprising: forming at least one trench having two sidewalls within the at least one epitaxial layer,wherein implanting ions through at least one sidewall comprises plasma immersion ion implanting, PIII, of at least one of carbon ions or silicon ions through the two sidewalls of the at least one trench.

15. The method of claim 14, further comprising: filling the at least one trench after PIII; andforming at least one contact layer on a top surface of the at least one epitaxial layer after filling the at least one trench.

16. The method of claim 14, further comprising: forming at least one electrode at a bottom surface of the at least one trench.

17. The method of claim 9, before implanting ions through the at least one sidewall, the method further comprises: depositing at least one metal material on a surface of the at least one epitaxial layer; andannealing the at least one metal material to form an electrode, thereby increasing a concentration of carbon vacancies (VC) in the silicon carbide semiconductor material.