Semiconductor device having an insulating layer and method of fabricating the same

Abstract

A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1A-1F represent non-limiting, example embodiments as described herein.

FIGS. 1A through 1F are diagrams illustrating sectional views of a method of fabricating a semiconductor device according to example embodiments.

Claims

1. A semiconductor device, comprising: gate electrodes formed on a substrate;a first interlayer oxide layer formed on the substrate and between the gate electrodes;a second interlayer oxide layer formed on the first interlayer oxide layer, wherein the second interlayer oxide layer is harder than the first interlayer oxide layer; anda plug electrode formed through the second interlayer oxide layer and the first interlayer oxide layer.

2. The semiconductor device of claim 1, wherein the first interlayer oxide layer is a High Aspect Ratio Process (HARP) oxide layer.

3. The semiconductor device of claim 1, wherein the first interlayer oxide layer is a low dielectric constant film.

4. The semiconductor device of claim 3, wherein the low dielectric constant film is formed of SiOC.

5. The semiconductor device of claim 1, wherein the first interlayer oxide layer is planarized.

6. The semiconductor device of claim 1, wherein the second interlayer oxide layer is formed of a material selected from a group consisting of Tetra Ethyl Ortho Silicate (TEOS), Undoped Silica Glass (USG), Fluorine-doped Silica Glass (FSG) and a combination thereof.

7. The semiconductor device of claim 1, wherein the plug electrode is formed of tungsten.

8. The semiconductor device of claim 1, wherein a portion of the second interlayer oxide layer around the plug electrode resists erosion after chemical-mechanical polishing.

9. The semiconductor device of claim 1, wherein the second interlayer oxide layer is formed of a material having a lower etch rate than the first interlayer oxide layer.

10. The semiconductor device of claim 1, wherein the first interlayer oxide layer is formed of a material that decreases parasitic capacitance between the gate electrodes.

11. A method of fabricating a semiconductor device, comprising: forming gate electrodes on a substrate;forming a first interlayer oxide layer on the substrate and between the gate electrodes;forming a second interlayer oxide layer on the first interlayer oxide layer, wherein the second interlayer oxide layer is harder than the first interlayer oxide layer;forming a contact hole through the second interlayer oxide layer and the first interlayer oxide layer;forming a first interconnect conductive layer on the second interlayer oxide layer in the contact hole; andchemical-mechanical polishing the first interconnect conductive layer to form a plug electrode.

12. The method of claim 11, wherein forming the first interlayer oxide layer includes forming a High Aspect Ratio Process (HARP) oxide layer.

13. The method of claim 11, wherein forming the first interlayer oxide layer includes forming a low dielectric constant film.

14. The method of claim 13, wherein the low dielectric constant film is formed of SiOC.

15. The method of claim 11, further comprising chemical-mechanical polishing the first interlayer oxide layer prior to forming the second interlayer oxide layer.

16. The method of claim 11, wherein the second interlayer oxide layer is formed of a material selected from a group consisting of Tetra Ethyl Ortho Silicate (TEOS), Undoped Silica Glass (USG), Fluorine-doped Silicate Glass (FSG) and a combination thereof.

17. The method of claim 11, wherein the first interconnect conductive layer is formed of tungsten.

18. The method of claim 11, wherein a portion of the second interlayer oxide layer around the plug electrode resists erosion after chemical-mechanical polishing.

19. The method of claim 11, wherein the second interlayer oxide layer is formed of a material having a lower etch rate than the first interlayer oxide layer.

20. The method of claim 11, wherein forming the first interlayer oxide layer is formed of a material that decreases parasitic capacitance between the gate electrodes.