Claims
- 1. A method of manufacturing a semiconductor device, comprising the steps of:
forming, above a semiconductor substrate, a first gate electrode of a first MISFET operating at a first operating voltage and a second gate electrode of a second MISFET operating at a second operating voltage higher than the first operating voltage; performing ion implantation, thereby forming a first LDD of the first MISFET and a second LDD of the second MISFET in the semiconductor substrate; forming a first film covering the first and second gate electrodes, above the semiconductor substrate; performing anisotropic etching on the first film, thereby forming a first side-all film on sides of the first and second gate electrodes; performing ion implantation, thereby forming a first source/drain diffusion layer of the first MISFET in the semiconductor substrate; forming a second film covering the first and second gate electrode, above the semiconductor substrate; performing anisotropic etching on the second film, thereby forming a second side-all film on sides of the first and second gate electrodes; and performing ion implantation, thereby forming a second source/drain diffusion layer of the second MISFET in the semiconductor substrate.
- 2. A method of manufacturing a semiconductor device, comprising the steps of:
forming, above a semiconductor substrate, a first gate electrode of a first MISFET operating at a first operating voltage and a second gate electrode of a second MISFET operating at a second operating voltage higher than the first operating voltage; performing ion implantation, thereby forming a first LDD of the first MISFET and a second LDD of the second MISFET in the semiconductor substrate; forming a first film covering the first and second gate electrodes, above the semiconductor substrate; forming a second film on the first film, said second film being different in material from the first film; performing anisotropic etching on the second film, thereby forming a first side-all film at a stepped part near the first gate electrode and a stepped part near the second gate electrode; and performing ion implantation, thereby forming a first source/drain diffusion layer of the first MISFET and a second source/drain diffusion layer of the second MISFET, in the semiconductor substrate.
- 3. A method of manufacturing a semiconductor device, comprising the steps of:
forming, above a semiconductor substrate, a first gate electrode of a first MISFET operating at a first operating voltage and a second gate electrode of a second MISFET operating at a second operating voltage higher than the first operating voltage; performing ion implantation, thereby forming a first LDD of the first MISFET and a second LDD of the second MISFET in the semiconductor substrate; forming a first film covering the first and second gate electrodes, above the semiconductor substrate; forming a second film on the first film, said second film being different in material from the first film; performing partial etching on the second film, thereby removing a part of the second film which lies above the first MISFET and leaving the second film above the second MISFET; performing anisotropic etching on the second film, thereby forming a first side-wall film at a stepped part near the second gate electrode; performing anisotropic etching on the first film, thereby forming a second side-all film on sides of the first and second gate electrodes; and performing ion implantation, thereby forming a first source/drain diffusion layer of the first MISFET and a second source/drain diffusion layer of the second MISFET in the semiconductor substrate.
Priority Claims (2)
Number |
Date |
Country |
Kind |
11-046728 |
Feb 1999 |
JP |
|
10-159205 |
Jun 1998 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of U.S. patent application Ser. No. 09/327,517, filed Jun. 8, 1999, which is based upon and claims the benefit of priority from the prior Japanese Patent Application Nos. 11-046728, filed Feb. 24, 1999 and 10-159205, filed Jun. 8, 1998, the entire contents of which are incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09327517 |
Jun 1999 |
US |
Child |
10060297 |
Feb 2002 |
US |