Claims
- 1. A method for fabricating a semiconductor device having reduced field oxide recess, comprising the steps of:
(a) performing a HF dip process on a substrate after field oxidation; (b) performing a select gate oxidation; (c) performing an implant; (d) depositing a tunnel oxide mask; (e) performing an etch to remove the select gate oxide uncovered by the mask; and (f) performing a tunnel oxidation.
- 2. The method of claim 1 further including the step of performing steps (a)-(f) in a select gate region of a flash memory array.
- 3. The method of claim 2 wherein step (a) further includes the step of:
(i) performing the HF dip for a time necessary to remove approximately 70 angstroms of material.
- 4. A memory array having reduced field oxide recess, comprising;
a word-line region where word-line gates are located; and a select gate region where select gates are located, wherein the select gate region is formed by (a) performing a HF dip process on a substrate after field oxidation, (b) performing a select gate oxidation, (c) performing a core implant, (d) performing a field implant, (e) depositing a tunnel oxide mask, (f) performing an etch to remove the select gate oxide uncovered by the mask, and (c) performing a tunnel oxidation.
- 5. The memory array of claim 4 wherein step (a) further includes the step of:
(i) performing the HF dip for a time necessary to remove approximately 70 angstroms of material.
- 6. The memory array of claim 5 wherein the memory array is a flash memory array.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is claiming under 35 USC 120 the benefit of provisional patent application Ser. No. 60/169,187 filed on Dec. 6, 1999.
Provisional Applications (1)
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Number |
Date |
Country |
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60169187 |
Dec 1999 |
US |