Semiconductor device having shallow B-doped region and its manufacture

Information

  • Patent Application
  • 20070232039
  • Publication Number
    20070232039
  • Date Filed
    December 04, 2006
    17 years ago
  • Date Published
    October 04, 2007
    16 years ago
Abstract
A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of the semiconductor substrate into which ions were implanted; and (d) after the step (c) is performed, executing second annealing with a heating time longer than the heating time of the first annealing, relative to the region of the semiconductor substrate into which ions were implanted. The method for manufacturing a semiconductor device is provided which can dope boron (B) shallowly and at a high concentration.
Description

BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a flow chart illustrating the procedure of a first experiment.



FIGS. 2A and 2B are a graph and a table showing B concentration profiles obtained by SIMS measurements of the first experiment.



FIG. 3 is a graph showing sheet resistances of B doped regions obtained by the first experiment.



FIG. 4 is a flow chart illustrating the procedure of a second experiment.



FIGS. 5A and 5B are a graph and a table showing B concentration profiles obtained by SIMS measurements of the second experiment.



FIGS. 6A to 6J are schematic cross sectional views illustrating the processes of a CMOS semiconductor device manufacture method according to a first embodiment.



FIG. 7 is a graph showing the transistor characteristics of samples manufactured by the method of the first embodiment and comparative samples.



FIGS. 8A to 8H are schematic cross sectional views illustrating the processes of a CMOS semiconductor device manufacture method according to a second embodiment.



FIG. 9 is a graph showing the transistor characteristics of samples manufactured by the method of the second embodiment and comparative samples.


Claims
  • 1. A method for manufacturing a semiconductor device, comprising the steps of: (a) implanting boron (B) ions into a semiconductor substrate;(b) implanting fluorine (F) or nitrogen (N) ions into said semiconductor device;(c) after said steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of said semiconductor substrate into which ions were implanted; and(d) after said step (c) is performed, executing second annealing with a heating time longer than the heating time of said first annealing, relative to the region of said semiconductor substrate into which ions were implanted.
  • 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: (e) before said steps (a) and (b), forming an insulated gate structure on a surface of said semiconductor substrate.
  • 3. The method for manufacturing a semiconductor device according to claim 2, wherein: said semiconductor substrate includes an n-type active region;said step (e) forms said insulated gate structure on said n-type active region; andsaid step (a) forms p-type extension regions of source/drain regions of a p-channel transistor in said n-type active region on both sides of said insulated gate structure.
  • 4. The method for manufacturing a semiconductor device according to claim 3, further comprising the step of: (f) after said step (e), implanting n-type impurity ions into said n-type active region deeper than said extension regions to form n-type pocket regions.
  • 5. The method for manufacturing a semiconductor device according to claim 2, wherein: said semiconductor substrate includes a p-type active region;said step (e) forms said insulated gate structure on said p-type active region; andsaid step (a) forms p-type pocket regions of an n-channel transistor in said p-type active region on both sides of said insulated gate structure.
  • 6. The method for manufacturing a semiconductor device according to claim 1, wherein said steps (a) and (b) are executed at a same time by implanting BF or BF2 ions.
  • 7. A method for manufacturing a semiconductor device comprising the steps of: (a) implanting impurity ions into a semiconductor substrate;(b) after said step (a) is performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of said semiconductor substrate into which ions were implanted; and(c) after said step (b) is performed, executing second annealing with a heating time longer than the heating time of said first annealing, relative to the region of said semiconductor substrate into which ions were implanted, before other annealing processes are executed.
  • 8. A semiconductor device comprising: a semiconductor substrate; anda p-type region formed on said semiconductor substrate and containing boron (B) and fluorine (F) or nitrogen (N), wherein a B concentration rapidly lowers from a surface of said semiconductor substrate as a depth becomes deeper, then gradually lowers forming a kink, and a B concentration at a depth of the kink is 2×1020 cm−3 or higher.
  • 9. The semiconductor device according to claim 8, wherein said semiconductor substrate includes an n-type active region; further comprising: an insulated gate electrode formed on a surface of said n-type active region; andwherein said p-type region is extension regions of source/drain regions formed on both sides of said insulated gate electrode.
  • 10. The semiconductor device according to claim 9, further comprising: n-type pocket regions covering said extension regions.
Priority Claims (1)
Number Date Country Kind
2006-094702 Mar 2006 JP national