Claims
- 1. A semiconductor device comprising:
- a semiconductor substrate having a first insulating layer thereon;
- a semiconductor on insulator (SOI) layer formed on the insulating layer;
- a transistor formed in an active region of said semiconductor SOI layer; and
- a field shield gate electrode formed only in an element isolation region under said semiconductor SOI layer with a second insulating layer interposed therebetween.
- 2. The semiconductor device according to claim 1, wherein
- a conductive layer is formed under said first insulating layer; and
- said field shield gate electrode and said conductive layer are electrically connected to each other with a plug electrode provided in said first insulating layer.
- 3. The semiconductor device according to claim 1, wherein
- a third insulating layer is formed in the element isolation region of said semiconductor layer; and
- a gate electrode is formed on said third insulating layer with a gate insulating film interposed therebetween.
- 4. The semiconductor device according to claim 3, wherein said third insulating layer has a thickness of approximately 500.ANG..
- 5. The semiconductor device according to claim 1, wherein said transistor includes:
- a first field effect transistor; and
- a second field effect transistor formed to sandwich said element isolation region with said first field effect transistor.
- 6. The semiconductor device according to claim 1, wherein
- a third interlayer insulating film is formed to have its upper surface planarized so as to cover said semiconductor layer and said transistor;
- a contact hole is formed at source/drain regions of said transistor in said interlayer insulating film;
- a plug electrode is buried in said contact hole; and
- an aluminum interconnection is formed in contact with the upper surface of said plug electrode.
- 7. The semiconductor device according to claim 1, wherein a gate electrode is formed on said semiconductor layer where said field shield gate electrode is located, with a gate insulating film interposed therebetween.
- 8. The semiconductor device according to claim 1, wherein
- said transistor is an n-type field effect transistor; and
- zero or negative voltage is applied to said field shield gate electrode.
- 9. The semiconductor device according to claim 1, wherein said second insulating layer and said field shield gate electrode are buried in said first insulating layer.
- 10. A semiconductor device manufacturing method comprising the steps of:
- forming a semiconductor layer on a first insulating layer;
- forming a transistor in an active region of said semiconductor layer; and
- forming a second insulating layer and a field shield gate electrode to be buried in said first insulating layer located under an element isolation region of said semiconductor layer.
- 11. A semiconductor device manufacturing method comprising the steps of:
- forming a field shield gate electrode in an element isolation region on the main surface of a first semiconductor substrate with a first insulating film interposed therebetween;
- forming a second insulating film to cover said field shield gate electrode and then forming a contact hole above said field shield gate electrode;
- forming a conductive layer to be buried in said contact hole;
- forming a second semiconductor substrate to be in contact with the upper surface of said second insulating film and the upper surface of said conductive layer; and
- forming a semiconductor layer by cutting the rear surface of said first semiconductor substrate by a predetermined thickness.
Priority Claims (1)
Number |
Date |
Country |
Kind |
6-293205 |
Nov 1994 |
JPX |
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Parent Case Info
This application is a continuation of Application Ser. No. 08/487,049 filed Jun. 7, 1995, now abandoned.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
5324960 |
Pfiester et al. |
Jun 1994 |
|
5440161 |
Iwamatsu et al. |
Aug 1995 |
|
Foreign Referenced Citations (5)
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Country |
4-176165 |
Jun 1992 |
JPX |
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5-183157 |
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JPX |
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Non-Patent Literature Citations (1)
Entry |
A.H. Hamdi, et al, "Novel SOI CMOS Design Using Ultra Thin Near Intrinsic Substrate," 1982 IEDM, pp. 107-110. |
Continuations (1)
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Number |
Date |
Country |
Parent |
487049 |
Jun 1995 |
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