Patent Application
20080185629
This application is based on Japanese Patent Applications No. 2006-27092 filed on Feb. 3, 2006, and No. 2007-23324 filed on Feb. 1, 2007, the disclosures of which are incorporated herein by reference.
The present invention relates to a semiconductor device having variable operating information.
Heretofore, as a semiconductor device of this type, there has been known a semiconductor device wherein, as the partial side sectional structure thereof is exemplified in
As shown in
Here, the channel region 102 is formed in a manner to surround a substrate contact portion 103 which is made of a diffusion layer of P-type (P+) formed at a concentration higher than that of the channel region 102, and a source region 104 which is made of a diffusion layer of N-type (N+) formed at a concentration higher than that of the drain region 101. Besides, the drain region 101 is formed with a drain contact portion 105 which is made of a diffusion layer (N+) at a concentration higher than that of this drain region 101.
On the other hand, a field oxide film (LOCOS oxide film) 106 which has a LOCOS structure is formed in the vicinity of the channel region 102 of the substrate 100 so as to isolate the channel region 102 and the drain contact portion 105 from each other. In addition, a gate electrode 107 made of, for example, polycrystal silicon is formed on the channel region 102 through a gate insulating film GI made of, for example, silicon oxide, and so as to partly overlap the LOCOS oxide film 106.
Incidentally, as shown in
In the semiconductor device thus configured, an operating voltage is applied from the operating voltage input terminal Vin to the gate electrode 107, whereby an inversion layer is formed between the drain region 101 and the source region 104, more exactly, at the part of the channel region 102 directly under the gate electrode 107, and current flows within the inversion layer. In addition, the operating voltage which is applied from the operating voltage input terminal Vin to the gate electrode 107 is regulated, whereby the quantity of the current which flows between the drain region 101 and the source region 104 can be made variable.
Meanwhile, in manufacturing such a semiconductor device, required values for an on-resistance, a switching time, etc. which correspond to the quantity of the current flowing through the channel region 102 are usually found in consideration of, for example, the supposed magnitude of the load to-be-operated which is connected to the drain region 101 (exactly, the drain contact portion 105). In addition, the total layout including the sizes and impurity concentrations of the individual impurity regions, etc. as the semiconductor device is determined so as to satisfy the required values. However, even when the semiconductor device has been successfully manufactured under the layout thus determined, the readjustments of the on-resistance, the switching time, etc. are sometimes needed for such a reason as the alteration of the load to-be-operated which is connected, or the problem of heat generation or the like. Since, however, a degree of freedom for the alterations of such required values is very low in the prior-art semiconductor device configured as the lateral MOS, design alterations such as changing a layout size so as to suit the required values have been eventually inevitable. That is, the semiconductor device itself is remade from the beginning in correspondence with the alteration of the load to-be-operated which is connected, or the like.
Incidentally, such circumstances are not restricted to the semiconductor device having the lateral MOS structure, but they are substantially common to a semiconductor device which is configured as a transistor having a general MOS structure.
That is, in the semiconductor devices, it is requested to cope with the adjustments and alterations of the various required values at a high degree of freedom even in a case where the readjustments of the required values are needed due to, for example, the alteration of the load.
In view of the above-described problem, it is an object of the present disclosure to provide a semiconductor device having variable operating information.
According to a first aspect of the present disclosure, a semiconductor device includes: a semiconductor substrate; a plurality of MOS type first transistors disposed on the semiconductor substrate; and a nonvolatile memory for memorizing an operating information of each first transistor. The plurality of first transistors is electrically coupled in parallel with a current path. Each first transistor includes a first electrode and a second electrode disposed on the current path, and further includes a gate electrode for controlling current flowing between the first and second electrodes based on an applied voltage. The operating information of each first transistor is variably set. Each first transistor is selectively set to an active state based on the operating information. When the plurality of first transistors provides a single transistor, an effective channel width of the single transistor is variable in accordance with the number of the first transistors under the active state.
In the semiconductor device having the above structure, assuming that separated multiple transistors provide a single transistor, an on-state resistance and/or a switching time are adjustable by controlling the operating information variably set in the nonvolatile memory even after the semiconductor device is manufactured. Accordingly, even when various requirements are necessary to adjust again in accordance with change of a load, it is possible to deal with the change and adjustment of requirements with high degree of freedom.
According to a second aspect of the present disclosure, a semiconductor device includes: a plurality of MOS type first transistors. The plurality of first transistors is electrically coupled in parallel with a current path. Each first transistor includes a first electrode and a second electrode disposed on the current path, and further includes a gate electrode for controlling current flowing between the first and second electrodes based on an applied voltage. The gate electrode of at least one of first transistors includes a first gate electrode and a second gate electrode. The first gate electrode is disposed on the first electrode and covers a channel region. The second gate electrode is disposed on the channel region and covers the second electrode.
In the above semiconductor device, the first gate electrode and the second gate electrode have channel layers, respectively. Accordingly, a voltage applied to the first gate electrode is independently controlled from a voltage applied to the second gate electrode so that much complicated control can be performed.
According to a third aspect of the present disclosure, a semiconductor device includes: a plurality of MOS type first transistors. The plurality of first transistors is electrically coupled in parallel with a current path. Each first transistor includes a first electrode and a second electrode disposed on the current path, and further includes a gate electrode for controlling current flowing between the first and second electrodes based on an applied voltage. The gate electrode of at least one of first transistors includes a first control electrode and a second control electrode. The first control electrode covers a channel region disposed from the first electrode to the second electrode. The first control electrode opens and closes between the first electrode and the second electrode. The second control electrode covers the second electrode.
In the above device, the first control electrode functioning as a gate electrode turns on and off (i.e., opens and closes). The charge accumulation layer provided by the second control electrode controls a current flowing amount, i.e., a resistance. Accordingly, an on-state resistance is much accurately controlled, compared with a case where a transistor is simply controlled to turn on and off. Further, only the first control electrode substantially functions as the gate electrode. Thus, a facing area between the first control electrode and the second electrode becomes small, so that a parasitic capacitance is reduced.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
Now, a first embodiment of a semiconductor device according to this invention will be described with reference to
In this embodiment, a configuration to be stated below is basically adopted as will be detailed later. A transistor having an LDMOS structure which includes drain and source electrodes that are connected so as to intervene in the path of current, and a gate electrode that controls the current to flow between the drain and source electrodes in accordance with an applied voltage is arrayed and formed in a semiconductor substrate in a manner to be divided into a plurality of transistors which are electrically connected in parallel with the path of the current. In addition, operating information which indicates whether or not operating voltages are to be applied to the respective gate electrodes of the plurality of transistors constituting the LDMOS region can be variably set in a plurality of memory cells which constitute a nonvolatile memory region in the identical semiconductor substrate, and the plurality of transistors are selectively activated on the basis of the set operating information. Thus, the required values of an on-resistance, a switching time, etc. at the time when the plurality of transistors are regarded as a single transistor are made variable, and even in a case, for example, where the readjustments of the required values are needed due to the alteration of a load, the adjustments and alterations of the required values can be coped with at a high degree of freedom.
First, as shown in
In the LDMOS region 10 of them, as stated above, the transistor having the LDMOS structure is arrayed and formed in the semiconductor substrate C1 in a manner to be divided into, for example, five transistors L11-L15 which are electrically connected in parallel with the path of the current. Each of the transistors L11-L15 has a structure similar to the LDMOS structure exemplified in
Besides, the five memory cells M11-M15 in the same number as that of the transistors L11-L15 are formed in the nonvolatile memory region 11 which is formed of an electrically rewritable nonvolatile memory (for example, EPROM). Also each of the memory cells M11-M15 has a MOS structure basically, and as shown in
Incidentally, the control gate electrodes CG of the memory cells M11-M15 are connected to a voltage control circuit (not shown), and predetermined voltages which correspond to the logic levels of rewritable information items of 5 bits constituting the operating information of the transistors L11-L15 are applied to the respective control gate electrodes CG through the voltage control circuit. Concretely, a voltage at a magnitude which brings the corresponding memory cell into an on-state is applied to the control gate electrode CG of the memory cell which corresponds to the bit that lies at, for example, a logic H (high) level among the bits constituting the operating information. On the other hand, a voltage at a magnitude which brings the corresponding memory cell into an off-state is applied to the control gate electrode CG of the memory cell which corresponds to the bit that lies at, for example, a logic L (low) level among the bits constituting the operating information. Thus, the on/off-states of the lines which couple the source electrodes S of the memory cells M11-M15 and the gate electrodes G of the transistors L11-L15, namely, the application lines of the operating voltages are respectively changed-over.
Meanwhile, as shown in
Here, in this embodiment, as the planar structure of the transistors L11-L15 constituting the LDMOS region 10 is shown in
On the other hand, as shown in
Next, there will be described a method for adjusting the effective channel width ChW at the time when the LDMOS region 10 is regarded as the single transistor, in the semiconductor device configured as stated above. Incidentally, the adjustment can be executed at will even after the manufacture of the semiconductor device.
In making the adjustment, the operating information which indicates whether or not the operating voltages are to be applied to the gate electrodes G (G11-G15) of the transistors L11-L15 (
As described above, in accordance with the semiconductor device according to the first embodiment, advantages to be listed below are obtained.
(1) The operating information which indicates whether or not the operating voltages are to be applied to the gate electrodes G (G11-G15) of the transistors L11-L15 constituting the LDMOS region 10 is variably set in the nonvolatile memory region 11, and the transistors L11-L15 are selectively activated on the basis of the operating information. Thus, even after the manufacture of the semiconductor device, the required values of the on-resistance, the switching time, etc. at the time when the transistors L11-L15 are regarded as the single transistor can be adjusted through the application aspect of the operating voltages to the gate electrodes G (G11-G15). Accordingly, even in the case, for example, where the readjustments of the required values are needed due to the alteration of the load, or the like, the adjustments and alterations of the required values can be coped with at a high degree of freedom.
(2) The LDMOS region 10 and the nonvolatile memory region 11 are formed on the identical semiconductor substrate C1. Thus, reduction in size can be attained as the semiconductor device. Besides, as regards the transistors L11-L15 constituting the LDMOS region 10 and the memory cells M11-M15 constituting the nonvolatile memory region 11, many of semiconductor manufacturing processes are common, and hence, reduction in the manufacturing man-hour of the semiconductor device can be attained.
(3) The drain electrodes (regions) D and source electrodes (regions) S of the transistors L11-L15 are electrically connected through the diffusion layers, respectively. Thus, it is dispensed with to lay metallic wirings or the like which serve to electrically connect the transistors L11-L15 in parallel with the path of the current extending from the circuit power source Vc to the ground (GND), so that the simplification of the structure, as well as the simplification of the manufacturing process can be attained. Moreover, as compared with the case of laying the metallic wirings or the like, the embodiment sweeps off the apprehension of disconnection, etc., so that the semiconductor device of higher reliability can be realized.
Next, a second embodiment of a semiconductor device according to this invention will be described with reference to
Also the semiconductor device of this embodiment has a configuration which basically conforms to the first embodiment shown in
First, as shown in
In the LDMOS region 20 of them, in the same manner as in the foregoing first embodiment, the transistor having the LDMOS structure is arrayed and formed in the semiconductor substrate C2 in a manner to be divided into, for example, five transistors L21-L25 which are electrically connected in parallel with the path of the current. Each of the transistors L21-L25 has a structure conforming to the LDMOS structure exemplified in
Besides, the five memory cells M21-M25 in the same number as that of the transistors L21-L25 are formed in the nonvolatile memory region 21 which is formed of an electrically rewritable nonvolatile memory (for example, EPROM), in the same manner as in the foregoing first embodiment. Also each of the memory cells M21-M25 has a MOS structure basically, and as shown in
Incidentally, also the control gate electrodes CG of the memory cells M21-M25 are connected to a voltage control circuit (not shown) in the same manner as in the foregoing first embodiment. In addition, predetermined voltages which correspond to the logic levels of rewritable information items of 5 bits constituting the operating information of the transistors L21-L25 are applied to the respective control gate electrodes CG through the voltage control circuit. Concretely, a voltage at a magnitude which brings the corresponding memory cell into an on-state is applied to the control gate electrode CG of the memory cell which corresponds to the bit that lies at, for example, a logic H (high) level among the bits constituting the operating information. On the other hand, a voltage at a magnitude which brings the corresponding memory cell into an off-state is applied to the control gate electrode CG of the memory cell which corresponds to the bit that lies at, for example, a logic L (low) level among the bits constituting the operating information.
Besides, the five MOS transistors N21-N25 also in the same number as that of the transistors L21-L25 are formed in the N-channel MOS region 22. As shown in
Meanwhile, as shown in
Further, as shown in
In this embodiment, in this manner, the memory cells M21-M25 constituting the nonvolatile memory region 21 function as switching elements for performing switching, in a manner to intervene in the application lines of the memory voltages. The on/off changeover of the application lines of the operating voltages (transistors L21-L25) is executed through the manipulations of the activation/inactivation of such application lines of the memory voltages (MOS transistors N21-N25).
Here, also in this embodiment, as the planar structure of the transistors L21-L25 constituting the LDMOS region 20 is shown in
On the other hand, also here, as shown in
Next, there will be described a method for adjusting the effective channel width ChW at the time when the LDMOS region 20 is regarded as the single transistor, in the semiconductor device configured as stated above. Incidentally, also the adjustment can be executed at will even after the manufacture of the semiconductor device, in the same manner as in the foregoing first embodiment.
In making the adjustment, the operating information which indicates whether or not the operating voltages are to be applied to the gate electrodes G (G21-G25) of the transistors L21-L25 (
When the MOS transistors N21-N25 are selectively activated on the basis of the operating information in this way, currents flow from the operating voltage input terminal Vin, between the drain electrodes D and source electrodes S of the activated MOS transistors, on the basis of the operating voltages applied to the drain electrodes D of the MOS transistors N21-N25. In addition, the currents flow through the pull-down resistors connected to the lines which succeed to the MOS transistors, and they lead to the ground (GND). In the lines through which the currents have flowed in this way, the divided voltages of the operating voltages based on the on-resistances of the activated MOS transistors and the pull-down resistors corresponding thereto are applied to the gate electrodes G of the corresponding transistors among the transistors L21-L25, and the transistors to which the divided voltages have been applied are activated. That is, current fed from the circuit power source Vc to the load to-be-operated Ld flows through only the activated transistors, and the effective channel width ChW at the time when the activated transistors L21-L25 are regarded as the single transistor is made variable within the semiconductor substrate C2.
As described above, in accordance with the semiconductor device according to the second embodiment, advantages to be listed below are obtained.
(1) The operating information which indicates whether or not the operating voltages are to be applied to the gate electrodes G (G21-G25) of the transistors L21-L25 constituting the LDMOS region 20 is variably set in the memory cells M21-M25. In addition, the transistors L21-L25 are selectively activated on the basis of the operating information, through the operations of the MOS transistors N21-N25 which are connected in a manner to respectively intervene in the application lines of the operating voltages to the gate electrodes G of the transistors L21-L25. Thus, even after the manufacture of the semiconductor device, the required values of the on-resistance, the switching time, etc. at the time when the transistors L21-L25 are regarded as the single transistor can be adjusted through the application aspect of the operating voltages to the gate electrodes G (G21-G25). Accordingly, even in the case, for example, where the readjustments of the required values are needed due to the alteration of the load, or the like, the adjustments and alterations of the required values can be coped with at a high degree of freedom. Moreover, in this case, owing to the intervention of the MOS transistors N21-N25, the gate resistors of the transistors L21-L25 and the on-resistances of the memory cells M21-M25 constructing the switching elements can be independently set unlike in the foregoing first embodiment.
(2) The LDMOS region 20 and the nonvolatile memory region 21 are formed on the identical semiconductor substrate C2. Thus, reduction in size can be attained as the semiconductor device. Besides, as regards the transistors L21-L25 constituting the LDMOS region 20, the memory cells M21-M25 constituting the nonvolatile memory region 21, and the MOS transistors N21-N25 constituting the N-channel MOS region 22, many of semiconductor manufacturing processes are common, and hence, reduction in the manufacturing man-hour of the semiconductor device can also be attained.
(3) The drain electrodes (regions) D and source electrodes (regions) S of the transistors L21-L25 are electrically connected through the diffusion layers, respectively. Thus, it is dispensed with to lay metallic wirings or the like which serve to electrically connect the transistors L21-L25 in parallel with the path of the current extending from the circuit power source Vc to the ground (GND), so that the simplification of the structure, as well as the simplification of the manufacturing process can be attained. Moreover, as compared with the case of laying the metallic wirings or the likes, the embodiment sweeps off the apprehension of disconnection, etc., so that the semiconductor device of higher reliability can be realized.
Incidentally, the first and second embodiments described above can also be performed by appropriately altering them in, for example, aspects stated below.
The first and second embodiments have adopted the structure in which the drain electrodes D and source electrodes S of the transistors L11-L15 or the transistors L21-L25 are electrically connected through the diffusion layers formed in the semiconductor substrate C1 or C2, respectively. However, this structure is not restrictive, but it is also allowed to adopt a structure in which, not only the gate electrodes G, but also the drain electrodes D and the source electrodes S are respectively isolated on the semiconductor substrate, whereupon they are electrically connected through suitable wirings.
In the first and second embodiments, the nonvolatile memory region 11 or 21 or the N-channel MOS region 22 has been collectively formed in the single semiconductor substrate C1 or C2 formed with the LDMOS region 10 or 20, but this configuration is not restrictive. Alternatively, it is also allowed, for example, that the memory cells M11-M15 or M21-M25 constituting the nonvolatile memory region 11 or 21, and the MOS transistors N21-N25 constituting the N-channel MOS region 22 are formed in another semiconductor substrate, and that they are respectively connected to the transistors L11-L15 or L21-L25 constituting the LDMOS region 10 or 20 formed in the semiconductor substrate C1 or C2, through suitable wirings. In short, an aspect for realization is as desired with any structure in which the equivalent circuit shown in
Next, a third embodiment of a semiconductor device according to this invention will be described with reference to
Also the semiconductor device of this embodiment has a configuration which basically conforms to the first embodiment shown in
First, as shown in
In the LDMOS region 30 of them, in the same manner as in the foregoing first embodiment, the transistor having the LDMOS structure is arrayed and formed in the semiconductor substrate C3 in a manner to be divided into, for example, five transistors L31-L35 which are electrically connected in parallel with the path of the current. Each of the transistors L31-L35 has a structure conforming to the LDMOS structure exemplified in
Besides, the five memory cells M31-M35 in the same number as that of the transistors L31-L35 are formed in the nonvolatile memory region 31 which is formed of an electrically rewritable nonvolatile memory (for example, EPROM), also in the same manner as in the foregoing first embodiment. Also each of the memory cells M31-M35 has a MOS structure basically, and as shown in
Incidentally, the control gate electrodes CG of the memory cells M31-M35 are connected to a voltage control circuit (not shown) in the same manner as in the foregoing first embodiment. In addition, predetermined voltages which correspond to the logic levels of rewritable information items of 5 bits constituting the operating information of the transistors L31-L35 are applied to the respective control gate electrodes CG through the voltage control circuit. Concretely, a voltage at a magnitude which brings the corresponding memory cell into an on-state is applied to the control gate electrode CG of the memory cell which corresponds to the bit that lies at, for example, a logic H (high) level among the bits constituting the operating information. Thus, the current feed to the transistor connected to a stage succeeding to the corresponding memory cell is permitted. On the other hand, a voltage at a magnitude which brings the corresponding memory cell into an off-state is applied to the control gate electrode CG of the memory cell which corresponds to the bit that lies at, for example, a logic L (low) level among the bits constituting the operating information. Thus, the current feed to the transistor connected to a stage succeeding to the corresponding memory cell is inhibited. In this way, the memory cells M31-M35 constituting the nonvolatile memory region 31 function as switching elements for performing the switching (on/off) of the transistors L31-L35, in a manner to intervene in lines which couple the source electrodes S of the memory cells M31-M35 and the drain electrodes D of the transistors L31-L35 constituting the LDMOS region 30, that is, current feed paths.
Here, in this embodiment, as the planar structure of the transistors L31-L35 is shown in
In addition, the operating voltages are applied in common from the operating voltage input terminal Vin to the individual gate electrodes G of the transistors L31-L35, that is, the single gate electrode G3, whereby a channel layer (inversion layer) of channel length ChL is formed at a part directly under the gate electrode G3. However, in spite of such formation of the channel layer for all the transistors L31-L35, in the case where the memory cells M31-M35 are selectively brought into the on-states, actually currents fed from the circuit power source Vc flow through only the transistors which correspond to the selected memory cells. In this way, among the transistors L31-L35, only the transistors in which the currents have actually flowed through their channel layers are selectively activated. That is, also in this case, an effective channel width ChW at the time when the transistors L31-L35 are regarded as a single transistor becomes variable within the LDMOS region 30 in accordance with the number of the activated transistors.
Next, there will be described a method for adjusting the effective channel width ChW at the time when the LDMOS region 30 is regarded as the single transistor, in the semiconductor device configured as stated above. Incidentally, also the adjustment can be executed at will even after the manufacture of the semiconductor device, in the same manner as in the foregoing first and other embodiments.
In making the adjustment, the operating voltages are first applied in common from the operating voltage input terminal Vin to the gate electrodes G (single gate electrode G3) of the transistors L31-L35 (
As described above, in accordance with the semiconductor device according to the third embodiment, advantages to be listed below are obtained.
(1) The operating information which indicates whether or not the currents are to be fed to the transistors L31-L35 constituting the LDMOS region 30 is variably set in the memory cells M31-M35 constituting the nonvolatile memory region 31, and those transistors of the transistors L31-L35 to which the currents are to be fed are selectively fed with the currents on the basis of the operating information. Thus, even after the manufacture of the semiconductor device, the required values of the on-resistance, the switching time, etc. at the time when the transistors L31-L35 are regarded as the single transistor can be adjusted through the aspect of the current feed to the transistors L31-L35. Accordingly, even in the case, for example, where the readjustments of the required values are needed due to the alteration of the load, or the like, the adjustments and alterations of the required values can be coped with at a high degree of freedom.
(2) The LDMOS region 30 and the nonvolatile memory region 31 are formed on the identical semiconductor substrate C3. Thus, reduction in size can be attained as the semiconductor device. Besides, as regards the transistors L31-L35 constituting the LDMOS region 30, and the memory cells M31-M35 constituting the nonvolatile memory region 31, many of semiconductor manufacturing processes are common, and hence, reduction in the manufacturing man-hour of the semiconductor device can be attained.
(3) The gate electrodes G of the transistors L31-L35 are formed as the single gate electrode G3 which corresponds to all the channel regions of the transistors L31-L35. Thus, it is dispensed with to lay metallic wirings or the like which serve to apply the operating voltages in common to the gate electrodes G of the transistors L31-L35, so that the simplification of the structure, as well as the simplification of the manufacture can be attained. Moreover, as compared with the case of laying the metallic wirings or the like, the embodiment sweeps off the apprehension of disconnection, etc., so that the semiconductor device of higher reliability can be realized. Incidentally, this holds true also of the source electrodes S which are electrically connected through the diffusion layer in the transistors L31-L35.
Next, a fourth embodiment of a semiconductor device according to this invention will be described with reference to
Also the semiconductor device of this embodiment has a configuration which basically conforms to the first embodiment shown in
First, as shown in
In the LDMOS region 40 of them, in the same manner as in the foregoing first embodiment, the transistor having the LDMOS structure is arrayed and formed in the semiconductor substrate C4 in a manner to be divided into, for example, five transistors L41-L45 which are electrically connected in parallel with the path of the current. Each of the transistors L41-L45 has a structure conforming to the LDMOS structure exemplified in
Besides, the five memory cells M41-M45 in the same number as that of the transistors L41-L45 are formed in the nonvolatile memory region 41. Also each of the memory cells M41-M45 has a MOS structure basically, and as shown in
Incidentally, the control gate electrodes CG of the memory cells M41-M45 are connected to a voltage control circuit (not shown) in the same manner as in the foregoing first embodiment. In addition, predetermined voltages which correspond to the logic levels of rewritable information items of 5 bits constituting the operating information of the transistors L41-L45 are applied to the respective control gate electrodes CG through the voltage control circuit. Concretely, a voltage at a magnitude which brings the corresponding memory cell into an on-state is applied to the control gate electrode CG of the memory cell which corresponds to the bit that lies at, for example, a logic H (high) level among the bits constituting the operating information. On the other hand, a voltage at a magnitude which brings the corresponding memory cell into an off-state is applied to the control gate electrode CG of the memory cell which corresponds to the bit that lies at, for example, a logic L (low) level among the bits constituting the operating information.
Besides, the five MOS transistors N41-N45 in the same number as that of the transistors L41-L45 are formed in the N-channel MOS region 42. The respective drain electrodes D of the MOS transistors N41-N45 are electrically connected in parallel with that end of the load to-be-operated Ld connected to the circuit power source Vc which is remote from this circuit power source, through a suitable wiring, and the respective source electrodes S of the MOS transistors N41-N45 are connected to the drain electrodes D of the corresponding transistors L41-L45.
Meanwhile, as shown in
In this manner, the memory cells M41-M45 constituting the nonvolatile memory region 41 function as switching elements for performing switching, in a manner to intervene in the application lines of the memory voltages. That is, the switching elements execute the on/off of the application lines of the memory voltages, in turn, the changeover of the activation/inactivation of the MOS transistors N41-N45. In addition, the on/off changeover of the current feed paths to the transistors L41-L45 connected at the succeeding stages is executed through the activation/inactivation manipulations of the MOS transistors N41-N45.
Here, in this embodiment, as the planar structure of the transistors L41-L45 is shown in
In addition, the operating voltages are applied in common from the operating voltage input terminal Vin to the individual gate electrodes G of the transistors L41-L45, that is, the single gate electrode G4, whereby a channel layer (inversion layer) of channel length ChL is formed at a part directly under the gate electrode G4. However, in spite of such formation of the channel layer for all the transistors L41-L45, in the case where the MOS transistors N41-N45 are selectively brought into the on-states, actually currents fed from the circuit power source Vc flow through only the transistors (L41-L45) which correspond to the selected MOS transistors. In this way, among the transistors L41-L45, only the transistors in which the currents have actually flowed through their channel layers are selectively activated. That is, also in this case, an effective channel width ChW at the time when the transistors L41-L45 are regarded as a single transistor becomes variable within the LDMOS region 40 in accordance with the number of the activated transistors.
Next, there will be described a method for adjusting the effective channel width ChW at the time when the LDMOS region 40 is regarded as the single transistor, in the semiconductor device configured as stated above. Incidentally, also the adjustment can be executed at will even after the manufacture of the semiconductor device, in the same manner as in the foregoing first and other embodiments.
In making the adjustment, the operating voltages are first applied in common from the operating voltage input terminal Vin to the gate electrodes G (single gate electrode G4) of the transistors L41-L45 (
As described above, in accordance with the semiconductor device according to the fourth embodiment, advantages to be listed below are obtained.
(1) The operating information which indicates whether or not the currents are to be fed to the transistors L41-L45 constituting the LDMOS region 40 is variably set in the memory cells M41-M45 constituting the nonvolatile memory region 41. In addition, those transistors of the transistors L41-L45 to which the currents are to be fed are selectively fed with the currents on the basis of the operating information, through the operations of the MOS transistors N41-N45 which are connected in a manner to intervene in the current feed paths to these transistors L41-L45. Thus, even after the manufacture of the semiconductor device, the required values of the on-resistance, the switching time, etc. at the time when the transistors L41-L45 are regarded as the single transistor can be adjusted through the aspect of the current feed to the transistors L41-L45. Accordingly, even in the case, for example, where the readjustments of the required values are needed due to the alteration of the load, or the like, the adjustments and alterations of the required values can be coped with at a high degree of freedom. Moreover, in this case, owing to the intervention of the MOS transistors N41-N45, the gate resistors of the transistors L41-L45 and the on-resistances of the memory cells M41-M45 constructing the switching elements can be independently set unlike in the foregoing third embodiment.
(2) The LDMOS region 40 and the nonvolatile memory region 41 are formed on the identical semiconductor substrate C4. Thus, reduction in size can be attained as the semiconductor device. Besides, as regards the transistors L41-L45 constituting the LDMOS region 40, the memory cells M41-M45 constituting the nonvolatile memory region 41, and the MOS transistors N41-N45 constituting the N-channel MOS region 42, many of semiconductor manufacturing processes are common, and hence, reduction in the manufacturing man-hour of the semiconductor device can be attained.
Next, a fifth embodiment of a semiconductor device according to this invention will be described with reference to
The semiconductor device of this embodiment has a configuration which basically conforms to the third embodiment shown in
In this embodiment, an electrically rewritable EPROM is adopted as the nonvolatile memory, and as shown in
Here, the transistor 32 having the built-in memory corresponds to the memory cell and the transistor in one set as are connected with each other by a suitable wiring, among the memory cells M31-M35 and the transistors L31-L35 shown in
Operating information which indicates whether or not current is to be fed to the transistor is set for such a transistor 32 having the built-in memory, through the operation of the voltage control circuit. More specifically, a voltage at a predetermined magnitude higher than the ground (GND) as corresponds to a bit which lies at a logic H (high) level (at which the current is to be fed), among individual bits constituting the operating information, is applied to the control gate electrode 323 of the transistor 32 having the built-in memory, by the voltage control circuit. Thus, electrons existing within the floating gate electrode 322 are extracted onto the side of the control gate electrode 323 through the tunnel film 324, and the transistor 32 having the built-in memory is brought into an on-state. On the other hand, a voltage at a predetermined magnitude lower than the ground (GND) as corresponds to a bit which lies at a logic (L) low level (at which the current is not to be fed), among the individual bits constituting the operating information, is applied to the control gate electrode 323 of the transistor 32 having the built-in memory, by the voltage control circuit. Thus, electrons are injected from the control gate electrode 323 onto the side of the floating gate electrode 322 through the tunnel film 324, and the transistor 32 having the built-in memory is brought into an off-state. In this manner, the transistor 32 having the built-in memory functions as a switching element whose on/off-states are respectively changed-over in accordance with the logic levels of the bits constituting the operating information.
Next, there will be described a method for adjusting an effective channel width at the time when the LDMOS region is regarded as a single transistor, in the semiconductor device configured as stated above. Incidentally, it is as stated before that the adjustment can be executed at will even after the manufacture of the semiconductor device.
In making the adjustment, predetermined operating voltages are first applied from the operating voltage input terminal Vin to the gate electrodes 321 of the transistors, whereby channel layers (inversion layers) are formed at the parts of channel regions 102 directly under the gate electrodes 321. The channel layers thus formed lie in touch with source regions 104 and are therefore electrically connected, whereas they do not lie in touch with a drain region 101 and are not electrically connected.
Meanwhile, the voltage control circuit is operated, whereby the on/off of the respective bits of the operating information are set on the basis of the exchanges of the electrons through the tunnel films 324 between the control gate electrodes 323 and the floating gate electrodes 322 as correspond to potentials applied to the control gate electrodes 323. On this occasion, when the transistors 32 having the built-in memories are brought into the on-states, channel layers (inversion layers) are formed at the parts of the channel regions 102 directly under the floating gate electrodes 322. The channel layers thus formed lie in touch with the drain region 101 and the foregoing channel layers formed at the parts directly under the gate electrodes 321, and they are therefore electrically connected.
In this way, when predetermined voltages are respectively applied selectively to the control gate electrodes 323 of the transistors 32 having the built-in memories and in common to the gate electrodes 321 of the transistors, current fed from a circuit power source Vc flows only between the drain region 101 and source regions 104 of the transistors 32 having the built-in memories, under the on-states, and it leads to the ground (GND). In this way, the effective channel width at the time when the transistors are regarded as the single transistor is made variable within the semiconductor substrate in accordance with the number of the transistors which are selectively activated on the basis of the operating information of the transistors set in the nonvolatile memory region.
Advantages equivalent to those of the third embodiment are attained also by the semiconductor device according to the fifth embodiment described above.
Incidentally, the fifth embodiment can also be performed through an appropriate alteration in, for example, an aspect stated below.
In the fifth embodiment, the channel layer has been formed at the part of the channel region 102 directly under the floating gate electrode 322, on the basis of the exchanges of the electrons through the tunnel film 324 between the control gate electrode 323 and the floating gate electrode 322, but a channel for forming the channel layer is not restricted to this aspect. As shown in
Next, a sixth embodiment of a semiconductor device according to this invention will be described with reference to
The semiconductor device of this embodiment has a configuration which basically conforms to the fourth embodiment shown in
As shown in
Here, the transistor 43 corresponds to the MOS transistor and the transistor in one set as are connected with each other by a suitable wiring, among the MOS transistors N41-N45 and the transistors L41-L45 shown in
Next, there will be described a method for adjusting an effective channel width at the time when the LDMOS region is regarded as a single transistor, in the semiconductor device configured in this manner. Incidentally, the adjustment can be executed at will even after the manufacture of the semiconductor device.
In making the adjustment, predetermined operating voltages are first applied from the operating voltage input terminal Vin to the gate electrodes 431 of the transistors 43, whereby channel layers (inversion layers) are formed at the parts of channel regions 102 directly under the gate electrodes 431. Incidentally, the channel layers thus formed lie in touch with source regions 104 and are electrically connected, whereas they do not lie in touch with a drain region 101 and are not electrically connected. However, in the case where the memory cells M41-M45 constituting the nonvolatile memory region 41 (
In this way, when predetermined voltages are respectively applied selectively to the memory cells constituting the nonvolatile memory region 41 and in common to the gate electrodes 431 of the transistors, current fed from a circuit power source Vc flows only between the drain region 101 and source regions 104 of the transistors 43 under the on-states, and it leads to the ground (GND). In this way, the effective channel width at the time when the transistors are regarded as the single transistor is made variable within the semiconductor substrate in accordance with the number of the transistors which are selectively activated on the basis of the operating information of the transistors variably set in the nonvolatile memory region.
Advantages equivalent to those of the fourth embodiment are attained also by the semiconductor device according to the sixth embodiment described above.
Moreover, in the semiconductor device according to the sixth embodiment, after the formation of each second gate electrodes 433, the corresponding first gate electrodes 431 has been formed so as to partly overlap the second gate electrodes 433, so that increases in the threshold voltage and on-resistance of the transistor 43 can be suppressed.
More specifically, in this embodiment, voltages different from each other need to be fed to the first gate electrode 431 and the second gate electrode 433 which are formed in adjacency. Therefore, both the gate electrodes 431 and 433 need to be held in an open state electrically therebetween. As a method for separating the gate electrodes 431 and 433, there is considered, for example, a method in which the gate electrode 107 shown in
In this regard, according to this embodiment, the first gate electrode 431 is formed so as to partly overlap the second gate electrode 433, so that the interval between the first gate electrode 431 and the second gate electrode 433 becomes the thickness of the insulating film ILD and becomes narrower than the interval of the gate electrodes formed by the above method. Therefore, even when the voltages which are applied to the respective gate electrodes 431 and 433 are low, the channel layers which are formed by both the gate electrodes 431 and 433 are connected, and hence, the increases in the threshold voltage and the on-resistance can be suppressed.
Incidentally, the sixth embodiment can also be performed through an appropriate alteration in, for example, an aspect stated below.
In the sixth embodiment, each first gate electrode 431 has been formed so as to partly overlap the corresponding second gate electrode 433. As shown in
In the sixth embodiment, the first gate electrode 431 and the second gate electrode 433 have been formed so as to partly overlap one over the other. As shown in
Further, in addition to the configuration of
The impurity concentration of the diffusion layer 434 is made the same as the concentration (N+) of the source region 104 by way of example. With such a configuration, even when the first gate electrode 431b and the second gate electrode 433b are not formed at the sufficiently short distance, channel layers which are respectively formed by the first and second gate electrodes 431b and 433b are connected by the diffusion layer 434, so that each transistor 43c can be turned on by low gate voltages, and increases in the threshold voltage and on-resistance of the transistor can be suppressed.
In each of the sixth embodiment and the modifications, the first gate electrode 431 or the like has been connected to the operating voltage input terminal Vin, and the second gate electrode 433 or the like has been connected to the memory region 41. It is also allowed, however, that the first gate electrode 431 or the like is connected to the memory region 41, and that the second gate electrode 433 or the like is connected to the operating voltage input terminal Vin. Besides, they may well be connected to the power source circuit (voltage control circuit) which is formed on the substrate formed with these transistors, in the same manner as in the fifth embodiment. It is to be understood that advantages equivalent to those of the sixth embodiment are attained even with these configurations.
Next, a seventh embodiment of a semiconductor device according to this invention will be described with reference to
As shown in
In addition, a channel region 102a is formed in such a manner that the length thereof in the direction of the path of current, between the source region 104 and a drain region 101 (a drain contact portion 105) is shorter than in the sixth embodiment. Besides, the gate electrode 451 is formed so as to cover a region which extends from the source region 104 to the drain region 101, and the control electrode 452 is formed so as to cover the upper part of the drain region 101.
Next, the operation of the transistor 45 thus configured will be described.
The gate electrode 451 covering the channel region 102a forms a channel layer (inversion layer) in the channel region 102a, on the basis of a predetermined operating voltage applied from the operating voltage input terminal Vin. Incidentally, the channel layer thus formed connects the source region 104 and the drain region 101 electrically. Accordingly, the gate electrode 451 which is formed so as to cover the channel region 102a constitutes a MOS transistor of N-type, together with the source region 104 and the drain region 101. The MOS transistor is turned on/off by the predetermined operating voltage which is applied from the operating voltage input terminal Vin to the gate electrode 451.
The control electrode 452 which covers the upper part of the drain region 101 opposes to this drain region through an insulating film ILD, and functions as a capacitor. Therefore, when a plus voltage is applied to the control electrode 452, a charge accumulation layer in which electrons are accumulated is formed in the drain region 101 opposing to the control electrode 452.
The drain region 101 is usually set at a low impurity concentration in order to ensure a withstand voltage, and it has a high resistance, so that the current chiefly flows through the charge accumulation layer. The quantity of the electrons which are accumulated in the charge accumulation layer corresponds to the voltage applied to the control electrode 452, and further, the current which corresponds to the quantity of the accumulated electrons flows. Therefore, the easiness of the flow of the current, namely, a resistance value can be controlled by the voltage which is applied to the control electrode 452. In addition, the resistance value of the charge accumulation layer acts at the time of the turn-on of the MOS transistor which is controlled by the gate electrode 451. That is, the transistor 45 functions as the MOS transistor, and a variable resistor connected in series with this transistor, as shown in
Incidentally, a potential applied to the source region 104 (the ground (GND) potential in
As described above, in accordance with the semiconductor device according to the seventh embodiment, advantages to be listed below are obtained.
(1) In the transistor 45, the gate electrode which is formed so as to extend from the source region 104 to the field oxide film 106 has been divided into the gate electrode 451 which covers the region extending from the source region 104 to the drain region 101, and the control electrode 452 which covers the upper part of the drain region 101. This transistor becomes equivalent to the structure in which the MOS transistor and the variable resistor are connected in series. Accordingly, the predetermined operating voltage applied from the operating voltage input terminal Vin is applied to the gate electrode 451, and the predetermined voltage is applied to the control electrode 452, whereby the on-resistance value between the source region 104 and the drain contact portion 105 can be precisely controlled.
(2) Since the control electrode 452 is not directly pertinent to the on/off operations of the transistor 45, this transistor 45 is turned-on/off substantially by the voltage applied to the gate electrode 451. In addition, since the opposing area between the first gate electrode 451 and the drain region becomes smaller than in the transistor of the prior-art example, and hence, a parasitic capacitance can be made smaller.
(3) The gate electrode 451 has been formed so as to partly overlap the control electrode 452. In the same manner as in the sixth embodiment, accordingly, increase in the on-resistance of the transistor 45 can be suppressed. More specifically, the gate electrode 451 and the control electrode 452 need to be electrically separated (brought into an open state). Therefore, when the gate electrode 451 and the control electrode 452 are excessively spaced, a part of high resistance is formed between the channel layer formed by the gate electrode 451 and the charge accumulation layer formed by the control electrode 452, and the on-resistance value which is controlled by the control electrode 452 becomes difficult of contributing to the operation of the transistor 45, so that the increase of the on-resistance is incurred.
In this regard, according to this embodiment, the gate electrode 451 is formed so as to partly overlap the control electrode 452, so that the interval between the gate electrode 451 and the control electrode 452 becomes the thickness of the insulating film ILD and becomes narrower than the interval of the electrodes formed by etching or the like expedient. Therefore, the part of the high resistance is not formed, or it becomes small, so that the increase of the on-resistance can be suppressed.
Incidentally, the seventh embodiment can also be performed through an appropriate alteration in, for example, an aspect stated below.
In the seventh embodiment, the gate electrode 451 has been formed so as to partly overlap the control electrode 452. As shown in
In the seventh embodiment, the gate electrode 451 and the control electrode 452 have been formed so as to partly overlap one over the other. As shown in
Further, in addition to the configuration of
Incidentally, the foregoing embodiments can also be performed through appropriate alterations in, for example, aspects stated below.
In each of the third to seventh embodiments, the drain electrodes D of the transistors L31-L35 or L41-L45 have been formed in a manner to be electrically separated, and the source electrodes S of the transistors L31-L35 or L41-L45 have been formed in a manner to be electrically connected through the diffusion layer S (N) formed within the semiconductor substrate C3 or C4. To the contrary, it is also allowed that the source electrodes S of the transistors L31-L35 or L41-L45 are formed in a manner to be electrically separated, and that the drain electrodes D of the transistors L31-L35 or L41-L45 are formed in a manner to be electrically connected through the diffusion layer Dc (N+) formed within the semiconductor substrate C3 or C4. In short, the advantage (3) of the foregoing third embodiment can be attained if the individual gate electrodes G are formed as the single electrode, whereupon either electrodes of the drain electrodes D and the source electrodes S are formed in the manner to be electrically separated, and the other electrodes are formed in the manner to be electrically connected through the diffusion layer formed within the semiconductor substrate.
Besides, it is also allowed that such transistors Ln1-Ln5 are respectively isolated in an array manner as shown in
In each of the third to seventh embodiments, the nonvolatile memory region 31 has been formed in the semiconductor substrate C3 formed with the LDMOS region 30, or the nonvolatile memory region 41 has been formed in the semiconductor substrate C4 formed with the LDMOS region 40 and the N-channel MOS region 42, but this configuration is not restrictive. The memory cells M31-M35 constituting the nonvolatile memory region 31 may well be formed on a separate semiconductor substrate, and be respectively connected to the transistors L31-L35 constituting the LDMOS region 30 formed in the semiconductor substrate C3, by metallic wirings by way of example. Alternatively, the memory cells M41-M45 constituting the nonvolatile memory region 41, and the MOS transistors N41-N45 constituting the N-channel MOS region 42 may well be formed on a separate semiconductor substrate, and be respectively connected to the transistors L41-L45 constituting the LDMOS region 40 formed in the semiconductor substrate C4, by metallic wirings by way of example. In short, a concrete aspect for realization is as desired with any structure in which the equivalent circuit shown in
Besides, the first to seventh embodiments can also be performed through appropriate alterations in, for example, aspects stated below.
In each of the embodiments, the transistor having the LDMOS structure, the drain electrode D and the source electrode S of which are connected so as to intervene in the current path of the load to-be-operated Ld, has been adopted as the transistors which are arrayed and formed on the semiconductor substrate in a manner to be divided into the plurality of transistors connected in parallel, but this configuration is not restrictive. Otherwise, as shown in
Further, the application scope of the present invention is not restricted to the transistors having the LDMOS structure and the VDMOS structure. Otherwise, by way of example, as shown in
Although the transistors in each of the foregoing embodiments have been the MOS transistors of N-type, they may well be constructed of MOS transistors of P-type. It is also allowed to employ a semiconductor device of so-called “CMOS structure” in which conductive types are appropriately altered, that is, MOS transistors of N-type and MOS transistors of P-type are formed on an identical semiconductor substrate.
The transistors in each of the fifth to seventh embodiments and modifications are formed on an identical semiconductor substrate, together with other elements. In a case, for example, where the transistor 45 in the seventh embodiment is applied to the transistors L21-L25 (refer to
As shown in
As shown in
Besides, a capacitor is formed on the identical semiconductor substrate as the other element. The capacitor is included in a voltage control circuit which feeds predetermined voltages to, for example, a second gate electrode. As shown in
In this manner, the other element formed on the same semiconductor substrate as that of the transistors in each of the fifth to seventh embodiments is formed by an identical process (for example, the second gate electrode 433 shown in
In each of the foregoing embodiments, at least one of the plurality of transistors constituting any of the LDMOS regions 10-40 may well be replaced with the transistor shown in each of the fifth to seventh embodiments and modifications. Owing to this configuration, the plurality of transistors constituting each of the LDMOS regions 10-40 are subjected to a control for the floating gate or divided gate electrodes, or the control electrode, in addition to the control based on the memory region and the N-channel MOS region, whereby the transistors can be controlled more precisely.
In each of the fifth to seventh embodiments and modifications, a metallic wiring may well be arranged in superposition on the gate electrode or the control electrode. Since the gate electrode is made of, for example, polycrystal silicon, it is larger in the value of a parasitic resistance than the metallic wiring (aluminum, copper or the like). As in the third or fourth embodiment, the plurality of transistors L31-L35 or L41-L45 constituting the LDMOS region 30 or 40 have been electrically connected in parallel, and the gates of the individual transistors L31-L35 or L41-L45 have been connected to the operating voltage input terminal Vin in common. Since such gate electrodes are formed as the single common gate electrode G3 or G4 as shown in
Still further, the application scope of the present invention is not restricted to transistors each having a built-in memory or transistors each having an LDMOS structure, VDMOS structure or IGBT structure. In short, it is allowed to employ any structure in which transistors each having a MOS structure that includes first and second electrodes connected so as to intervene in the path of current, and gate electrodes for controlling currents to flow between the first and second electrodes, in accordance with applied voltages, are arrayed on a semiconductor substrate in a manner to be divided into a plurality of transistors that are electrically connected in parallel with the path of the current. With such a structure, an effective channel width at the time when the plurality of divided transistors are regarded as a single transistor can be made variable within the semiconductor substrate, in accordance with the number of the transistors selectively activated on the basis of the operating information of the plurality of transistors variably set in a nonvolatile memory, and the intended object can be accomplished.
While the invention has been described with reference to preferred embodiments thereof, it is to be understood that the invention is not limited to the preferred embodiments and constructions. The invention is intended to cover various modification and equivalent arrangements. In addition, while the various combinations and configurations, which are preferred, other combinations and configurations, including more, less or only a single element, are also with in the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-23324 | Feb 2007 | JP | national |
