Patent Application
20240222205
This US application claims the benefit of priority under 35 USC § 119 to Korean Patent Application No. 10-2022-0186658, field on Dec. 28, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
Various example embodiments generally relate to semiconductor integrated circuits, and more particularly to a semiconductor device including a detection structure and/or a method of detecting a progressive crack in a semiconductor device, and/or a method of downgrading semiconductor devices which may lead to an improved yield and/or reliability.
In general, integrated circuits are manufactured by forming repeated patterns on a wafer of semiconductor material. Progressive cracks due to seams on a profile according to etching process during forming patters may not be detected. It is required or desired to prevent or reduce the likelihood of the shipment of defective products by more accurately detecting such progressive cracks.
Some example embodiments may provide a semiconductor device including a crack detection structure capable of detecting progressive cracks by accelerating progress of cracks.
Alternatively or additionally, some example embodiments may provide a method of detecting a progressive crack in a semiconductor device.
According to various example embodiments, a semiconductor device includes a semiconductor die, a chip guard ring, a first crack detection structure, a second crack detection structure, and a detection controller. The semiconductor die includes a central region in which a semiconductor integrated circuit is arranged and an external region surrounding the central region. The chip guard ring is arranged inside the semiconductor die along an edge of the semiconductor die and separates the central region and the external region. The first crack detection structure is arranged along an edge of the central region as a closed curve. The second crack detection structure is arranged along the edge of the central region as a closed curve, and is spaced apart from the chip guard ring farther than the first crack detection structure. In a first phase, the detection controller is configured to induce an electrical short circuit between the first crack detection structure and the second crack detection structure by applying a first power to the first crack detection structure and by applying a second power greater than the first power to the second crack detection structure. In a second phase, the detection controller is configured to apply a test input signal to the first crack detection structure, and to determine whether a progressive crack occurs in the central region based on whether a test output signal responding to the test input signal is detected in the second crack detection structure in the second phase.
Alternatively or additionally according to some example embodiments, there is provided a method of detecting a progressive crack in a semiconductor device which includes a semiconductor die including a central region in which a semiconductor integrated circuit is arranged and an external region surrounding the central region and a chip guard ring arrange inside the semiconductor die along an edge of the semiconductor die so as to separate the central region and the external region. According to the method, a first power and a second power greater than the first power are applied to a first crack detection structure and a second crack detection structure, respectively, during a first time interval in a first phase, where the first crack detection structure is arranged along an edge of the central region as a closed curve, the second crack detection structure is arranged along the edge of the central region as a closed curve and the second crack detection structure is spaced apart from the chip guard ring farther than the first crack detection structure, a test input signal is applied to the first crack detection structure during a second time interval in a second phase, and a progressive crack may be determined to occur in the central region based on whether a test output signal responding to the test input signal is detected in the second crack detection structure in the second phase.
Alternatively or additionally according to some example embodiments, a semiconductor device includes a semiconductor die, a chip guard ring, a crack detection structure and a detection controller. The semiconductor die includes a central region in which a semiconductor integrated circuit is arranged and an external region surrounding the central region. The chip guard ring is arranged inside the semiconductor die along an edge of the semiconductor die and separates the central region and the external region. The crack detection structure is arranged along an edge of the central region as a closed curve. The detection controller is configured to induce an electrical short circuit between the crack detection structure and the chip guard ring by applying a power to the crack detection structure during a first time interval in a first phase, to apply a test input signal to the crack detection structure in a second phase, and to determine whether a progressive crack occurs in the central region based on whether a test output signal responding to the test input signal is detected in the crack detection structure in the second phase.
Therefore, the semiconductor device according to various example embodiments may accelerate a progress of a crack occurring around the first crack detection structure by applying a first power and a second power having a voltage level difference to the first crack detection structure and the second crack detection structure, respectively, in the first phase, may apply a pulse signal and/or a DC voltage to the first crack detection structure in a second phase, and may determine whether a progressive crack occurs in the central region based on whether the pulse signal or the DC voltage is detected in the second crack detection structure, in the second phase. Therefore, the semiconductor device according to various example embodiments may be screened and may be removed from further processing or downgraded when having potential defects, and thus yield and/or reliability of the semiconductor device may be enhanced.
Various example embodiments will be described below in more detail with reference to the accompanying drawings.
Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. In the drawings, like numerals refer to like elements throughout. The repeated descriptions may be omitted.
Referring to
Various semiconductor integrated circuits may be formed or arranged in the central region CTREG, depending on a kind and/or type of the semiconductor device 1000. For example, the semiconductor device 1000 may be or may include or be included in a nonvolatile memory device, and a memory integrated circuit may be formed in the central region CTREG of the semiconductor die.
The external region EREG may be a region in which no element is formed or a region in which only dummy elements, e.g. elements that are not electrically active or operational, are formed. The external region EREG may be a place having a space margin, for example in case of a damaged part when dicing the wafer so as to singulate the semiconductor device 1000.
Even if a crack, e.g., a cracking phenomenon of the semiconductor device 1000 occurs in the external region EREG, there may not be a problem in the direct operation of the semiconductor device 1000. However, when cracks occur in the central region CTREG of the semiconductor device 1000 or cracks proceed from the external region EREG to the central region CTREG, the reliability of the operation of the semiconductor device 1000 may be greatly impaired.
The chip guard ring GR may be formed inside the semiconductor die along an edge of the semiconductor die so as to separate the central region CTREG and the external region EREG. The chip guard ring GR may be located between the central region CTREG and the external region EREG. The chip guard ring GR may serve to block or at least partly block or inhibit progress of the above-described cracks from the external region EREG to the central region CTREG.
Alternatively or additionally, the chip guard ring GR may perform a moisture absorption action which prevents or reduces an amount of external moisture from entering the inside of the semiconductor device 1000. For example, when moisture enters the central region CTREG of the semiconductor device 1000, the elements located in the central region CTREG of the semiconductor device 1000 may be damaged and/or malfunction. The chip guard ring GR may prevent or reduce the likelihood of such problems.
The chip guard ring GR may be formed while making a closed curve along the edge of the semiconductor die. Here, a “closed curve” refer to ring shapes that are in contact with one another, but does not necessarily indicate that the extended portion of the chip guard ring GR necessarily has curvature. For example, the horizontal arrangement shape of the chip guard ring GR be a polygon such as a rectangle or square, rather than a circle or an ellipse. In some example embodiments, a polygon as opposed to a circle or an ellipse, such as a polygonal guard ring GR and/or a polygonal first crack detection structure CDS1 and/or a polygonal second crack detection structure CDS2 may be easier to fabricate, but examples are not limited thereto.
The first crack detection structure CDS1 may be arranged along an edge of the central region CTREG in a form of a closed curve. The second crack detection structure CDS2 may be formed along the edge of the central region in a form of a closed curve, and the second crack detection structure CDS2 may be spaced apart from the chip guard ring GR farther than the first crack detection structure CDS1.
The semiconductor device 1000 may further include pads PD1 and PD2 and a detection controller DCON 890. The pads PD1 and PD2 are not necessarily arranged as in
The detection controller 890 may induce an electrical short circuit between the first crack detection structure CDS1 and the second crack detection structure CDS2 by applying a first power (e.g. a first voltage and/or a first current) to the first crack detection structure CDS1 and by applying a second power (e.g. a second voltage and/or a second current) having a level higher than a level of the first power to the second crack detection structure CDS2, in a first phase, may apply a test input signal (e.g. a test input voltage) to the first crack detection structure CDS1 in a second phase, and may determine whether a progressive crack occurs in the central region CTREG based on whether a test output signal responding to the test input signal is detected in the second crack detection structure CDS2. When the electrical short circuit is induced between the first crack detection structure CDS1 and the second crack detection structure CDS2, a progression of a crack occurring around the chip guard ring GR may be accelerated and the crack may proceed to the second crack detection structure CDS2. In some example embodiments, the detection controller 890 may induce an electrical short circuit after fabrication or after dicing of the semiconductor device; however, example embodiments are not necessarily limited thereto.
The pads PD1 and PD2 may be selectively used when applying the first power to the first crack detection structure CDS1, applying the second power to the second crack detection structure CDS2, and applying the test input signal to the first crack detection structure CDS1.
Each of the chip guard ring GR, the first crack detection structure CDS1, and the second crack detection structure CDS2 may include a first conduction segment passing through a left-bottom corner region CLB of the external region EREG, a second conduction segment passing through a left-upper corner region CLU of the external region EREG, a third conduction segment passing through a right-upper corner region CRU of the external region EREG, and a fourth conduction segment passing through a right-bottom corner region CRB of the external region EREG.
Each of the chip guard ring GR, the first crack detection structure CDS1 and the second crack detection structure CDS2 may be formed or arranged in a first direction, a second direction and a third direction.
Hereinafter, various example embodiments are described using an orthogonal set of an X direction, a Y direction and a Z direction for convenience of illustration and description. The X direction, the Y direction, and the Z direction refer to three perpendicular directions along the three directions, and are not limited to particular directions. The X direction corresponds to a first direction (e.g., a row direction), the Y direction corresponds to a second direction (e.g., a column direction) and the Z direction corresponds to a third direction or a vertical direction.
Referring to
The first crack detection structure CDS1 may be spaced apart from the chip guard ring GR by a first gap d1 in the first direction X and the second crack detection structure CDS2 may be may be spaced apart from the first crack detection structure CDS1 by a second gap d2 in the first direction X. Therefore, the second crack detection structure CDS2 may be may be spaced apart from the chip guard ring GR by a gap of greater than or equal to d1+d2 in the first direction X, and the second crack detection structure CDS2 may be may be spaced apart from the chip guard ring GR farther than the first crack detection structure CDS1.
Referring to
Although five horizontal lines are illustrated in
Because the first crack detection structure CDS1 and the second crack detection structure CDS2 have structures as illustrated in
When the first crack detection structure CDS1 is connected to at least a portion of the second crack detection structure CDS2, a test output signal responding to a test input signal that is applied to the first crack detection structure CDS1 may be detected in the second crack detection structure CDS2.
In
A first power PWR1 and a second power PWR2 having a level such as a voltage level higher than a voltage level of the first power PWR1 may be applied to the first crack detection structure CDS1 and the second crack detection structure CDS2, respectively. The second power PWR2 may have a voltage level with a value or an absolute value large enough for generating an electric field from the second crack detection structure CDS2 to the first crack detection structure CDS1, with respect to the voltage level of the first power PWR1. For example, a voltage difference between the second power PWR2 and the first power PWR1 may be one volt or two volts, or a value between one volt and two volts, however, example embodiments are not limited thereto.
When the first power PWR1 and the second power PWR2 are applied to the first crack detection structure CDS1 and the second crack detection structure CDS2, respectively, an electric field may be generated from the second crack detection structure CDS2 to the first crack detection structure CDS1. When the electric field is generated, electrons may move from the first crack detection structure CDS1 to the second crack detection structure CDS2 along a reverse direction of the electric field, an electrical short circuit is induced between the first crack detection structure CDS1 and the second crack detection structure CDS2 due to a crack or a delamination occurring around the first crack detection structure CDS1, and the first crack detection structure CDS1 is connected to or shorted to at least a portion of the second crack detection structure CDS2.
Referring to
Referring to
Referring to
When the first power supply voltage VPP1 and the second power supply voltage VPP2 are applied to the first crack detection structure CDS1 and the second crack detection structure CDS2, respectively, an electric field is generated from the second crack detection structure CDS2 to the first crack detection structure CDS1. When the electric field is generated, electrons may move from the first crack detection structure CDS1 to the second crack detection structure CDS2 along a reverse direction of the electric field. When the electrons move from the first crack detection structure CDS1 to the second crack detection structure CDS2, an electrical short circuit may be induced between the first crack detection structure CDS1 and the second crack detection structure CDS2 due to acceleration of a progression of a crack that occurs around the first crack detection structure CDS1 but does not proceed to the first crack detection structure CDS1 and/or to a delamination occurring around the first crack detection structure CDS1, and thus, the first crack detection structure CDS1 is connected to or shorted to at least a portion of the second crack detection structure CDS2. In addition, a progression of a crack occurring in the chip guard ring GR may be accelerated due to the electric field.
Referring to
When the ground voltage VSS and the power supply voltage VPP are applied to the first crack detection structure CDS1 and the second crack detection structure CDS2, respectively, an electric field is generated from the second crack detection structure CDS2 to the first crack detection structure CDS1. When the electric field is generated, electrons may move from the first crack detection structure CDS1 to the second crack detection structure CDS2 along a reverse direction of the electric field. When the electrons move from the first crack detection structure CDS1 to the second crack detection structure CDS2, an electrical short circuit is induced between the first crack detection structure CDS1 and the second crack detection structure CDS2 due to due to acceleration of a progression of a crack that occurs around the first crack detection structure CDS1 but does not proceed to the first crack detection structure CDS1 and/or a delamination occurring around the first crack detection structure CDS1, and thus, the first crack detection structure CDS1 is connected to or shorted to at least a portion of the second crack detection structure CDS2. In addition, a progression of a crack occurring in the chip guard ring GR may be accelerated due to the electric field.
Referring to
As described with reference to
If a crack does not occur in the chip guard ring GR, a progress of the crack may not be accelerated even when the first power PWR1 and the second power PWR2 are applied to the first crack detection structure CDS1 and the second crack detection structure CDS2, respectively, and the detection controller 890 cannot or is not likely to receive the output signal TSO responding to the test input signal TSI from a second pad PD2 in the second phase. In this case, the detection controller 890 may determine that a crack does not occur in the central region CTREG.
Referring to
When the test output signal TSO responds to the test input signal TSI as denoted by a solid line, the detection controller 890 determines that a crack occurs in the central region CTREG.
When the test output signal TSO does not respond to the test input signal TSI as denoted by a dotted line, the detection controller 890 determines that a crack does not occur in the central region CTREG.
The test input signal TSI may be pulse signal and/or a direct current (DC) voltage.
Referring to
The first crack detection structure CDS1a may include a plurality of top horizontal line segments HLT formed in the first conduction layer and extending in the first direction X and the second direction Y, a plurality of bottom horizontal line segments HLB formed in the second conduction layer and extending in the first direction X and the second direction Y, a plurality of bottom horizontal line segments HLB formed in the second conduction layer and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB respectively in the third direction Z. The top horizontal line segments HLT, the bottom horizontal line segments HLB and the vertical line segments VL may be disposed alternatingly along the first crack detection structure CDS1a to surround the central region CTREG of the semiconductor die.
Referring to
The second crack detection structure CDS2a may include a first horizontal conduction loop HLOOP1 formed in the first conduction layer and a second horizontal conduction loop HLOOP2 formed in the second conduction layer. The first horizontal conduction loop HLOOP1 may correspond to the plurality of top horizontal line segments HLT in
Referring to
A first crack detection structure CDS1b may include a plurality of top horizontal line segments HLT formed in the first conduction layer ML1, a plurality of bottom horizontal line segments HLB formed in the second conduction layer PL2 and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB respectively.
In various example embodiments such as illustrated in
The vertical line segments VL may include vertical contacts VC1, VC2 and VC3 to provide an electrical connection between the metal line patterns MP1 in the uppermost metal layer ML1 and the polysilicon line patterns PP in the bit-line polysilicon layer PL2. The vertical line segments VL may further include conduction line patterns MP2 and MP3 in the respective intermediate conduction layers ML2 and ML3. In some example embodiments, the conduction line pattern in one or both of the intermediate conduction layers ML2 and ML3 may be omitted. For example, the metal line patterns MP2 in the intermediate metal layer ML2 may be omitted, and the two vertical contacts VC1 and VC2 may be combined as a longer vertical contact.
Hereinafter, the descriptions repeated with
Referring to
In various example embodiments for example as illustrated in
Referring to
The horizontal conduction loop HLOOP11 may include metal line patterns MP1 formed in the first conduction layer ML1, the horizontal conduction loop HLOOP12 may include metal line patterns MP2 formed in the second conduction layer ML2, the horizontal conduction loop HLOOP13 may include metal line patterns MP4 formed in the third conduction layer ML3 and the horizontal conduction loop HLOOP14 may include polysilicon line patterns PP formed in the bit-line polysilicon layer PL2. The second crack detection structure CDS2b may correspond to the first crack detection structure CDS1b of
Referring to
The horizontal conduction loop HLOOP11 may include metal line patterns MP1 formed in the first conduction layer ML1, the horizontal conduction loop HLOOP12 may include metal line patterns MP2 formed in the second conduction layer ML2, the horizontal conduction loop HLOOP13 may include metal line patterns MP4 formed in the third conduction layer ML3, the horizontal conduction loop HLOOP14 may include polysilicon line patterns PP2 formed in the bit-line polysilicon layer PL2 and the horizontal conduction loop HLOOP15 may include polysilicon line patterns PP1 formed in the bit-line polysilicon layer PL1. The second crack detection structure CDS2c may correspond to the second crack detection structure CDS1c of
Referring to
Referring to
Referring to
Referring to
The first switch circuit 850 may in response to a first switching control signal SCS1 provide the first power PWR1 to the first crack detection structure CDS1 during the first time interval in the first phase, and may provide the test input signal TSI to the first crack detection structure CDS1 during the second time interval in the second phase.
The second switch circuit 860, may in response to a second switching control signal SCS2 and a third switching control signal SCS3 provide the second power PWR2 to the second crack detection structure CDS2 during the first time interval in the first phase, and may connect the second crack detection structure CDS2 to the detection controller 890 during the second time interval in the second phase and thus, may provide the detection controller 890 with the test output signal TSO responding to the test input signal TSI.
The detection controller 890 may apply the first switching control signal SCS1 to the first switch circuit 850, may apply the second switching control signal SCS2 and the third switching control signal SCS3 to the second switch circuit 860, and may apply the test input signal TSI to the first switch circuit 850 during the second time interval in the second phase.
In
Referring to
The second switch circuit 860 may include a first sub switch 870 and a second sub switch group 880 and the second sub switch group 880 may include a plurality of second sub switches 881, 882, 883, 884 and 885.
The first sub switch 870 may be connected between the detection controller 890 and a first node N11. The plurality of second sub switches 881, 882, 883, 884 and 885 may be commonly connected to the first node N11 and may be connected to the plurality of horizontal conduction loops HLOOP11, HLOOP12, HLOOP13, HLOOP14 and HLOOP15, respectively.
The first sub switch 870, in response to the second switching control signal SCS2, may provide the second power PWR2 to the first node N11 in the first phase and may connect the first node N11 to the detection controller 890 in the second phase.
The plurality of second sub switches 881, 882, 883, 884, and 885 may in response to the third switching control signal SCS3 provide the plurality of horizontal conduction loops HLOOP11, HLOOP12, HLOOP13, HLOOP14 and HLOOP15 with the second power PWR2 provided to the first node N11 in the first phase and may connect at least a portion of the plurality of horizontal conduction loops to HLOOP11, HLOOP12, HLOOP13, HLOOP14 and HLOOP15 to the detection controller 890 through the first node N11 and the first sub switch 870 in the second phase to provide the test output signal TSO to the detection controller 890.
In some example embodiments, the plurality of second sub switches 881, 882, 883, 884, and 885 may in response to the third switching control signal SCS3 provide all of the plurality of horizontal conduction loops HLOOP11, HLOOP12, HLOOP13, HLOOP14 and HLOOP15 with the second power PWR2 provided to the first node N11 in the first phase, and sequentially connect the plurality of horizontal conduction loops to HLOOP11, HLOOP12, HLOOP13, HLOOP14 and HLOOP15 to the detection controller 890 through the first node N11 and the first sub switch 870 in the second phase.
When the plurality of horizontal conduction loops to HLOOP11, HLOOP12, HLOOP13, HLOOP14 and HLOOP15 are sequentially connected to the detection controller 890 through the first node N11 and the first sub switch 870 in the second phase and the test output signal TSO in responding to the test input signal TSI is detected, at least one of the plurality of horizontal conduction loops to HLOOP11, HLOOP12, HLOOP13, HLOOP14 and HLOOP15 in which a crack occur, may be specified.
Referring to
Various semiconductor integrated circuits may be formed in the central region CTREG depending on a kind or type of the semiconductor device 1000a. For example, the semiconductor device 1000a may be or include or be included in a nonvolatile memory device and a memory integrated circuit may be formed in the central region CTREG of the semiconductor die.
The external region EREG may be a region in which no element is formed or dummy elements are formed. The external region EREG may be a place having a space margin in case of a damaged part when dicing the wafer to the semiconductor device 1000a.
Even if a crack, e.g., a cracking phenomenon of the semiconductor device 1000a occurs in the external region EREG, there may be no problem in the direct operation of the semiconductor device 1000a. However, when cracks occur in the central region CTREG of the semiconductor device 1000a or proceed from the external region EREG to the central region CTREG, the reliability of the operation of the semiconductor device 1000a may be greatly impaired.
The chip guard ring GR may be formed inside the semiconductor die along an edge of the semiconductor die to separate the central region CTREG and the external region EREG. The chip guard ring GR may be located between the central region CTREG and the external region EREG. The chip guard ring GR may serve to block progress of the above-described cracks from the external region EREG to the central region CTREG.
Alternatively or additionally, the chip guard ring GR may perform a moisture absorption action which prevents or reduces external moisture from entering the inside of the semiconductor device 1000. In other words, when moisture enters the central region CTREG of the semiconductor device 1000, the elements located in the central region CTREG of the semiconductor device 1000a may be damaged or malfunction. The chip guard ring GR may prevent or reduce the likelihood of such problems.
The chip guard ring GR may be formed while making a closed curve along the edge of the semiconductor die. Here, “closed curve” refers to ring shapes that are in contact with one another, but does not necessarily indicate that the extended portion of the chip guard ring GR necessarily has curvature. For example, the horizontal arrangement shape of the chip guard ring GR be a polygon such as a rectangle, rather than a circle or an ellipse.
The crack detection structure CDS may be formed along an edge of the central region CTREG in a form of a closed curve.
The semiconductor device 1000a may further include pads PD11 and PD12 and a detection controller DCON 890a.
The detection controller 890a may induce an electrical short circuit between the crack detection structure CDS and the chip guard ring GR by applying a power to the crack detection structure in a first phase, may apply a test input signal to the chip guard ring GR in a second phase, and may determine whether a progressive crack occurs in the central region CTREG based on whether a test output signal responding to the test input signal is detected in the crack detection structure CDS.
The pads PD11 and PD12 may be selectively used when applying the power to the crack detection structure CDS and applying the test input signal to the chip guard ring GR.
Each of the chip guard ring GR and the crack detection structure may be formed along the first direction X and the second direction Y and may extend in the third direction Z perpendicular to the first direction X and the second direction Y.
Referring to
The crack detection structure CDS may be spaced apart from the chip guard ring GR by a first gap d11 in the first direction X.
Referring to
Because the crack detection structure CDS forms a conduction loop, an electric field is generated from the crack detection structure CDS to the chip guard ring GR when a power is applied to the crack detection structure CDS. When the electric field is generated, electrons may move from the chip guard ring GR to the crack detection structure CDS along a reverse direction of the electric field, an electrical short circuit is induced between the chip guard ring GR and the crack detection structure due to a crack and/or a delamination occurring around the crack detection structure CDS, and the crack detection structure CDS and the chip guard ring GR are electrically connected or shorted. Therefore, electrical loading becomes greater and a progressive crack may be detected based on delay of a test output signal.
Referring to
The first switch circuit 850a may, in response to a first switching control signal SCS1a, provide a power supply voltage VPP to the crack detection structure CDS during a first time interval in a first phase, and may connect the crack detection structure CDS to the detection controller 890a to provide the test output signal TSO to the detection controller 890a during a second time interval in a second phase.
The second switch circuit 860a may, in response to a second switching control signal SCS2a, provide the ground voltage VSS to the chip guard ring GR during the first time interval in the first phase and may provide the test input signal TSI to the chip guard ring GR during the second time interval in the second phase.
When the power supply voltage VPP is applied to the crack detection structure CDS in the first phase, an electric field is generated from the crack detection structure CDS to the chip guard ring GR. When the electric field is generated, electrons move from the chip guard ring GR to the crack detection structure CDS along a reverse direction of the electric field, a progression of a crack occurring in the chip guard ring GR is accelerated due to the electrons and the crack proceeds to the crack detection structure CDS. The detection controller 890a may apply the test input signal TSI to the chip guard ring GR in the second phase and may determine whether a crack occurs in the central region CTREG based on whether the test output signal TSO responding to the test input signal TSI is received.
The semiconductor device 1000 may include a semiconductor die and the semiconductor die includes a central region CTREG in which a semiconductor integrated circuit is formed and an external region EREG surrounding the central region CTREG and a chip GR formed along an edge of the semiconductor die to separate the central region CTREG and the external region EREG.
Referring to
The detection controller 890 may apply a test input signal TSI to the first crack detection structure CDS1 during a second time interval in a second phase (operation S120).
The detection controller 890 may determine whether a progressive crack occurs in the central region CTREG based on whether a test output signal TSO responding to the test input signal TSI is detected in the second crack detection structure CDS2 in the second phase (operation S130). Based on a result of the test output signal TSO, the semiconductor device may be scrapped or downgraded, leading to an improved yield and/or reliability and/or an earlier detection of inoperable parts and/or a decrease in fabrication time and/or costs (operation S140).
For applying the test input signal TSI to the first crack detection structure CDS1, the detection controller 890 may apply a pulse signal or a DC voltage to the first crack detection structure CDS1 during the second time interval in the second phase. When a pulse signal or a DC voltage is detected in the second crack detection structure CDS2, the detection controller 890 determines that the progressive crack occurs in the central region CTREG.
Accordingly, the semiconductor device according to some example embodiments, may accelerate a progression of a crack occurring around the first crack detection structure by applying a first power and a second power having a voltage level difference to the first crack detection structure and the second crack detection structure, respectively, in the first phase, may apply a pulse signal or a DC voltage to the first crack detection structure in a second phase and may determine whether a progressive crack occurs in the central region based on whether the pulse signal or the DC voltage is detected in the second crack detection structure, in the second phase. Therefore, the semiconductor device according to some example embodiments may be screened when having potential defects and thus reliability of the semiconductor device may be enhanced.
Hereinafter, it is assumed that a semiconductor device corresponds to a nonvolatile memory device; however, example embodiments are not limited thereto.
Referring to
The memory cell array 200 may be coupled to the address decoder 330 through a string selection line SSL, a plurality of word-lines WLs, and a ground selection line GSL.
In addition, the memory cell array 200 may be coupled to the page buffer circuit 310 through a plurality of bit-lines BLs. The memory cell array 200 may include a plurality of nonvolatile memory cells coupled to the plurality of word-lines WLs and the plurality of bit-lines BLs.
The memory cell array 200 may include a plurality of memory blocks BLK1 through BLKz, and each of the memory blocks BLK1 through BLKz may have a three-dimensional (3D) structure. Here, z is an integer greater than two. The memory cell array 200 may include a plurality of (vertical) cell strings (e.g., NAND strings) and each of the cell strings includes a plurality of memory cells stacked with respect to each other.
The control circuit 350 may receive a command CMD, an address ADDR, and a control signal CTRL from an external memory controller and may control, for example, an erase loop, a program loop and a read operation of the nonvolatile memory device 100. The program loop may include a program operation and a program verification operation and the erase loop may include an erase operation and an erase verification operation.
In various example embodiments, the control circuit 350 may generate control signals CTLs, which are used for controlling the voltage generator 340, based on the command CMD, may generate a page buffer control signal PCTL for controlling the page buffer circuit 310, and may generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 350 may provide the row address R_ADDR to the address decoder 330, may provide the column address C_ADDR to the data I/O circuit 320, may provide the control signals CTLs to the voltage generator 340 and may provide the page buffer control signal PCTL to the page buffer circuit 310.
The address decoder 330 may be coupled to the memory cell array 200 through the string selection line SSL, the plurality of word-lines WLs, and the ground selection line GSL, During program operation or read operation, the address decoder 330 may determine one of the plurality of word-lines WLs as a selected word-line based on the row address R_ADDR and may determine the rest of the plurality of word-lines WLs except the selected word-line as unselected word-lines.
The voltage generator 340 may generate word-line voltages VWLs associated with operations of the nonvolatile memory device 100 using an external voltage EVC provided from the memory controller based on control signals CTLs from the control circuit 350. The word-line voltages VWLs may be applied to the plurality of word-lines WLs through the address decoder 330.
For example, during the erase operation, the voltage generator 350 may apply an erase voltage to a well of a selected memory block and may apply a ground voltage to all word-lines of the selected memory block. During the erase verification operation, voltage generator 350 may apply an erase verification voltage to all word-lines of the selected memory block or may apply the erase verification voltage to the word-lines of the selected memory block on a word-line basis.
For example, during the program operation, the voltage generator 350 may apply a program voltage to the selected word-line and may apply a program pass voltage to the unselected word-lines. Alternatively or additionally, during the program verification operation, the voltage generator 350 may apply a program verification voltage to the selected word-line and may apply a verification pass voltage to the unselected word-lines. Alternatively or additionally, during the read operation, the voltage generator 350 may apply a read voltage to the selected word-line and may apply a read pass voltage to the unselected word-lines.
The page buffer circuit 310 may be coupled to the memory cell array 200 through the plurality of bit-lines BLs. The page buffer circuit 310 may include a plurality of page buffers PB. The page buffer circuit 310 may temporarily store data to be programmed in a selected page or data read out from the selected page of the memory cell array 200.
In some example embodiments, page buffer units included in each of the plurality of page buffers PB (and cache latches included in each of the plurality of page buffers PB may be spaced apart from each other, and may have separate structures. Accordingly, the degree of freedom of wirings on the page buffer units may be increased, and the complexity of a layout may be reduced. In addition, because the cache latches are adjacent to data I/O lines, the distance between the cache latches and the data I/O lines may be reduced, and thus, data I/O speed may be increased.
The data I/O circuit 320 may be coupled to the page buffer circuit 310 through a plurality of data lines DLs. During the program operation, the data I/O circuit 320 may receive program data DATA from the memory controller and provide the program data DATA to the page buffer circuit 310 based on the column address C_ADDR received from the control circuit 450. During the read operation, the data I/O circuit 320 may provide read data DATA to the memory controller based on the column address C_ADDR received from the control circuit 350.
Referring to
In some example embodiments, the memory cell array 200 in
Accordingly, the nonvolatile memory device 100 may have a structure in which the memory cell array 200 is disposed on the peripheral circuit 300, that is, a cell over periphery (COP) structure. The COP structure may effectively reduce an area in a horizontal direction and increase the degree of integration of the nonvolatile memory device 100.
In some example embodiments, the second semiconductor layer L2 may include a substrate, and by forming transistors on the substrate and metal patterns for wiring transistors, the peripheral circuit 300 may be formed in the second semiconductor layer L2. After the peripheral circuit 300 is formed on the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 200 may be formed, and the metal patterns for connecting the word-lines WL and the bit-lines BL of the memory cell array 200 to the peripheral circuit 300 formed in the second semiconductor layer L2 may be formed. For example, the word-lines WL may extend in the first direction X and the bit-lines BL may extend in the second direction Y.
Referring to
The memory block BLKi of
Referring to
The string selection transistor SST may be connected to corresponding string selection lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 may be connected to corresponding word-lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to corresponding ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to corresponding bit-lines BL1, BL2 and BL3, and the ground selection transistor GST may be connected to the common source line CSL.
Word-lines (e.g., WL1) having the same height may be commonly connected, and the ground selection lines GSL1 to GSL3 and the string selection lines SSL1 to SSL3 may be separated.
Referring to
The memory cell array 610 may include first through sixteenth bank arrays 610a˜610p. The row decoder 560 may include first through sixteenth row decoders 560a˜560p respectively coupled to the first through sixteenth bank arrays 610a˜610p, the column decoder 570 may include first through sixteenth column decoders 570a˜570p respectively coupled to the first through sixteenth bank arrays 610a˜610p, and the sense amplifier unit 585 may include first through sixteenth sense amplifiers 585a˜585p respectively coupled to the first through sixteenth bank arrays 610a˜610p.
The first through sixteenth bank arrays 610a˜610p, the first through sixteenth row decoders 560a˜560p, the first through sixteenth column decoders 570a˜570p and first through sixteenth sense amplifiers 585a˜585p may form first through sixteenth banks. Each of the first through sixteenth bank arrays 610a˜610p includes a plurality of memory cells MC formed at intersections of a plurality of word-lines WL and a plurality of bit-lines BTL.
The address register 520 may receive the address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDR from an external memory controller. The address register 520 may provide the received bank address BANK_ADDR to the bank control logic 530, may provide the received row address ROW_ADDR to the row address multiplexer 540, and may provide the received column address COL_ADDR to the column address latch 550.
The bank control logic 530 may generate bank control signals in response to the bank address BANK_ADDR. One of the first through sixteenth row decoders 560a˜560s corresponding to the bank address BANK_ADDR is activated in response to the bank control signals, and one of the first through sixteenth column decoders 570a˜570p corresponding to the bank address BANK_ADDR is activated in response to the bank control signals.
The row address multiplexer 540 may receive the row address ROW_ADDR from the address register 520, and may receive a refresh row address REF_ADDR from the refresh control circuit 700. The row address multiplexer 540 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address SRA. The row address SRA that is output from the row address multiplexer 240 is applied to the first through sixteenth row decoders 560a˜560p.
The refresh control circuit 700 may sequentially increase or decrease the refresh row address REF_ADDR in a normal refresh mode under control the control logic circuit 510.
The activated one of the first through sixteenth row decoders 560a˜560p, by the bank control logic 530, may decode the row address SRA that is output from the row address multiplexer 540, and may activate a word-line corresponding to the row address SRA. For example, the activated bank row decoder applies a word-line driving voltage to the word-line corresponding to the row address.
The column address latch 550 may receive the column address COL_ADDR from the address register 520, and may temporarily store the received column address COL_ADDR. In some embodiments, in a burst mode, the column address latch 550 may generate column address COL_ADDR′ that increment from the received column address COL_ADDR. The column address latch 550 may apply the temporarily stored or generated column address COL_ADDR′ to the first through sixteenth column decoders 570a˜570p.
The activated one of the first through sixteenth column decoders 570a˜570p activates a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I/O gating circuit 590.
The I/O gating circuit 590 may include a circuitry for gating input/output data, and may further include input data mask logic, read data latches for storing data that is output from the first through sixteenth bank arrays 610a˜610p, and write drivers for writing data to the first through sixteenth bank arrays 610a˜610p.
Codeword CW read from a selected one bank array of the first through sixteenth bank arrays 610a˜610s is sensed by a sense amplifier coupled to the selected one bank array from which the data is to be read, and is stored in the read data latches. The codeword CW stored in the read data latches may be provided to the data I/O buffer 620 as data DTA after ECC decoding is performed on the codeword CW by the ECC engine 650. The data I/O buffer 620 may convert the data DTA into the data signal DQ and may transmit the data signal DQ along with the data strobe signal DQS to the memory controller.
The data signal DQ to be written in a selected one bank array of the first through sixteenth bank arrays 610a˜610p may be provided to the data I/O buffer 320 from the memory controller. The data I/O buffer 620 may convert the data signal DQ to the data DTA and may provide the data DTA to the ECC engine 650. The ECC engine 650 may perform an ECC encoding on the data DTA to generate parity bits, and the ECC engine 650 may provide the codeword CW including data DTA and the parity bits to the I/O gating circuit 590. The I/O gating circuit 590 may write the codeword CW in a sub-page in the selected one bank array through the write drivers.
The data I/O buffer 620 may provide the data signal DQ from the memory controller to the ECC engine 650 by converting the data signal DQ to the data DTA in a write operation of the semiconductor device 500 and may convert the data DTA to the data signal DQ from the ECC engine 650 and may transmit the data signal DQ and the data strobe signal DQS to the memory controller in a read operation of the semiconductor device 500.
The ECC engine 650 may perform an ECC encoding on the data DTA and may perform an ECC decoding on the codeword CW based on a second control signal CTL2 from the control logic circuit 510.
The clock buffer 525 may receive the clock signal CK, may generate an internal clock signal ICK by buffering the clock signal CK, and may provide the internal clock signal ICK to circuit components processing the command CMD and the address ADDR.
The strobe signal generator 535 may receive the clock signal CK, may generate the data strobe signal DQS based on the clock signal CK and may provide the data strobe signal DQS to the data I/O buffer 620.
The control logic circuit 510 may control operations of the semiconductor device 500. For example, the control logic circuit 510 may generate control signals for the semiconductor device 500 in order to perform a write operation, a read operation, a normal refresh operation. The control logic circuit 510 may include a command decoder 511 that decodes the command CMD received from the memory controller and a mode register 512 that sets an operation mode of the semiconductor device 500.
For example, the command decoder 511 may generate the control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 510 may provide a first control signal CTL1 to the I/O gating circuit 590, and a second control signal CTL2 to the ECC engine 650.
The semiconductor device 500 of
Referring to
The word-lines WL0˜WLm-1 coupled to the plurality of memory cells MCs may be referred to as rows of the first bank array 610a and the bit-lines BTL0˜BTLn-1 coupled to the plurality of memory cells MCs may be referred to as columns of the first bank array 610a.
In
Referring to
Crack detection structures according to some example embodiments may be applied to any electronic devices and systems formed using semiconductor dies. For example, example embodiments may be applied to systems such as one or more of a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IOT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, an automotive, etc.
Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.
The foregoing is illustrative of some example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those of ordinary skill in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Accordingly, all such modifications are intended to be included within the scope of example embodiments as defined in the claims. Furthermore example embodiments are not necessarily mutually exclusive with one another. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0186658 | Dec 2022 | KR | national |
