Patent Application
20220052113
This application claims benefit of priority to Korean Patent Application No. 10-2020-0102222 filed on Aug. 14, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to semiconductor devices, and more particularly, to a semiconductor device including a data storage material pattern and a selector material pattern.
With the trend for high performance and low power consumption in semiconductor devices such as memory devices, next-generation memory devices such as PRAM, RRAM, and the like, have been developed. Such next-generation memory devices may have resistance values varying depending on current or voltage and may maintain resistance values thereof even when current or voltage supplies thereof are interrupted.
Example embodiments provide a semiconductor device including a data storage material pattern and a selector material pattern.
According to an example embodiment, a semiconductor device includes a semiconductor substrate, a circuit element on the semiconductor substrate, a lower insulating structure covering the circuit element, circuit interconnections in the lower insulating structure on the circuit interconnections being electrically connected to the circuit element, and an upper structure on the lower insulating structure. The upper structure includes first conductive lines, second conductive lines, and a memory cell structure between the first conductive lines and the second conductive lines. The first conductive lines extend in a first horizontal direction. The second conductive lines extend in a second horizontal direction, perpendicular to the first horizontal direction. The memory cell structure includes at least three electrode patterns, a data storage material pattern, and a selector material pattern overlapping each other in a vertical direction. The selector material pattern includes a threshold switching material and a metal material. The threshold switching material includes germanium (Ge), arsenic (As), and selenium (Se), and the metal material includes at least one of tungsten (W), titanium (Ti), aluminum (Al), and copper (Cu). A content of the metal material in the selector material pattern is greater than 0 atomic % and less than 2 atomic %.
According to an example embodiment, a semiconductor device includes a semiconductor substrate, first conductive lines extending in a first horizontal direction on the semiconductor substrate, a memory cell structure on the first conductive lines, and second conductive lines on the memory cell structure and extending in a second horizontal direction perpendicular to the first horizontal direction. The memory cell structure includes a first electrode pattern on the first conductive lines, a second electrode pattern on the first electrode pattern, and a data storage material pattern and a selector material pattern between the first electrode pattern and the second electrode pattern. The selector material pattern includes a threshold switching material including germanium (Ge), arsenic (As), and selenium (Se). The selector material pattern includes a metal material in common with the first conductive lines or the second conductive lines. The metal material of the selection material pattern is in a region adjacent to side surfaces of the selector material pattern.
According to an example embodiment, a semiconductor device includes a semiconductor substrate, first conductive lines extending in a first horizontal direction on the semiconductor substrate, second conductive lines on the first conductive lines and extending in a second horizontal direction perpendicular to the first horizontal direction, and a memory cell structure between the first conductive lines and the second conductive lines. The memory cell structure includes a first electrode pattern on the first conductive lines, a second electrode pattern on the first electrode pattern, and a data storage material pattern and a selector material pattern between the first electrode pattern and the second electrode pattern. The selector material pattern includes a first material, a second material, and a third material. The first material includes at least one of germanium (Ge), arsenic (As), and selenium (Se). The second material includes at least one of tellurium (Te), silicon (Si), indium (In), and gallium (Ga). The third material includes at least one of tungsten (W), titanium (Ti), aluminum (Al), and copper (Cu). A content of the first material and a content of the second material are each greater than a content of the third material.
The above and other aspects, features, and effects of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings.
When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes.
Expressions such as “at least one of,” when preceding a list of elements (e.g., A, B, and C), modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of A, B, and C,” “at least one of A, B, or C,” “one of A, B, C, or a combination thereof,” and “one of A, B, C, and a combination thereof,” respectively, may be construed as covering any one of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.”
Hereinafter, a semiconductor device according to an example embodiment will be described with reference to
Referring to
The lower structure 10 may include a semiconductor substrate 6, a circuit element 20 on the semiconductor substrate 6, a lower insulating structure 30 covering the circuit element 20 on the semiconductor substrate 6, and contact plugs 40 and circuit interconnections 50 disposed in the lower insulating structure 30 on the semiconductor substrate 60 and electrically connected to the circuit element 20.
The semiconductor substrate 6 may be a single-crystalline silicon substrate. An isolation layer 9s may be formed in the semiconductor substrate 6 to define an active region 9a.
The circuit elements 20 may include a gate electrode 25, a gate insulating layer 26, and source/drain regions 28. The gate electrode 25 may be disposed on the active regions 9a defined by the isolation layer 9s. The source/drain regions 28 may be formed in active regions 9a adjacent to opposite sides of the gate electrode 25. The gate insulating layer 26 may be disposed between the gate electrode 25 and the active region 9a. As an example, a spacer layer may be further disposed on both sidewalls of the gate electrode 25.
The lower insulating structure 30 may be disposed on the circuit element 20 on the semiconductor substrate 6. The circuit contact plugs 40 may be connected to the source/drain regions 28 through a portion of the lower insulating structure 30. An electrical signal may be applied to the circuit element 20 by the circuit contact plugs 40. The circuit interconnections 50 may be connected to the circuit contact plugs 40, and may be disposed as a plurality of layers. The circuit element 20 may be connected to the first conductive lines CL1 or the second conductive lines CL2 through additional contact plugs.
The first conductive lines CL1 may extend upwardly of the semiconductor substrate 6 in a first horizontal direction X, and may be disposed to be spaced apart from each other in a second horizontal direction Y. The first conductive lines CL may include a plurality of conductive lines disposed to be parallel to each other. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other.
The second conductive lines CL2 may extend upwardly of the first conductive lines CL1 in the second horizontal direction Y, and may be disposed to be spaced apart from each other. The second conductive lines CL2 may include a plurality of conductive lines disposed to be parallel to each other.
As an example, a thickness of each of the second conductive lines CL2 may be greater than a thickness of each of the first conductive lines CL1. For example, a thickness of each of the second conductive lines CL2 may be about two to three times a thickness of each of the first conductive lines CL1, but the present disclosure is not limited thereto.
As an example, one of the first conductive lines CL1 and the second conductive lines CL2 may be wordlines, and the other may be bitlines. As an example, the first conductive lines CL may be wordlines, and second conductive lines CL2 may be bitlines. As another example, the first conductive lines CL1 may be bitlines, and the second conductive lines CL2 may be wordlines.
As an example, each of the first conductive lines CL may include a first lower conductive layer and a second lower conductive layer sequentially stacked. The first lower conductive layer may be formed as a barrier layer such as a titanium nitride, a tungsten nitride, or the like, and the second lower conductive layer may be formed of a metal material such as tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), or the like. The second conductive lines CL2 may also include a first upper conductive layer and a second upper conductive layer sequentially stacked. The first upper conductive layer may be formed as the barrier layer, and the second upper conductive layer may be formed of a metal material such as tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), or the like.
As an example, the upper structure 100 may further include first insulating patterns 112 on side surfaces of the first conductive lines CL1 and second insulating patterns 192 on side surfaces of the second conductive lines CL2. The first insulating patterns 112 may be disposed to extend between the first conductive lines CL1 in the first horizontal direction X. The second insulating patterns 192 may be disposed to extend between the second conductive lines CL2 in the second horizontal direction Y. The first insulating patterns 112 may be repeatedly arranged alternately with the first conductive lines CL1 in the second direction Y. The second insulating patterns 192 may be repeatedly arranged alternately with the second conductive lines CL2 in the first direction X. The first insulating patterns 112 and the second insulating patterns 192 may include at least one of SiN, SiON, SiC, SiCN, SiOC, SiOCN, SiO2, and Al2O3.
The memory cell structure MC may include N electrode patterns (where N is an integer of 3 or more), a data storage material pattern 160, and a selector material pattern 130 overlapping in a vertical direction, For example, the memory cell structure MC may include a first electrode pattern 120, the selector material pattern 130, intermediate electrode patterns 140 and 150, the data storage material pattern 160, and second electrode patterns 170 and 180, which are sequentially stacked on the first conductive lines CL.
The memory cell structure MC may have a structure in which a plurality of patterns have central portions matching each other in a vertical direction Z. For example, the selector material pattern 130 and the data storage material pattern 160 may overlap each other in the vertical direction Z. The selector material pattern 130 and the data storage material pattern 160 may be arranged in a region in which the first conductive lines CL1 and the second conductive lines CL2 intersect each other.
The memory cell structure MC may include a plurality of patterns having, for example, a quadrangular shape such a square or a rectangle, or a circular shape, when viewed from above.
The first electrode pattern 120 may be disposed between the first conductive lines CL1 and the selector material pattern 130. The second electrode patterns 170 and 180 may be disposed between the data storage material pattern 160 and the second conductive lines CL2. The intermediate electrode patterns 140 and 150 may be disposed between the selector material pattern 130 and the data storage material pattern 160.
The first electrode pattern 120 may be a carbon material layer or a carbon-containing material layer. As an example, the carbon-containing material layer may be a material layer in which at least one of a nitrogen element and a metal element is contained in a carbon material layer. For example, the carbon-containing material layer may be formed of a conductive material including a metal-based metal element, such as a W-based metal element or a Ti-based metal element, and a carbon element, for example, a metal-carbon alloy material such as a tungsten carbide (WC) or a titanium carbide (TiC). The metal element of the metal-carbon alloy material is not limited to W and Ti, and may include another metal element (for example, Ta, Co, or the like) capable of forming an alloy with carbon (C).
Hereinafter, it will be understood that, as described above, a carbon-containing material layer is a conductive material layer including a carbon element with at least one of a nitrogen element and a metal element, unless described additionally.
The intermediate electrode patterns 140 and 150 may include a first intermediate electrode layer 140 and a second intermediate electrode layer 150 sequentially stacked. The intermediate electrode layer 140 may have a greater thickness than a thickness of the second intermediate electrode layer 150. The first intermediate electrode layer 140 may be in contact with the selector material pattern 130, and the second intermediate electrode layer 150 may be in contact with the data storage material pattern 160. The first intermediate electrode layer 140 may be a carbon material layer or a carbon-containing material layer, and the second intermediate electrode layer 150 may be a metal layer or a metal-alloy layer. For example, the second intermediate electrode layer 150 may include a conductive material such as W, WN, TiN, or the like.
The second electrode patterns 170 and 180 may include a first upper electrode layer 170 and a second upper electrode layer 180 sequentially stacked. The first upper electrode layer 170 may have a smaller thickness than a thickness of the second upper electrode layer 180. The first upper electrode layer 170 may be in contact with the data storage material pattern 160, and the second upper electrode layer 180 may be in contact with the second conductive line CL2. The first upper electrode layer 170 may include a conductive material such as W, WN, TiN, or the like. The second upper electrode layer 180 may be a carbon material layer or a carbon-containing material layer.
The selector material pattern 130 may be disposed between the first electrode pattern 120 and the intermediate electrode patterns 140 and 150. The selector material pattern 130 may constitute an ovonic threshold switching device.
As an example, the selector material pattern 130 may be formed of a chalcogenide-based ovonic threshold switching material maintaining an amorphous phase when a semiconductor device operates.
For example, the selector material pattern 130 may include an alloy material, including at least two or more elements among As, S, Se, Te, and Ge, or an additional element (for example, Si, N, or the like) maintaining the amorphous phase at a higher temperature in addition to the alloy material
As a detailed example, the selector material pattern 130 may include at least one composition, among a binary composition such as GeSe, GeS, AsSe, AsTe, AsS SiTe, SiSe, SiS, GeAs, SiAs, SnSe, and SnTe, a ternary composition such as GeAsTe, GeAsSe, AlAsTe, AlAsSe, SiAsSe, SiAsTe, GeSeTe, GeSeSb, GaAsSe, GaAsTe, InAsSe, InAsTe, SnAsSe, and SnAsTe, a quaternary composition such as GeSiAsTe, GeSiAsSe, GeSiSeTe, GeSeTeSb, GeSiSeSb, GeSiTeSb, GeSeTeBi, GeSiSeBi, GeSiTeBi, GeAsSeSb, GeAsTeSb, GeAsTeBi, GeAsSeBi, GeAsSeIn, GeAsSeGa, GeAsSeAl, GeAsSeTl, GeAsSeSn, GeAsSeZn, GeAsTeIn, GeAsTeGa, GeAsTeAl, GeAsTeTl, GeAsTeSn, and GeAsTeZn, a quinary composition such as GeSiAsSeTe, GeAsSeTeS, GeSiAsSeS, GeSiAsTeS, GeSiSeTeS, GeSiAsSeP, GeSiAsTeP, GeAsSeTeP, GeSiAsSeIn, GeSiAsSeGa, GeSiAsSeAl, GeSiAsSeTl, GeSiAsSeZn, GeSiAsSeSn, GeSiAsTeIn, GeSiAsTeGa, GeSiAsTeAl, GeSiAsTeTl, GeSiAsTeZn, GeSiAsTeSn, GeAsSeTeIn, GeAsSeTeGa, GeAsSeTeAl, GeAsSeTeTl, GeAsSeTeZn, GeAsSeTeSn, GeAsSeSIn, GeAsSeSGa, GeAsSeSAl, GeAsSeSTl, GeAsSeSZn, GeAsSeSSn, GeAsTeSIn, GeAsTeSGa, GeAsTeSAl, GeAsTeSTl, GeAsTeSZn, GeAsTeSSn, GeAsSeInGa, GeAsSeInAl, GeAsSeInTl, GeAsSeInZn, GeAsSeInSn, GeAsSeGaAl, GeAsSeGaTl, GeAsSeGaZn, GeAsSeGaSn, GeAsSeAlTl, GeAsSeAlZn, GeAsSEAlSn, GeAsSeTlZn, GeAsSeTlSn, and GeAsSeZnSn, and a senary composition such as GeSiAsSeTeS, GeSiAsSeTeIn, GeSiAsSeTeGa, GeSiAsSeTeAl, GeSiAsSeTeTl, GeSiAsSeTeZn, GeSiAsSeTeSn, GeSiAsSeTeP, GeSiAsSeSIn, GeSiAsSeSGa, GeSiAsSeSAl, GeSiAsSeSTl, GeSiAsSeSZn, GeSiAsSeSSn, GeAsSeTeSIn, GeAsSeTeSGa, GeAsSeTeSAl, GeAsSeTeSTl, GeAsSeTeSZn, GeAsSeTeSSn, GeAsSeTePIn, GeAsSeTePGa, GeAsSeTePAl, GeAsSeTePTl, GeAsSeTePZn, GeAsSeTePSn, GeSiAsSeInGa, GeSiAsSeInAl, GeSiAsSeInTl, GeSiAsSeInZn, GeSiAsSeInSn, GeSiAsSeGaAl, GeSiAsSeGaTl, GeSiAsSeGaZn, GeSiAsSeGaSn, GeSiAsSeAlSn, GeAsSeTeInGa, GeAsSeTeInAl, GeAsSeTeInTl, GeAsSeTeInZn, GeAsSeTeInSn, GeAsSeTeGaAl, GeAsSeTeGaTl, GeAsSeTeGaZn, GeAsSeTeGaSn, GeAsSeTeAlSn, GeAsSeSInGa, GeAsSeSInAl, GeAsSeSInTl, GeAsSeSInZn, GeAsSeSInSn, GeAsSeSGaAl, GeAsSeSGaTl, GeAsSeSGaZn, GeAsSeSGaSn, and GeAsSeSAlSn.
As an example, the compositions may include at least one of B, C, N, and O in small amount. In an example embodiment, the selector material pattern 130 may have a multilayer structure including two or more layers having different compositions.
As an example, the selector material pattern 130 may be formed of a single switching material layer. As another example, the selector material pattern 130 may be formed of a plurality of layers having different compositions each other.
The data storage material pattern 160 may be disposed between the intermediate patterns 140 and 150 and the second electrode patterns 170 and 180.
As an example, a thickness of the data storage material pattern 160 may be about two to about four times greater than a thickness of the selector material pattern 130.
The data storage material pattern 160 may include a phase change material changing from a crystalline state to an amorphous state or changing from an amorphous state to a crystalline state. For example, the data storage material pattern 160 may include a phase change material such as a chalcogenide material including Ge, Sb, and/or Te. For example, the data storage material pattern 160 may include a phase change material including at least one of Te and Se and at least one of Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, N, and In.
As a detailed example, the data storage pattern 160 may include at least one composition, among a binary composition such as GeTe, GeSe, GeS, SbSe, SbTe, SbS, SbSe, SnSb, InSe, InSb, AsTe, AlTe, GaSb, AlSb, BiSb, ScSb, Ysb, CeSb, DySb, and NdSb, a ternary composition such as GeSbSe, AlSbTe, AlSbSe, SiSbSe, SiSbTe, GeSeTe, InGeTe, GeSbTe, GeAsTe, SnSeTe, GeGaSe, BiSbSe, GaSeTe, InGeSb, GaSbSe, GaSbTe, InSbSe, InSbTe, SnSbSe, SnSbTe, ScSbTe, ScSbSe, ScSbS, YSbTe, YSbSe, YSbS, CeSbTe, CeSbSe, CeSbS, DySbTe, DySbSe, DySbS, NdSbTe, NdSbSe, and NdSbS, a quaternary composition such as GeSbTeS, BiSbTeSe, AgInSbTe, GeSbSeTe, GeSnSbTe, SiGeSbTe, SiGeSbSe, SiGeSeTe, BiGeSeTe, BiSiGeSe, BiSiGeTe, GeSbTeBi, GeSbSeBi, GeSbSeIn, GeSbSeGa, GeSbSeAl, GeSbSeTl, GeSbSeSn, GeSbSeZn, GeSbTeIn, GeSbTeGa, GeSbTeAl, GeSbTeTl, GeSbTeSn, GeSbTeZn, ScGeSbTe, ScGeSbSe, ScGeSbS, YGeSbTe, YGeSbSe, YGeSbS, CeGeSbTe, CeGeSbSe, CeGeSbS, DyGeSbTe, DyGeSbSe, DyGeSbS, NdGeSbTe, NdGeSbSe, and NdGeSbS, and a quinary composition such as InSbTeAsSe, GeScSbSeTe, GeSbSeTeS, GeScSbSeS, GeScSbTeS, GeScSeTeS, GeScSbSeP, GeScSbTeP, GeSbSeTeP, GeScSbSeIn, GeScSbSeGa, GeScSbSeAl, GeScSbSeTl, GeScSbSeZn, GeScSbSeSn, GeScSbTeIn, GeScSbTeGa, GeSbAsTeAl, GeScSbTeTl, GeScSbTeZn, GeScSbTeSn, GeSbSeTeIn, GeSbSeTeGa, GeSbSeTeAl, GeSbSeTeTl, GeSbSeTeZn, GeSbSeTeSn, GeSbSeSIn, GeSbSeSGa, GeSbSeSAl, GeSbSeSTl, GeSbSeSZn, GeSbSeSSn, GeSbTeSIn, GeSbTeSGa, GeSbTeSAl, GeSbTeSTl, GeSbTeSZn, GeSbTeSSn, GeSbSeInGa, GeSbSeInAl, GeSbSeInTl, GeSbSeInZn, GeSbSeInSn, GeSbSeGaAl, GeSbSeGaTl, GeSbSeGaZn, GeSbSeGaSn, GeSbSeAlTl, GeSbSeAlZn, GeSbSeAlSn, GeSbSeTlZn, GeSbSeTlSn, and GeSbSeZnSn.
As an example, the compositions may include at least one of B, C, N, O, P, Cd, W, Ti, Hf, and Zr in a small amount. As an example, the data storage material pattern 160 may have a multilayer structure including two or more layers having different compositions.
The semiconductor device 1 according to example embodiments may further include spacer layers 114, covering side surfaces of the memory cell structure MC, and an interlayer insulating layer 116 filling a space between the memory cell structures MC on the first conductive lines CL1 and the first insulating patterns 112. The spacer layers 114 may cover a portion of upper surfaces of the first conductive lines CL1 and a portion of upper surfaces of the first insulating patterns 112.
As an example, the spacer layers 114 may include at least one of SiN, SiO2, SiON, SiBN, SiCN, SiOCN, Al2O3, AlN, and AlON. The spacer layers 114 may include a plurality of layers.
As an example, the interlayer insulating layer 116 may include at least one of SiN, SiON, SiC, SiCN, SiOC, SiOCN, SiO2, and Al2O3. The interlayer insulating layer 116 may include a plurality of layers.
Referring to Table 1 below, various embodiments in which a composition of the selector material pattern 130 varies will be described.
250
350
In the first embodiment, a threshold switching material of the selector material pattern 130 may be a GeαAsβSeγTeδSiη material. Here, α may be in the range of about 13 atomic % to about 23 atomic %, β may be in the range of about 25 atomic % to about 35 atomic %, γ may be in the range of about 38 atomic % to about 50 atomic %, δ may be in the range of about 0.1 atomic % to about 6 atomic %, and η may be in the range of about 0.1 atomic % to about 8 atomic %.
In the second embodiment, a threshold switching material of the selector material pattern 130 may be a GeαAsβSeγInη material. Here, α may be in the range of about 13 atomic % to about 23 atomic %, β may be in the range of about 25 atomic % to about 35 atomic %, γ may be in the range of about 38 atomic % to about 50 atomic %, and η may be in the range of about 0.1 atomic % to about 6 atomic %.
In the third embodiment, a threshold switching material of the selector material pattern 130 may be a GeαAsβSeγSiηInδ material. Here, α may be in the range of about 13 atomic % to about 23 atomic %, β may be in the range of about 25 atomic % to about 35 atomic %, γ may be in the range of about 38 atomic % to about 50 atomic %, η may be in the range of about 0.1 atomic % to about 8 atomic %, and δ may be in the range of about 0.1 atomic % to about 6 atomic %.
In the fourth embodiment, a threshold switching material of the selector material pattern 130 may be a GeαAsβSeγGaη material. Here, α may be in the range of about 13 atomic % to about 23 atomic %, β may be in the range of about 25 atomic % to about 35 atomic %, γ may be in the range of about 38 atomic % to about 50 atomic %, and η may be in the range of about 0.1 atomic % to about 6 atomic %.
In the fifth embodiment, a threshold switching material of the selector material pattern 130 may be a GeαAsβSeγGaηInδ material. Here, α may be in the range of about 13 atomic % to about 23 atomic %, β may be in the range of about 25 atomic % to about 35 atomic %, γ may be in the range of about 38 atomic % to about 50 atomic %, η may be in the range of about 0.1 atomic % to about 6 atomic %, and δ may be in the range of about 0.1 atomic % to about 6 atomic %.
In the first to fifth embodiments discussed above, a sum of the atomic percentages for elements in the selector material pattern 130 may add up to 100 atomic % or less, but not more than 100 atomic %. For example, in the GeαAsβSeγTeδSiη material of the first embodiment, a sum of α, β, γ, δ, and η may be 100 atomic % or less. As another example, in the GeαAsβSeγInη material of the second embodiment, a sum of α, β, γ, and η may be 100 atomic % or less. In the GeαAsβSeγSiηInδ material of the third embodiment, a sum of α, β, γ, η, and δ may be 100 atomic % or less. In the GeαAsβSeγGaη material of the fourth embodiment, a sum of α, β, γ, and η may be 100 atomic % or less. In the GeαAsβSeγGaηInδ material of the fifth embodiment, a sum of α, β, γ, η, and δ may be 100 atomic % or less.
Table 1 illustrates physical properties and operational durability depending on threshold switching materials of selector material patterns 130 according to the above-described first to fifth embodiments, as compared with the first Comparative Example. The first Comparative Example indicates a case in which elements such as Te, Si, In, Ga, and the like, are not included as threshold switching materials.
Referring to Table 2 below, table 2 illustrates bonding energy of Se to Si, In, and Ga, dopants, and oxide formation enthalpy.
In the first to fifth embodiments, a volatilization temperature Ts and the vitrification temperature Tg are increased, as compared with the first Comparative Example. Referring to Table 2, the Si element, the In element, and the Ga element having high bonding strength may bond to the Se element to increase thermal stability of the threshold switching material. In the first to fifth embodiments, the selector material pattern 130 may include dopants of the Si element, the In element, and the Ga element at a content in the desired and/or alternatively predetermined range to limit and/or prevent a decreasing in band gap energy or crystallization of an entire layer.
In the first to fifth embodiments, a volatilization temperature of the threshold switching material of the selector material pattern 130 may be about 250° C. or higher. In the first to fifth embodiments, a vitrification temperature of the threshold switching material of the selector material pattern 130 may be about 350° C. or higher.
In addition, the referring to Table 2, oxide formation enthalpy of the In element may have a small value of, value of oxide formation enthalpy of the Si element may have a greatest value, and value of oxide formation enthalpy of the Ga element may have an intermediate value between the values of the oxide formation enthalpy of the In element and the Si element. The term “oxide formation enthalpy” refers to a value representing the degree of stability in an oxide state. The higher the oxide formation enthalpy, the more oxidation is readily performed and the more an oxide is stable. Since the In element has less bonding strength to Se element than Si element but has low oxide formation enthalpy, the In element may significantly reduce oxide formation, and all In elements may participate in bonding to the Se element and may improve thermal stability, electrical characteristics and operational durability of the threshold switching material.
In the first to fifth embodiments, leakage current Ioff is decreased and the amount of variation in a threshold voltage Vth is decreased, as compared with the first Comparative Example. The amount of variation in the threshold voltage Vth represents a value of time-dependent variations of the threshold voltage Vth. The improvement in characteristics of the leakage current Ioff and the threshold voltage Vth may result from an increase in thermal stability of the threshold switching material which is achieved by including dopants of the Si element, the In element, and/or the Ga element in the selector material pattern 130 at the content in the above-described range.
Referring to
In the first to fifth embodiments, operational durability may be improved, as compared with the first Comparative Example. The improvement in the operational durability may result from an increase in thermal stability of the threshold switching material which is achieved by including the dopant of the Si element, the In element, and/or the Ga element in the selector material pattern 130 at the content in the above-described range. In particular, in the first embodiment, the number of operations until significant variation of the threshold voltage was increased by about 600 times or more, as compared with the first Comparative Example. In the second embodiment, the number of operations until significant variation of the threshold voltage was increased by about 1000 times or more.
Referring to
In the semiconductor device 1 according to the example embodiment, the selector material pattern 130 may further include a metal material. For example, the metal material of the selector material pattern 130 may include at least one of tungsten (W), titanium (Ti), aluminum (Al), and copper (Cu). The metal material may be a metal material common with the first conductive lines CL1 or the second conductive lines CL2. For example, the selector material pattern 130 may include tungsten (W), a metal material in common with the first conductive lines CL1 and the second conductive lines CL2.
As an example, the metal material of the selector material pattern 130 may be distributed in regions adjacent to side surfaces of the selector material pattern 130. Metal materials, generated by etching a portion of the first conductive lines CL1 or the second conductive lines CL2, may be redeposited on the side surfaces of the selector material pattern 130.
As an example, the content of the metal material may be greater than 0 atomic % and less than about 2 atomic %.
As an example, the content of the metal material may be greater than 0.1 atomic % and less than about 2.1 atomic %.
As an example, the content of the metal material may be greater than 1 atomic % and less than about 2.5 atomic %.
Table 3 illustrates operational durability of a threshold switching device depending on the content of a metal element included in the selector material pattern 130. In the case of the second Comparative Example, the content of a metal element (for example, tungsten (W)) included in the selector material pattern 130 is about 2.8 atomic %, and the number of operations repeated until significant variation of a threshold voltage is less than about 3×103. On the other hand, in an example embodiment, a threshold voltage significantly varies when the content of a metal element (for example, tungsten (W)) included in the selector material pattern 130 is about 1.9 atomic %. The number of repeated operations is greater than about 105. For example, when the content of the metal element included in the selector material pattern 130 is less than about 2 atomic %, deterioration in operational durability may be reduced.
When each of the GeαAsβSeγTeδSiη material, the GeαAsβSeγInη material, the GeαAsβSeγSiηInδ material, the GeαAsβSeγGaηmaterial, and the GeαAsβSeγGaηInδ material of the selector material pattern 130 has the above-described composition ratio in the first to fifth embodiments and the content of the metal element included in the selector material pattern 130 is within about 2 atomic %, physical properties and operational durability of the selector material pattern 130 may be improved, as compared with the first Comparative Example, without deteriorating the physical properties and operational durability of the selector material pattern 130.
As an example, the selector material pattern 130 may include a first material including at least one of Ge, As, and Se, and a second material including at least one of Te, Si, In, and Ga, and a third material including at least one of W, Ti, Al, and Cu. The content of the first material and the content of the second material may each be greater than the content of the third material. The content of the first material may be greater than the content of the second material. The content of the third material may be greater than 0 atomic % of the total content of the first to third materials, and may be less than about 2 atomic %.
Referring to
Referring to
The second electrode patterns 170′ and 180′ may include a first lower electrode layer 170′ and a second lower electrode layer 180′. The first lower electrode layer 170′ may have a smaller thickness than the second lower electrode layer 180′. The intermediate electrode pattern 140′ and 150′ may include a first intermediate electrode layer 140′ and a second intermediate electrode layer 150′. The second intermediate electrode layer 150′ may have a smaller thickness than the first intermediate electrode layer 140′. The second lower electrode layer 180′, the first intermediate electrode layer 140′, and the first electrode layer 120′ may be a carbon material layer or a carbon-containing material layer described above. The first lower electrode layer 170′ and the second intermediate electrode layer 150′ may be a metal layer or metal alloy layer described above.
Referring to
Referring to
Referring to
Referring to
The forming of the lower structure 10 may include preparing a semiconductor substrate 6, forming an isolation layer 9s to define an active region 9a in the semiconductor substrate 6, and forming circuit elements 20 and lower insulating structure 30 on the semiconductor substrate 6. The circuit elements 20 may include a gate electrode 25, a gate insulating layer 26, and source/drain regions 28, as described in
First conductive lines CL1 may be formed on the lower insulating structure 30. The forming of the first conductive lines CL1 may include forming a conductive layer and patterning the conductive layer. The first conductive lines CL1 may be formed to extend in a first horizontal direction X. First insulating patterns 112 may be formed between the first conductive lines CL1. The first insulating patterns 112 may be formed to extend in the first horizontal direction X. The forming of the first conductive lines CL1 may include forming a first lower conductive layer and a second lower conductive layer.
Referring to
A portion of the plurality of layers 121, 131, 141, 151, 161, 171, and 181 may be etched in a subsequent process to constitute a memory cell structure MC. The plurality of layers 121, 131, 141, 151, 161, 171, and 181 may be formed to have different thicknesses, or some of plurality of layers 121, 131, 141, 151, 161, 171, and 181 the may be formed to have substantially the same thickness.
Referring to
In the plurality of layers 121, 131, 141, 151, 161, 171, and 181, an external region in a location corresponding to the memory cell structure MC of
In this case, a portion of the first conductive lines CL1 may be exposed in the etching process of the plurality of layers 121, 131, 141, 151, 161, 171, and 181. A metal element, included in the first conductive lines CL1, may be redeposited on the memory cell structure MC by an etchant used in the etching process. The metal element may include at least one of tungsten (W), titanium (Ti), aluminum (Al), and copper (Cu). The content of the metal element redeposited on the selector material pattern 130 may be in the range of about 2 atomic %. The content of the metal element included in the selector material pattern 130 may be limited to about 2 atomic % or less to limit and/or prevent deterioration of the operational durability of the selector material pattern 130 as a threshold switching device.
As another example, the forming of the memory cell structure MC may include patterning the plurality of layers 121, 131, 141, 151, 161, 171, and 181 in a first horizontal direction X, filling a region, in which the plurality of layers 121, 131, 141, 151, 161, 171, and 181 are removed, with an insulating layer, forming second conductive layers, and patterning the second conductive layer, the insulating layer, and the plurality of layers 121, 131, 141, 151, 161, 171, and 181. Thus, the second conductive layer may be formed as second conductive lines CL2, and the plurality of layers 121, 131, 141, 151, 161, 171, and 181 may each be formed as a memory cell structure MC in a region in which the first conductive lines CL1 and the second conductive lines CL2 intersect each other.
Referring to
The interlayer insulating layer 116 may fill a space between the memory cell structures MC on the first conductive lines CL1 and the first insulating patterns 112. Before the interlayer insulating layer 116 is formed, a spacer layer 114 may be formed to cover sidewalls of the memory cell structures MC.
Second conductive lines CL2 may be formed on the memory cell structure MC. The forming of the second conductive lines CL2 may include forming a conductive layer and patterning the conductive layer. The second conductive lines CL2 may be formed to extend in a second horizontal direction Y. Second insulating patterns 192 may be formed between the second conductive lines CL2. The second insulating patterns 192 may be formed to extend in the second horizontal direction Y. The forming of the second conductive lines CL2 may include forming a first upper conductive layer and a second upper conductive layer.
Referring to
The semiconductor device 1200 may be a semiconductor device according to one of the example embodiments described with reference to
The first structure 1200L may include a row driver 1220, a column driver 1230, a control logic 1240 electrically connected to the row driver 1220 and the column driver 1230. The row driver 1220 may include an address decoder circuit for selecting data storage material patterns (for example, 160 in
The second structure 1200U may include a plurality of memory cell structures stacked in a vertical direction.
As an example, the plurality of memory cell structures may include two or more memory cell structures. For example, the plurality of memory cell structures may include first to fourth memory cell structures MC1, MC2, MC3, and MC4 stacked in the vertical direction. Each of the first to fourth memory cell structures MC1, MC2, MC3, and MC4 may include the data storage material pattern 160 and the selector material pattern 130, as illustrated in
According to an example embodiment, a structure may include more than four memory cell structures vertically stacked.
The second structure 1200U may include first conductive lines CL1 disposed between the first memory cell structure MC1 and the first structure 1200L and extending in a first horizontal direction, second conductive lines CL2 extending in a second horizontal direction between the first memory cell structure MC1 and the second memory cell structure MC2, third conductive lines CL3 extending in the first horizontal direction between the second memory cell structure MC2 and the third memory cell structure MC3, fourth conductive lines CL2 extending in the second horizontal direction between the third memory cell structure MC3 and the fourth memory cell structure MC4, and fifth conductive lines CL5 extending in the first horizontal direction on the fourth memory cell structure MC4.
As an example, the first, third, and fifth conductive lines CL1, CL3, and CL5 may be wordlines, and the second and fourth conductive lines CL2 and CL4 may be bitlines.
The second structure 1200U may further include first, third, and fifth contact structures PL1, PL3, and PL5, electrically connecting the first, third, and fifth conductive lines CL1, CL, and CL5 to the row decoder 1200, and second and fourth contact structures PL2 and PL4 electrically connecting the second and fourth conductive lines CL2 and CL4 to the column driver 1230.
The second structure 1200 may include an input/output (I/O) pad 1201. The semiconductor device 1200 may further include an input/output (I/O) contact structure PL6 electrically connected to the I/O pad 1201 and extending inwardly of the first structure 1200L through the second structure 1200U to be electrically connected to a control logic 1240.
The electronic system 1100 may communicate with the controller 1300 through the I/O pad 1201 electrically connected to the control logic 1240. The controller 1300 may include a processor 1310, a memory controller 1322, and a host interface 1330. According to example embodiments, the electronic system 1100 may include a plurality of semiconductor devices 1200. In this case, the controller 1300 may control the plurality of semiconductor devices 1200.
The processor 1310 may control overall operations of the electronic system 1100 including the controller 1300. The processor 1310 may operate according to desired and/or alternatively predetermined firmware, and may control the memory controller 1320 to access the semiconductor device 1200. The memory controller 1320 may include a memory interface 1321 processing communications with the semiconductor device 1200.
A control command for controlling the semiconductor device 1200, data to be written to the data storage material patterns 160 of the memory cell structures MC1, MC2, MC3, and MC4 of the semiconductor device 1200, data to be read from the data storage material patterns 42 of the memory cell structures MC1, MC2, MC3, and MC4 of the semiconductor device 1200, and the like, may be transmitted through the memory interface 1321. The host interface 1330 may provide a communications function between the electronic system 1100 and an external host. When the control command is received from the external host through the host interface 1330, the processor 1310 may control the semiconductor device 1200 in response to the control command.
As described above, a composition of a threshold switching material and the content of a metal element may be adjusted, and thus, a semiconductor device having improved electrical characteristics and reliability may be provided.
One or more of the elements of the controller 1300 in
While some example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of inventive concepts as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2020-0102222 | Aug 2020 | KR | national |
