Patent Application
20160343598
The disclosure of Japanese Patent Application No. 2015-103580 filed on May 21, 2015 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
The present invention relates to a FOUP (Front Opening Unified Pod) and a semiconductor device manufacturing technique which uses the FOUP.
The FOUP is known as a container for carrying and storing a wafer which is used in the manufacturing line for a semiconductor wafer (semiconductor substrate, hereinafter simply called a wafer).
For the FOUP, external airtightness is important in order to prevent foreign substances from the outside from infiltrating the wafer housed in it, so the FOUP is a hermetic wafer container. Since it is a hermetic container, outgas generated from the wafer in the FOUP stagnates in the FOUP.
Therefore, the inside of the FOUP must be cleaned periodically.
Japanese Unexamined Patent Application Publication No. 2014-60375 discloses the shape of the FOUP whose inside can be cleaned efficiently.
However, in the wafer manufacturing line, there are cases that after completion of a prescribed process, the wafer is temporarily stored in the FOUP and then the next step is started while the wafer remains housed in the FOUP. In such a case, the following problem may arise: outgas generated from the wafer stagnates in the FOUP and the outgas reattaches to the wafer without being taken out of the FOUP, resulting in a product defect. An object of the present invention is to increase the productivity of a semiconductor device. Another object thereof is to enhance the reliability of the semiconductor device.
The above and further objects and novel features of the invention will more fully appear from the following detailed description in this specification and the accompanying drawings.
According to one aspect of the present invention, there is provided a semiconductor device manufacturing method which includes the steps of: (a) forming a gate insulating film over a front surface of a semiconductor substrate; (b) forming a gate electrode over the gate insulating film; (c) forming a sidewall spacer comprised of a first insulating film over the front surface of the semiconductor substrate and on a sidewall of the gate electrode; and (d) forming a source region and a drain region on a front surface side of the semiconductor substrate. Furthermore, it includes the steps of: (e) after the steps (a) to (d), forming an etching stopper film comprised of a second insulating film over the gate electrode, over the sidewall spacer, over the source region, and over the drain region; and (f) after the step (e), storing the semiconductor substrate in a FOUP temporarily. Furthermore, the first insulating film and the second insulating film contain silicon and nitrogen, and at the step (f), at least one of the first insulating film and the second insulating film is formed over a back surface of the semiconductor substrate. The FOUP includes a main body having an opening for taking in or out the semiconductor substrate and including an internal space, a cover detachably attached to the main body in close contact with the main body in a manner to cover the opening, a first hole and a second hole which are formed in the main body, and a filter provided on each of the first hole and the second hole. At the step (f), with the semiconductor substrate housed in the internal space of the FOUP, external air is taken into the internal space from one of the first hole and the second hole through the filter and air in the internal space is taken out of the main body from the other of the first hole and the second hole, and at the step (f), the FOUP is stored in a cleanroom.
According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method which includes the steps of: (a) forming a gate insulating film over a front surface of a semiconductor substrate; (b) forming a gate electrode over the gate insulating film; (c) forming a sidewall spacer comprised of a first insulating film over the front surface of the semiconductor substrate and on a sidewall of the gate electrode; and (d) forming a source region and a drain region on a front surface side of the semiconductor substrate. Furthermore, it includes the steps of: (e) after the steps (a) to (d), forming an etching stopper film comprised of a second insulating film over the gate electrode, over the sidewall spacer, over the source region, and over the drain region; (f) forming a first interlayer insulating film over the etching stopper film; and (g) forming a first wiring in a manner to be buried in the first interlayer insulating film. Furthermore, it includes the steps of: (h) forming a barrier insulating film over the first interlayer insulating film and over the first wiring; (i) forming a second interlayer insulating film over the barrier insulating film; (j) forming a contact hole in the second interlayer insulating film; (k) forming an organic film in the contact hole; and (l) after the step (k), storing the semiconductor substrate in a FOUP temporarily. It further includes the steps of: (m) after the step (l), forming a resist pattern over the second interlayer insulating film; (n) forming a trench to be coupled with the contact hole in the second interlayer insulating film using the resist pattern as a mask; and (o) after the step (n), removing the resist pattern and the organic film. Furthermore, it includes the steps of (p) after the step (o), exposing the surface of the first wiring by removing the barrier insulating film on the bottom of the contact hole; and (q) after the step (p), forming a conductive film to fill the trench and the contact hole. The first insulating film and the second insulating film contain silicon and nitrogen, and at the step (l), at least one of the first insulating film and the second insulating film is formed over the back surface of the semiconductor substrate. The FOUP includes a main body having an opening for taking in or out the semiconductor substrate and including an internal space, a cover detachably attached to the main body in close contact with the main body in a manner to cover the opening, a first hole and a second hole which are formed in the main body, and a filter provided on each of the first hole and the second hole. At the step (l), with the semiconductor substrate housed in the internal space of the FOUP, external air is taken into the internal space from one of the first hole and the second hole through the filter and air in the internal space is taken out of the main body from the other of the first hole and the second hole, and at the step (l), the FOUP is stored in a cleanroom.
According to a third aspect of the present invention, there is provided a FOUP which includes: a main body having an opening for taking in or out a semiconductor substrate and including an internal space; a cover detachably attached to the main body in close contact with the main body in a manner to cover the opening; a first hole and a second hole which are formed in the main body; and a filter provided on each of the first hole and the second hole. With the semiconductor substrate housed in the internal space of the main body, external air can be taken into the internal space from one of the first hole and the second hole through the filter and air in the internal space can be taken out of the main body from the other of the first hole and the second hole.
According to the present invention, the productivity of a semiconductor device can be increased and the reliability of the semiconductor device can be enhanced.
As for the preferred embodiments of the invention as described below, basically the same or similar elements or matters will not be repeatedly described except when necessary.
The preferred embodiments of the present invention may be described in different sections or separately as necessary or for the sake of convenience, but the embodiments described as such are not irrelevant to each other unless otherwise expressly stated. One embodiment may be, in whole or in part, a modified, detailed or supplementary form of another.
In the preferred embodiments as described below, when numerical information for an element (the number of pieces, numerical value, quantity, range, etc.) is indicated by a specific number, it is not limited to the specific number unless otherwise specified or theoretically limited to the specific number; it may be larger or smaller than the specific number.
In the preferred embodiments as described below, constituent elements (including constituent steps) are not necessarily essential unless otherwise specified or theoretically essential.
In the preferred embodiments as described below, as for constituent elements, it is obvious that the expression “comprising A”, “comprised of A”, “having A”, or “including A” does not exclude another element unless exclusion of another element is expressly stated. Similarly, in the preferred embodiments as described below, when a specific form or positional relation is indicated for an element, it should be interpreted to include a form or positional relation which is virtually equivalent or similar to the specific form or positional relation unless otherwise specified or theoretically limited to the specific form or positional relation. The same is true for the above numerical values and ranges.
Next, the preferred embodiments of the invention will be described in detail referring to the accompanying drawings. In all the drawings that illustrate the preferred embodiments, members with like functions are designated by like reference numerals and repeated descriptions thereof are omitted. For easy understanding, hatching may be used even in a plan view.
The FOUP 1 according to the first embodiment as shown in
The FOUP 1 according to the first embodiment is structured as follows. As shown in
The main body 2 includes a ceiling surface (top surface) 2a, a bottom surface 2b opposite to the ceiling surface 2a, two side surfaces 2c which are located between the ceiling surface 2a and bottom surface 2b and opposite to each other, and aback surface 2cc (see
A handle 2j is provided in the center of the ceiling surface 2a of the main body 2 so that the FOUP 1 can be grasped.
The cover 3 is tightly attached to a brim 2e around the opening 2d of the main body 2. As shown in
The internal space 2k of the main body 2 of the FOUP 1 can house a plurality of semiconductor wafers 4 in a manner that they are stacked and spaced apart; for example, it can house about 24 wafers. The number of semiconductor wafers 4 which can be housed is not limited to 24.
The FOUP 1 has two first holes and two second holes in the main body 2. In the FOUP 1 according to the first embodiment, two first holes are provided in the ceiling surface 2a and two second holes are provided in the bottom surface 2b. In the first embodiment, the two first holes in the ceiling surface 2a are intake holes 2f and the two second holes in the bottom surface 2b are exhaust holes 2h. In other words, either the first holes or the second holes are provided in the ceiling surface 2a and the other holes (the first or second holes) are provided in the bottom surface 2b.
The two first holes in the ceiling surface 2a and the two second holes in the bottom surface 2b are opposite to each other. Specifically, in the FOUP 1 according to the first embodiment, the two intake holes 2f in the ceiling surface 2a and the two exhaust holes 2h in the bottom surface 2b are located near the opening 2d (front side in the depth direction), facing each other.
Filters 2g and 2i are provided on the holes in a manner to cover the holes. Specifically, the intake holes 2f are covered by the filters 2g and the exhaust holes 2h are covered by the filters 2i.
The filters 2g and 2i are HEPA (High Efficiency Particulate Air) filters and made of grafiber or similar material. However, the filters are not limited to HEPA filters.
In the above structure of the FOUP 1, as shown in
In other words, with semiconductor wafer 4 housed in the FOUP 1, external air is taken into the FOUP and the air 7 stagnating in the FOUP is taken out of the FOUP so that the inside of the FOUP is ventilated.
In the first embodiment, for example, a downflow 6 of N2, etc. outflowing from above is used in a cleanroom 9 as shown in
The filters 2g on the intake holes 2f prevent the infiltration of foreign substances through the intake holes 2f.
The filters 2i on the exhaust holes 2h in the bottom surface 2b have the function as a valve: only when the pressure of the air 7 is given by the downflow 6, the valve is opened by the pressure of the air 7 and the internal air 7 is discharged and when the pressure of the air 7 is not given, the valve is closed to prevent the infiltration of foreign substances from the outside.
Next, the environment in which the FOUP 1 according to the first embodiment is used will be described referring to
In the area for the stocker 10, the FOUP is purged of N2 and the FOUP itself is stored. In the area for the cleanroom 9, the wafer is processed as prescribed in a processing apparatus (production apparatus) 11.
For example, as illustrated by section P and section Q of the stocker 10 shown in
In the area for the cleanroom 9 as well, the inside of the FOUP can be ventilated using the downflow 6 going into the cleanroom 9. For example, when the required processing is finished by the processing apparatus 11 in the area for the cleanroom 9, the FOUP 1 housing the wafer is placed on a stage 11a of the processing apparatus 11 and the wafer is temporarily stored therein, the inside of the FOUP can be ventilated using the downflow 6 coming from above.
In these cases, in the stocker 10 or in the area for the cleanroom 9, the downflow 6 is taken into the internal space 2k through the intake holes 2f in the ceiling surface 2a as shown in
The existence of the filters 2g and 2i on the intake holes 2f and exhaust holes 2h prevents the infiltration of foreign substances from the outside into the FOUP when the downflow 6 is taken into the internal space 2k.
As described above, in the FOUP 1 according to the first embodiment, the inside of the FOUP can be ventilated to discharge the outgas stagnating in the FOUP without using a special exhaust facility.
Consequently, occurrence of defects of the semiconductor substrate (semiconductor wafer 4) due to outgas can be suppressed. In short, product defects due to outgas can be suppressed.
Next, a variation of the first embodiment will be described.
In the FOUP 1 as a variation shown in
In other words, the intake holes 2f and exhaust holes 2h are located so that when the FOUP 1 is viewed sideways, the air 7 in the FOUP flows obliquely from the back surface 2cc side (back side) toward the opening 2d (front side) during ventilation.
Like the FOUP 1 shown in
Consequently, in the FOUP 1 as the variation shown in
As a result, occurrence of defects of the semiconductor substrate (product defects) due to outgas can be suppressed.
In the second embodiment, the size and number of first holes of the FOUP 1 which ensure the achievement of the ventilation effect are calculated in consideration of the strength of the main body 2 and the position of the handle 2j.
Next, the conditions for the above simulation shown in
On the assumption that the FOUP housing a wafer is placed in the stocker 10 shown in
The flow rate Q of N2 in the stocker 10 can be calculated in accordance with equation Q=CA×(2×P÷ρ)1/2 and Q is 0.09−0.45 m3/s(speed: 1−5 m/s). As for the flow path areas A in the FOUP, A1, A2, A3, and A4 in
Under the above preconditions, assuming that the N2 flow velocity is the same as the conveying speed of an OHT (Overhead Hoist Transport) and the FOUP stays for 10 minutes in the stocker 10, the number of intake holes 2f with a diameter of 10 mm in the ceiling surface 2a of the FOUP 1 should be about ten, as shown in
The FOUP 1 shown in
As discussed above, if the flow velocities in the simulation result shown in
The number of intake holes 2f is not limited to ten but it may be any other number larger than one, in consideration of the simulation result, the strength of the main body 2 and other factors.
In the FOUP 1 shown in
In the FOUP 1 shown in
Filters 2g and 2i are provided on the long holes 2n and long holes 2p. Specifically, the filters 2g are provided on the long holes 2n and the filters 2i are provided on the long holes 2p.
The FOUP 1 shown in
Consequently, the inside of the FOUP can be ventilated so that occurrence of semiconductor substrate defects (product defects) due to outgas can be suppressed.
For the FOUP 1 shown in
The formation of the long holes 2n and 2p in the opposite side surfaces 2c of the FOUP 1 enables automatic internal ventilation by the movement of the OHT, etc. to convey the FOUP 1. This means that internal ventilation can be automatically performed during conveyance of the FOUP regardless of whether or not there is a downflow 6 and the outgas stagnating inside the FOUP can be discharged.
The filters 2g and 2i on the long holes 2n and 2p prevent the infiltration of foreign substances together with external air during ventilation.
In the FOUP 1 shown in
The conveying means is not limited to the above vehicle (OHT). For example, even when a conveying mechanism such as a belt conveyor is used, the same effect can be achieved.
In the FOUP 1 shown in
For example, an exhaust fan 12 is provided in the ceiling surface 2a and external air is taken in through the purge port 2m provided in the bottom surface 2b and the outgas inside the FOUP is discharged to the outside by the fan 12 in the ceiling surface 2a. The inside of the FOUP is thus ventilated. The fan 12 has a power source outside the FOUP 1 and for example, when the FOUP 1 is placed on the FOUP stand 5, the power is supplied to start the fan 12.
However, the fan 12 is not limited to an electric fan but it may be rotated by air.
In other words, the FOUP 1 according to the fourth embodiment is provided with the fan 12 so that ventilation can be performed without the need for a downflow 6 or an air flow generated by movement.
Since the fan 12 does not always rotate, a filter 2g is also provided on the fan 12 to prevent the infiltration of foreign substances from the outside.
Alternatively, the fan 12 may be an intake fan and in that case, external air is taken in through the fan 12 and internal outgas is discharged through an exhaust hole 2h in the bottom surface 2b to ventilate the inside of the FOUP.
In the FOUP 1 according to the fourth embodiment as well, the inside of the FOUP can be ventilated by the use of the exhaust or intake fan 12 so that occurrence of semiconductor substrate defects (product defects) due to outgas can be suppressed.
The fifth embodiment concerns a case that while the FOUP is temporarily stored between steps of processing the semiconductor substrate in the semiconductor device manufacturing process, the inside of the FOUP housing a wafer is ventilated. The fifth embodiment is explained below by giving an example of the steps of forming the essential part of a transistor such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in a semiconductor substrate.
First, as shown in
After the formation of the gate electrode 20c, a SiN film 20d is formed over the surface of the P well 20 and over the gate electrode 20c as shown in
After the formation of the SiN film, a sidewall spacer 20e is formed by anisotropically etching the SiN film 20d as shown in
Next, as shown in
After the formation of the source region 20h and drain region 20i, a SiN film (second insulating film) 21 as an etching stopper film is formed as shown in
After the formation of the SiO film 22, a contact plug 23 which is buried in the SiN film 21 and SiO film 22 is formed as shown in
After the formation of the Cu wiring 25, a barrier insulating film 26 is formed over the interlayer insulating film 24 and Cu wiring 25 as shown in
After the formation of the SiO film 28, a via 29 as a contact hole is formed in the interlayer insulating film 27 as shown in
After the formation of the via-fill material 29a, the semiconductor wafer 4 is temporarily stored in the FOUP. More specifically, the semiconductor wafer 4 already subjected to the steps up to the formation of the via-fill material 29a is housed in the FOUP for temporary storage. At the step of storing the semiconductor wafer 4 temporarily, at least one of the SiN film (first insulating film) 20d and the SiN film (second insulating film) 21 has been formed on the back surface of the semiconductor wafer 4. In the semiconductor wafer 4 according to the fifth embodiment, both the SiN film 20d and the SiN film 21 have been formed on the back surface.
The semiconductor wafer 4 thus processed is housed, for example, in the FOUP 1 shown in
Next, the mechanism which causes the above problem will be explained referring to
The reason that the resist film 30 is not made properly at the next step as mentioned above is occurrence of a development failure called poisoning as shown in
Furthermore, if, during the step of forming the via (contact hole) 29, an ammonia plasma process is performed in order to reduce the oxide on the Cu wiring surface after the formation of the via 29 and before burying the via-fill material 29a in the via 29, the ammonia plasma-processed layer on the surface of the interlayer insulating film 24 as a SiOC film becomes an amine source and generates a lot of amine.
As far as the work-in-process is concerned, a SiN film is formed on the wafer back surface before the formation of the via (contact hole) 29, in order to eliminate the possibility that metal ion contamination occurs in the silicon substrate (semiconductor wafer 4) from the lower stage of the production apparatus for the wiring process, the conveyor robot arm or the like through the wafer back surface. The SiN film on the wafer back surface is, for example, an LP—SiN film as an etching stopper film. In some cases, it may be formed as a sidewall spacer film. It has been found from an investigation by the present inventors that NH4+ ions emitted from the SiN film on the wafer back surface has an influence on the increase in the amount of amine on the wafer front surface. The problem is that the amine concentration in the FOUP rapidly increases while the wafer is stored in the FOUP.
Therefore, in the semiconductor device manufacturing method according to the fifth embodiment, while the semiconductor wafer 4 already subjected to the steps up to the formation of the via-fill material 29a is housed in the FOUP and temporarily stored, the inside of the FOUP is ventilated in the cleanroom 9 shown in
Consequently, the amine outgas stagnating in the FOUP is taken out of the main body 2. As a result, the amine concentration in the FOUP decreases, so occurrence of poisoning (development failure) as mentioned above at the next step is suppressed and a correct pattern resist film 30 as shown in
The formation of a correct pattern resist film 30 suppresses the occurrence of semiconductor substrate defects due to outgas, resulting in improvement in the product yield rate. In addition, the desired shape of the wiring trench is maintained, leading to improvement in the reliability of the semiconductor device.
After the ventilation of the FOUP 1 (temporary storage of the wafer) is finished, the wafer is conveyed to the prescribed production apparatus through the FOUP 1 and a resist film (resist pattern) 30 to make a trench is formed over the interlayer insulating film (second interlayer insulating film) 27 as shown in
After the formation of the resist film 30, a trench 33 to be coupled with the via (contact hole) 29 is made in the interlayer insulating film 27 by etching, using the resist film 30 as a mask as shown in
After the removal of the SiCN film 26a, a Cu wiring 34 as a conductive film is formed in a manner to be buried in the trench 33 and the via (contact hole) 29 as shown in
The invention made by the present inventors has been so far explained concretely in reference to the preferred embodiments thereof. However, the invention is not limited thereto and it is obvious that these details may be modified in various ways without departing from the spirit and scope thereof.
The fifth embodiment has been described above on the assumption that a SiN film is formed on the wafer back surface but even when a SiN film is not formed on the wafer back surface, the amine concentration in the FOUP can be decreased by ventilating the inside of the FOUP using the FOUP 1 according to any one of the first to fourth embodiments.
The fifth embodiment has been described above on the assumption that the wafer is stored in the FOUP when a wiring trench is made, but not limited thereto. For example, even when the wafer is stored after the formation of the sidewall spacer 20e and etching stopper film 21, the amine concentration can be kept low by using the FOUP according to one of the above embodiments for storage.
In the FOUPs 1 according to the first to fourth embodiments, at least one hole should be formed in each of the two opposite surfaces of the main body 2 (for example, the ceiling surface 2a and bottom surface 2b or the two opposite side surfaces 2c) and the holes should be each provided with a filter. The number of holes with a filter in one surface is not limited.
Some details of the embodiments described above are given below:
A semiconductor device manufacturing method which includes the steps of:
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-103580 | May 2015 | JP | national |
