Patent Application
20230047052
This disclosure claims the priority of a Chinese patent application, filed with the Chinese Patent Office on Mar. 5, 2020, the application number of 202010149409.5 and titled “Semiconductor Device, Manufacturing Method and Application thereof”, the entire content of which is incorporated herein by reference.
The present disclosure relates to the field of semiconductor devices, and more specifically, to a group III nitride semiconductor device, a manufacturing method and the use thereof.
A group III nitride semiconductor is an important new semiconductor material, which mainly comprises AlN, GaN, InN and compounds of these materials, such as, AlGaN, InGaN, AlInGaN, etc. Utilizing the advantages of the direct band gap, the wide forbidden band, and the high breakdown electric field strength of the group III nitride semiconductors, through optimized design of the structure and process of the devices, the group III nitride semiconductor has great prospects in the field of power semiconductors. The transistors with high electron mobility and high hole mobility are important devices using the group III nitride semiconductors. It is desired to develop a transistor with high electron mobility and high hole mobility, which has high performance, such as, the high withstand voltage, the high power and the low on-resistance, etc.
The existing transistors with high electron mobility and high hole mobility have the structure design in which the integration level per unit area is not high enough, and the existing transistors with high electron mobility and high hole mobility mostly are the normally-on devices, which is not good for energy saving and application security.
In view of this, the present disclosure provides a novel semiconductor device structure and manufacturing method thereof.
In the following, a brief summary of the present disclosure will be given in order to help the basic understanding of certain aspects of the present disclosure. It should be understood that this summary is not an exhaustive summary of the present disclosure. It is not intended to determine the key or important part of the present disclosure, nor is it intended to limit the scope of the present disclosure. Its purpose is merely to present some concepts in a simplified form, as a prelude to the more detailed description that will be discussed later.
According to one aspect of the present disclosure, a manufacturing method for a semiconductor device is provided, comprising:
Step 1: providing a substrate, which has a first surface;
Step 2: forming a first insulating layer on the first surface of the substrate, with the first insulating layer having a first surface parallel to the first surface of the substrate;
Step 3: etching the first insulating layer and a part of the substrate to form a plurality of first step structures and second step structures arranged vertically and spaced apart, wherein a lower part of the first surface of the plurality of first step structures and a lower part of the second surface of the plurality of second step structures are respectively constituted by a second surface and a third surface of the substrate, and an upper part of the first surface of the plurality of first step structures and an upper part of the second surface of the plurality of second step structures are respectively constituted by a second surface and a third surface of the first insulating layer;
Step 4: forming a second insulating layer on third surfaces of the first step structure and the second step structure;
Step 5: forming a single crystal nucleation layer on a second surface of the first step structure, formed by a third surface of the substrate, and forming a single crystal nucleation layer on a first surface of the second step structure, formed by the second surface of the substrate; and
Step 6: making a first semiconductor layer grown epitaxially laterally, with the single crystal nucleation layer as a nucleation center.
According to another aspect of the present disclosure, a manufacturing method for a semiconductor device is provided, comprising:
Step 1: providing a substrate, which has a first surface;
Step 2: forming a first insulating layer on the first surface of the substrate, with the first insulating layer having a first surface parallel to the first surface of the substrate;
Step 3: etching the first insulating layer and a part of the substrate to form a plurality of first trenches (grooves) and second trenches arranged vertically and spaced apart, wherein lower parts of first surfaces and second surfaces of the plurality of first trenches and second trenches are respectively constituted by a second surface and a third surface of the substrate, and upper parts of the first surfaces and the second surfaces of the plurality of first trenches and second trenches are respectively constituted by a second surface and a third surface of the first insulating layer;
Step 4: forming a second insulating layer on third surfaces of the first trench and the second trench;
Step 5: forming a single crystal nucleation layer on a second surface of the first trench, formed by a third surface of the substrate, and forming a single crystal nucleation layer on a first surface of the second trench, formed by the second surface of the substrate; and
Step 6: making a first semiconductor layer grown epitaxially laterally, with the single crystal nucleation layer as a nucleation center.
Optionally, herein, the second surface and the third surface of the substrate are of a hexagonal symmetrical lattice structure.
Optionally, herein, the second surface and the third surface of the substrate are selected from the group consisting of Si (111) plane, Al2O3 (0001) plane, SiC (0001) plane, SiC (000-1) plane, GaN (0001) plane and GaN (000-1) plane.
Optionally, herein, in Step 5, a single crystal nucleation layer is formed on a part of a second surface of the first trench or the first step structure, formed by a third surface of the substrate, and a single crystal nucleation layer is formed on a part of a first surface of the second trench or the second step structure, formed by the second surface of the substrate.
Optionally, herein, the Step 5 can be replaced with Step 5′, and in the Step 5′, with the single crystal nucleation layer as a nucleation center, a first sub-layer of a first semiconductor layer is epitaxially laterally grown in the trenches, and then a doped third semiconductor layer is grown with the first sub-layer as a core, and then further a second sub-layer of the first semiconductor layer is grown, wherein the third semiconductor layer is N-type doped or P-type doped.
Optionally, herein, in the Step 5, before growing the first semiconductor layer, a buffer layer is deposited on the nucleation layer.
Optionally, herein, after the first and second trenches or the first and second step structures are formed, it further comprises forming a sacrificial layer through coplanar deposition, wherein the sacrificial layer and the first insulating layer have the high etching selection ratio, and then retaining, through the dry etching, the sacrificial layer on the first surface and the second surface of the first trench and the second trench.
Optionally, herein, a second insulating layer is formed on the third surface of the first and second trenches or the first and second step structures by using the sacrificial layer, and then the sacrificial layer is removed.
Optionally, a fourth insulating layer is respectively formed on the first surface and the second surface of the first and second trenches or the first and second step structures.
Optionally, the first insulating layer at the portion between the first and second trenches or the first and second step structures is exposed by a photolithography pattern, and the etching is performed to remove the exposed fourth insulating layer on the second surface of the first trench or the first step structure and on the first surface of the second trench or the second step structure, thereby exposing the third surface of the substrate in the first trench and the second surface of the substrate in the second trench.
Optionally, herein, after the formation of the single crystal nucleation layer, the nucleation layers on all the insulating layers need to be separately removed; or during the formation of the nucleation layer, the nucleation layer grows merely on the substrate but not on any of the insulating layers, by means of introducing gas containing chlorine.
Optionally, herein, the growth of the first semiconductor layer comprises growth in a direction perpendicular to the first surface of the substrate, wherein when the growth of the first semiconductor layer in a direction perpendicular to the first surface of the substrate exceeds the height of the trench or the step structure, the excess part of the first semiconductor layer is removed by planarization or etching technology.
Optionally, herein, the growth of the first sub-layer and the second sub-layer of the first semiconductor layer and the growth of the third semiconductor layer comprise the growth in a direction perpendicular to the first surface of the substrate, wherein when the growth of the first sub-layer and the second sub-layer of the first semiconductor layer and the third semiconductor layer in the direction perpendicular to the first surface of the substrate exceeds the height of the trench or the step structure, the excess part is removed through the planarization or the etching technique or the excess part is retained.
Optionally, a photolithography pattern is formed to expose a region between the first trench and the second trench which are adjacent, and the first insulating layer and a part of the substrate in the region are etched, exposing the first face of the first semiconductor layer having the spontaneous and piezoelectric polarization effect and the second surface opposite to the first face, with the second face having the spontaneous and piezoelectric polarization effect.
Optionally, a photolithography pattern is formed to expose a part of the region between the first trench and the second trench which are adjacent, and to expose a first face or a second face of the first semiconductor layer, having spontaneous and piezoelectric polarization effect; the first insulating layer in the region, a part of the substrate, and the exposed first face or second face of the first semiconductor layer are etched, exposing the second face or the first surface opposite thereto of the first semiconductor layer.
Optionally, a photolithography pattern is formed to expose a part of the region between the first trench and the second trench which are adjacent, and the first insulating layer and a part of the substrate are etched to expose a first face or a second face of the first semiconductor layer, which have spontaneous and piezoelectric polarization effect, and the second surface or the first surface opposite thereto is still covered by the substrate and the first insulating layer.
Optionally, a third insulating layer is formed on the substrate having been subjected to the etching, and then the third insulating layer on the first semiconductor layer is removed.
Optionally, a second semiconductor layer is formed on the exposed first semiconductor layer, so that two-dimensional electron gas is formed at the interface of the first face of the first semiconductor layer adjacent to the second semiconductor layer, and/or two-dimensional hole gas is formed at the interface of the second face of the first semiconductor layer adjacent to the second semiconductor layer.
Optionally, a plurality of stacks, which are composed of the first semiconductor layers and the second semiconductor layers alternately, are continuously formed on the second semiconductor layer.
Optionally, a dielectric layer is deposited, the dielectric layer is lithographically etched, and then metal is deposited, so as to form, along the length direction of the trench on the first face or the second face of the first semiconductor layer, a first electrode, a second electrode, and a third electrode, wherein the second electrode is in contact with the second semiconductor layer, and the first electrode and the third electrode are in contact with the second semiconductor layer or the first semiconductor layer.
Optionally, a fourth electrode is formed on the second face or the first face of the first semiconductor layer opposite to the first electrode, the second electrode, and the third electrode, and is connected with the third semiconductor layer.
Optionally, herein, the nucleation layer is formed at a position corresponding to the first electrode, or a position corresponding to the third electrode, or provided at a position corresponding to a portion between the second electrode and the third electrode.
Optionally, herein, when the nucleation layer is disposed at a position corresponding to the third electrode, a current blocking layer may also be formed in a direction perpendicular to the first face or the second face of the trenches.
Optionally, herein, corresponding doping is performed in the region corresponding to the first electrode and the region corresponding to the third electrode, of the first semiconductor layer, to form the corresponding first electrode region and third electrode region.
Optionally, herein, when the HEMT device is formed, the doping of the first electrode region and the third electrode region is N-type doping; and when the HHMT device is formed, the doping of the first electrode region and the third electrode region is P-type doping.
Optionally, herein, the doping of the first electrode region and the third electrode region and the doping of the third semiconductor layer are performed simultaneously, or the doping of the first electrode region, the doping of the third electrode region and the doping of the third semiconductor layer are performed sequentially.
According to one aspect of the present disclosure, a semiconductor device is provided, comprising:
Optionally, herein, the single crystal nucleation layer is formed on a part of the second surface of the first trench, and the single crystal nucleation layer is formed on a part of the first surface of the second trench.
Optionally, herein, the first semiconductor layer is divided into a first sub-layer and a second sub-layer of the first semiconductor layer along the length direction of the trench, and a doped third semiconductor layer is also arranged between the first sub-layer and the second sub-layer.
Optionally, herein, the second surface and the third surface of the substrate are of a hexagonal symmetrical lattice structure.
Optionally, herein, the second surface and the third surface of the substrate are selected from Si (111) plane, Al2O3 (0001) plane, SiC (0001) plane, SiC (000-1) plane, GaN (0001) plane or GaN (000-1) plane.
Optionally, a second insulating layer is formed on the third surfaces of the first and second trenches.
Optionally, a fourth insulating layer is respectively formed on the first surface of the first trench and the second surface of the second trench.
Optionally, herein, the first semiconductor layer is flush with the first insulating layer, or the first semiconductor layer has a portion protruding from the first insulating layer.
Optionally, herein, the first insulating layer, the second insulating layer and the fourth insulating layer are silicon dioxide layers.
According to one aspect of the present disclosure, a semiconductor device is provided, comprising:
According to one aspect of the present disclosure, there is provided:
According to one aspect of the present disclosure, there is provided:
According to one aspect of the present disclosure, there is provided:
Optionally, herein, the first semiconductor layer is divided into a first sub-layer of the first semiconductor layer and a second sub-layer of the second semiconductor layer along the length direction of the trenches; and a third semiconductor layer is also arranged between the first sub-layer and the second sub-layer.
Optionally, herein, the first surface and the second surface of the trenches are of a hexagonal symmetrical lattice structure.
Optionally, the second surface and the third surface of the substrate are selected from Si (111) plane, Al2O3 (0001) plane, SiC (0001) plane, SiC (000-1) plane, GaN (0001) plane or GaN (000-1) plane.
Optionally, herein, the third semiconductor layer is a P-type buried layer or an N-type buried layer.
Optionally, herein, a first electrode, a second electrode, and a third electrode are respectively formed on the third insulating layer, at the first face/second face of the first semiconductor layer along the length direction of the trenches, wherein the first electrode, the second electrode and the third electrode are respectively connected to the second semiconductor layer; or the first electrode and the third electrode are connected to the first semiconductor layer, and the second electrode is connected to the second semiconductor layer.
Optionally, herein, the projection of the third semiconductor layer onto the first face/second face of the first semiconductor layer is within the range of the projection of the second electrode onto the first face/second face of the first semiconductor layer, or partially overlaps with it.
Optionally, herein, the first electrode, the second electrode and the third electrode are separated from each other by a dielectric layer.
Optionally, herein, at the first face/second face opposite to the second face/first face of the first semiconductor layer where the first electrode, the second electrode, and the third electrode are located, a fourth electrode is formed on the third insulating layer, and the fourth electrode is connected to the third semiconductor layer.
Optionally, herein, the doping concentration of the third semiconductor layer is sufficient to deplete 95%-100% of the two-dimensional electron gas/two-dimensional hole gas in at least a part of the region overlapping the projection region of the second electrode, without the device bias.
Optionally, herein, the nucleation layer is formed at a position corresponding to the first electrode, or a position corresponding to the third electrode, or provided at a position corresponding to a portion between the second electrode and the third electrode.
Optionally, herein, when the nucleation layer is disposed at a position corresponding to the third electrode, a current blocking layer is formed in a direction perpendicular to the first face or the second face of the trenches.
Optionally, herein, the region corresponding to the first electrode and the region corresponding to the third electrode, of the first semiconductor layer, have the corresponding doping, so as to form the corresponding first electrode region and third electrode region.
Optionally, herein, when the HEMT device is formed, the doping of the first electrode region and the third electrode region is N-type doping; and when the HHMT device is formed, the doping of the first electrode region and the third electrode region is P-type doping.
According to another aspect of the present disclosure, an electronic device is provided.
Optionally, the electronic device is a power supply device, a mobile phone, or a power amplifier in a communication system.
Hereinafter, the specific content of the present disclosure will be described with reference to the drawings, which will help to more easily understand the purposes, features, and advantages of the present disclosure. The drawings are only to illustrate the principles of the present disclosure. In the drawings, it is not necessary to draw the size and relative positions of the units according to scale. In the attached drawings:
Hereinafter, an exemplary disclosure of the present disclosure will be described with reference to the drawings. For the sake of clarity and conciseness, not all the features that realize the present disclosure are described in the specification. However, it should be understood that in the process of implementing the present disclosure, many ways to implement the present disclosure can be made in order to achieve the specific goals of the inventor, and these ways may be modified based on the present disclosure.
Here, it should also be noted that, in order to avoid the present disclosure from becoming complicated due to unnecessary details, only the device structures closely related to the technical solution according to the present disclosure are shown in the drawings, with some details omitted.
As understood, it will not happen that the present disclosure is limited to the described implementation forms due to the following description with reference to the drawings. Herein, where feasible, features may be substituted or combined between different embodiments, or one or more features may be omitted in one embodiment.
Specifically, the semiconductor device of the present disclosure is a compound semiconductor device containing a nitride semiconductor material, also referred to as a nitride semiconductor device, wherein the nitride semiconductor device is a group III nitride semiconductor device. Further, the group III nitride semiconductor device comprises a transistor using Wurtzite group III nitride semiconductor material. Furthermore, the transistor is a GaN transistor containing a GaN semiconductor material. In particular, the GaN transistor is a normally-off GaN-HEMT and/or GaN-HHMT.
A semiconductor device and a manufacturing method thereof according to an embodiment will be described with reference to
As shown in
Exemplarily, a silicon substrate of (110) or (112) plane may be used as the single crystal silicon substrate. As shown in
Due to the limitation of the trench 102, the first semiconductor layer can grow very straight during the lateral epitaxial growth, and further, the vertical surface of the semiconductor device, which is formed with the first semiconductor layer as a functional layer, can be formed very straight with the help of the trench. Therefore, it is easy to achieve a higher aspect ratio. More specifically, when the first semiconductor layer 201 is used as a vertical channel, the higher channel density per unit area can be achieved, thereby reducing the resistance of the device and improving the performance of the device.
The manufacturing method for manufacturing the semiconductor device will now be described in detail with reference to
Step 1: as shown in
Step 2: as shown in
Step 3: as shown in
Step 4: as shown in
Step 5: as shown in
Step 6: as shown in
Step 7: as shown in
Step 8: as shown in
Step 9: as shown in
Step 10: as shown in
It is understandable that if other substrates, such as Al2O3, are used, the nucleation layer may also be GaN. At this time, it is easier to achieve, through process adjustment, that the nucleation is only on the exposed substrate surface.
Step 11: as shown in
It can be understood that, before the growth of the first semiconductor layer, a buffer layer can also be formed first by deposition.
Optionally, the structure of the first trench and the second trench can also be replaced with the corresponding first step structure and second step structure, and then a nucleation layer is formed on a sidewall of each step structure, and an insulating layer is formed on the first surface of the substrate and the third surface of the step parallel to the first surface of the substrate, and then the corresponding buffer layer and the first semiconductor layer 201 epitaxially grow, with the nucleation layer as the core, for which the previous manufacturing method may be referred to, which will not be repeated.
An optional semiconductor device and a manufacturing method are described with reference to
On the basis of the foregoing content, the first insulating layer 101 outside the first semiconductor layer and the substrate 100 are etched, and the first insulating layer 101 and a part of the substrate 100 are removed, so that the first semiconductor layer 201 protrudes from the fourth surface 1004 of the substrate 100 after etching. The first semiconductor layer 201 has the first face 2013 with spontaneous polarization effect and piezoelectric polarization effect and the second face 2014 with spontaneous polarization effect and piezoelectric polarization effect, opposite to the first face. When the first semiconductor layer is GaN, the first face 2013 is the (0001) face, and the second face 2014 is the (000-1) face. A third insulating layer 107 is formed on the substrate 100 after etching, to isolate the exposed silicon substrate. Exemplarily, the third insulating layer may be a silicon dioxide layer. Then a second semiconductor layer 202 is formed in a way of covering the first semiconductor layer 201. The second semiconductor layer may be an AIN layer or an AlGaN layer, and then two-dimensional electron gas 2DEG and two-dimensional hole gas 2DHG are formed respectively on the first face 2013 and the second face 2014 of the first semiconductor layer.
Then, a first electrode 401, a second electrode 402, and a third electrode 403 are respectively formed on the second semiconductor layer 202, in a direction along the length of the trench. Optionally, the first electrode is a source, the second electrode is a gate, and the third electrode is a drain. The first electrode and the third electrode may also be formed on the first semiconductor layer 201 along the transmission direction of the two-dimensional electron gas.
Herein, the first electrode to the third electrode are all formed on the surface of the third insulating layer of the substrate 100, so that while the structure of the semiconductor device has a vertical channel, the arrangement of the electrodes is particularly suitable for the planarization process, which is beneficial to improve the integration density of semiconductor devices.
The manufacturing method for manufacturing the semiconductor device is exemplarily described below. The above-mentioned manufacturing method may further comprise the following steps.
Step 12: as shown in
Step 13: as shown in
Step 14: as shown in
It is understandable that a plurality of stack structures, which are composed of the first semiconductor layers and the second semiconductor layers alternately, can be continuously formed, covering on the second semiconductor layer, so as to further form a plurality of multi-channel structures composed of two-dimensional electron gas 2DEG and two-dimensional hole gas 2DHG.
Step 15: As shown in
An optional semiconductor device and a manufacturing method thereof are described with reference to
Optionally, a first sub-layer 2011 of a first semiconductor, a third semiconductor 203 and a second sub-layer 2012 of the first semiconductor are formed in the trench along the direction of the first surface and the second surface of the channel. The first sub-layer, the third semiconductor 203 and the second sub-layer completely fill the trench, so that the layers are each parallel to the first surface of the first semiconductor and coplanar with each other. It can be understood that the third semiconductor layer has P-type doping or N-type doping. Exemplarily, the P-type doping is P-type GaN, and the N-type doping is N-type GaN. Exemplarily, the doping concentration is 1E17−5E19/cm3, more preferably 1E+18/cm3−5E+19/cm3. The P-type GaN layer can deplete the two-dimensional electron gas on the first face of the first semiconductor layer; and the N-type GaN layer can deplete the two-dimensional hole gas on the second face of the first semiconductor layer, so that the device has a normally-off state. The selection of P-type doping or N-type doping depends on the specific type of subsequent devices. For HEMT devices, P-type doping is selected, and for HHMT devices, N-type doping is selected. It is understandable that the doping can be gradual (gradually varied). The rest of the structural features are the same as the above-mentioned embodiments, and will not be repeated here. The projection of the third semiconductor onto the first face of the first semiconductor is within the range of the projection of the second electrode in this direction, or partially overlaps with projection of the second electrode in this direction. The parameters of the third semiconductor layer, such as the doping concentration and size, can be set according to the device parameters, as long as it can deplete 95%-100% of the two-dimensional electron gas or two-dimensional hole gas, wherein along with the concentration of two-dimensional charge carrier gas being higher, the corresponding doping concentration can be increased accordingly.
The manufacturing method for the optional semiconductor device is specifically described below.
Step 11′: as shown in
Then, with the third semiconductor layer 203 as the core, the second sub-layer 2012 of the first semiconductor layer is continued to grow. The second sub-layer of the first semiconductor layer may also be an intrinsic GaN layer or an unintentionally doped GaN layer. The growth direction of the second sub-layer 2012 of the first semiconductor layer is the same as the growth direction of the first sub-layer or the third semiconductor layer. Finally, the parts of the first sub-layer, the third semiconductor, and the second sub-layer that grow perpendicular to the third surface of the trench and are located outside the trench are removed by planarization or etching technique, so that the first sub-layer, the third semiconductor layer and the second sub-layer are all located in the trench, forming a coplanar structure. The coplanar structure can make the device in a constrained state during the formation process, which is conducive to the formation of a specific structure and size, helps to form a device with a higher aspect ratio, and provides a means for achieving a device with higher aspect ratio, in addition to the adjustment of growth process parameters, wherein since the growth of the first semiconductor and the third semiconductor in the trench is restricted by the first surface and the second surface of the trench, during the growth process of the first semiconductor layer and the third semiconductor, the situation, where it cannot be kept completely vertical or the growth surfaces are not on the same plane, is avoided, as well as the situation, where multiple complicated growth surfaces may appear, is avoided, which facilitates the control on the device and achieves the improvement of the electrical performance.
Of course, it can be understood that part of the first sub-layer, the third semiconductor layer and the second sub-layer may also be made to be located outside the trench.
An optional semiconductor device and a manufacturing method thereof will be described with reference to
Optionally, on the basis of the foregoing content, a fourth electrode 404 is formed on the face of the first semiconductor layer 201 in the transmission direction of the two-dimensional hole gas, that is, in the direction facing away from the transmission direction of the two-dimensional electron gas. The fourth electrode is a body electrode for contacting with the third semiconductor layer 203, so as to better control the threshold voltage. It can be understood that the fourth electrode can also be formed on the fourth surface of the substrate. The position and forming method of the fourth electrode are not specifically limited here, as long as it can contact with the third semiconductor.
Optionally, one side of the first semiconductor layer is etched to remove the first insulating layer 101 and a part of the substrate 100 so that the substrate has a first surface and a fifth surface that is lower than and parallel to the first surface. The first face 2013 of the first semiconductor layer 201 having the spontaneous polarization effect and the piezoelectric polarization effect is exposed. When the first semiconductor layer is GaN, the first face 2013 is the (0001) face. At this time, the second face 2014 opposite to the first face 2013, with spontaneous polarization effect and piezoelectric polarization effect, is still covered by the substrate and the first insulating layer, and the second face 2014 is the (000-1) face of GaN. A third insulating layer 107 is formed on the substrate 100 after etching, to isolate the exposed silicon substrate. Exemplarily, the third insulating layer may be a silicon dioxide layer. Then a second semiconductor layer 202 is formed on the first face 2013 of the first semiconductor layer 201. The second semiconductor layer is an AIN layer or an AlGaN layer, thereby forming a two-dimensional electron gas 2DEG on the first face 2013 of the first semiconductor layer. It can be understood that the first semiconductor layer and the second layer may form a plurality of alternate stack structures, to form a HEMT device with a plurality of multi-channel structures of two-dimensional electron gas 2DEG.
The manufacturing method for manufacturing the semiconductor device will now be exemplarily described with reference to
Step 12′, as shown in
Step 13′, as shown in
Step 14′, as shown in
Optionally, only one side of the first semiconductor layer is etched to remove the first insulating layer 101 and part of the substrate 100, so that the substrate has a first surface and a sixth surface that is lower than and parallel to the first surface. The second face 2014 having the spontaneous polarization effect and the piezoelectric polarization effect, of the first semiconductor layer 201, is exposed. When the first semiconductor layer is GaN, the second face 2014 is the (000-1) face. At this time, the first face 2013 with spontaneous polarization effect and piezoelectric polarization effect, opposite to the second face 2014, is still covered by the substrate and the first insulating layer, and the first face 2013 is the (0001) face of GaN. A third insulating layer 107 is formed on the substrate 100 after etching, to isolate the exposed silicon substrate. Exemplarily, the third insulating layer may be a silicon dioxide layer formed by oxidation. Then, a second semiconductor layer 202 is formed to cover the second face 2014 of the first semiconductor layer 201. The second semiconductor layer is an AlN layer or an AlGaN layer, thereby forming two-dimensional hole gas 2DHG on the second face 2014 of the first semiconductor layer. It can be understood that the first semiconductor layer and the second semiconductor layer may form a plurality of alternate stack structures, thereby forming an HHMT device with a plurality of channel structures of two-dimensional hole gas 2DHG.
The manufacturing method for manufacturing the semiconductor device will now be exemplarily described with reference to
Step 12′, as shown in
Step 13′, as shown in
Step 14′, as shown in
It is understandable that, in some embodiments, the manner of forming the photolithographic pattern may be changed. All the regions between adjacent first trenches and second trenches are exposed from above, and the first insulating layer 101 and a part of the substrate 100 in these regions are etched, so that the first semiconductor layer covered by the fourth insulating layer, in the trench 102, protrudes from the fourth surface of the substrate after etching, and then only the region on the side of the first face/the second face of the first semiconductor layer is further etched to expose the fifth surface or the sixth surface of the substrate, the specific method of which may be obtained by referring to the foregoing content, which will not be repeated here.
Optionally, the position where the single crystal nucleation layer is located corresponds to the position where the third electrode (drain) of the subsequent device is formed. At this time, in order to avoid problems of, such as, poor crystal quality and large leakage current in the nucleation region, a current blocking layer may be added onto the single crystal nucleation layer. The current blocking layer, for example, may be heavily doped with C or Fe elements, and the doping range of C or Fe may be 1E17−1E20/cm3.
Optionally, the position of the single crystal nucleation layer may also be arranged in the region between the second electrode and the third electrode. Exemplarily, the above technical problems can be overcome by separating, by a certain distance, the position where the nucleation layer is located, from the position where the subsequent drain electrode region is located.
Optionally, for the region where the single crystal nucleation layer is provided, the regions of the corresponding first and second trenches may be exposed by photolithography.
The current blocking layer can be formed by performing corresponding doping during epitaxial growth with a single crystal nucleation layer as the core.
Optionally, doping is performed in the first electrode region (source region) and the third electrode region (drain region) to reduce the contact resistance. It is understandable that when forming HEMT devices, the doping type of the source and drain regions is N-type; and when forming HHMT devices, the doping type of the source and drain regions is P-type .
Optionally, in the HEMT device, the second semiconductor layer can be removed so that the first electrode and/or the third electrode are in physical contact with the first semiconductor layer, and form an ohmic contact with the two-dimensional electron carrier gas (2DEG). Due to the existence of the doped first electrode region and third electrode region, such direct physical contact with the first semiconductor layer is more conducive to reducing the ohmic contact resistance, through the design of the process and the structure.
Optionally, in the HHMT device, since the P-type ohmic contact is more difficult to be formed, when the second semiconductor layer is removed so as to make the first electrode (and/or the third electrode) in physical contact with the first semiconductor layer and form an ohmic contact with the two-dimensional hole carrier gas (2DHG), due to the existence of the doped first electrode and third electrode regions, through the design of the process and structure, this method of being the direct physical contact with the first semiconductor layer is more conducive to reducing ohmic contact resistance.
The manufacturing method for manufacturing the semiconductor device will now be exemplarily described with reference to
The doping of the source region and the drain region are illustrated, with the example where the nucleation layer corresponds to the source region. The case where the nucleation layer corresponds to the drain region, or the case where the nucleation layer is located between the gate region and the drain region is similar to the case where the nucleation layer corresponds to the source region, which will not be repeated here. As shown in
Optionally, during the growth process of the first semiconductor layer 201 with the nucleation layer as the core, before the corresponding doping, the intrinsic (undoped) first semiconductor layer, or unintentionally doped first semiconductor layer grows, and then the doped source region grows.
Next, as shown in
Then, as shown in
It is understandable that, herein, the doping of the drain region and the source region may be performed simultaneously with the doping of the third semiconductor layer, or the doping of the drain region, the doping of the source region, and the doping of the third semiconductor layer may be carried out successively.
A power supply device comprises any one of the above-mentioned semiconductor devices. The power supply device comprises a primary circuit, a secondary circuit, transformer, etc., wherein both the primary circuit and the secondary circuit have a switching element, wherein the switching element uses any one of the above-mentioned semiconductor devices.
A mobile phone comprises any one of the above-mentioned semiconductor devices. The mobile phone comprises a display screen, a charging unit, etc., wherein the charging unit comprises any one of the above-mentioned semiconductor devices.
An amplifier is provided, with the amplifier being a power amplifier capable of being in the fields of mobile phone base stations, optical communication systems, and the like. The power amplifier can comprise any one of the above-mentioned semiconductor devices.
The technical solutions of the present disclosure can at least help to achieve one of the following effects that: the semiconductor device can reduce the gate leakage current, has high threshold voltage, high power, and high reliability, and achieve the low on-resistance and the normally-off state of devices, and provide a stable threshold voltage, so that the semiconductor device has good switching characteristics.
The technical solutions of the present disclosure can also help to achieve one of the following effects that: it is easy to achieve a higher aspect ratio; it can achieve a higher channel density per unit area; it is suitable for a planarization process and beneficial to increase the integration density of semiconductor devices; and the structure and preparation process of the semiconductor devices are relatively simple, which can effectively reduce the production cost.
The present disclosure has been described above in conjunction with embodiments, but it should be clear for those skilled in the art that these descriptions are exemplary and do not limit the scope of protection of the present disclosure. Those skilled in the art can make various variations and modifications to the present disclosure according to the spirit and principle of the present disclosure, and these variations and modifications are also within the scope of the present disclosure.
The present disclosure provides a novel semiconductor device structure and manufacturing method thereof, which has simple process, low cost, and higher aspect ratio, and can achieve the higher channel density per unit area, and an energy-saving semiconductor device with high performances, such as high withstand voltage, high power, low on-resistance, etc.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202010149409.5 | Mar 2020 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/078736 | 3/2/2021 | WO |
