This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2019-80975, filed on Apr. 22, 2019, the entire contents of which are incorporated herein by reference.
The embodiments discussed herein are related to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device.
As a semiconductor device using a nitride semiconductor, a light emitting diode (LED) using a gallium nitride (GaN)-based semiconductor is known, for example. Regarding such an LED, a technique of growing an n-type contact layer on a substrate having a recessed portion with the depth of 0.1 μm or more, and sequentially growing an active layer having a quantum well structure and a p-type contact layer on the n-type contact layer is known, for example. In addition, a technique of growing a first semiconductor layer on a wafer having an uneven structure having substantially an n-fold symmetrical array, and sequentially growing a light emitting semiconductor layer and a second semiconductor layer on the first semiconductor layer is known.
Furthermore, as a semiconductor device using a nitride semiconductor, a high electron mobility transistor (HEMT) provided with a barrier layer on a channel layer is known. Regarding such a HEMT, a quantum confinement structure-type HEMT is known, which is provided with a channel layer such as GaN on a first barrier layer such as aluminum nitride (AlN) and provided with a second barrier layer such as AlN on the channel layer, for example.
For example, Japanese Laid-open Patent Publication No. 2007-36174, International Publication Pamphlet No. 2014/192821, and US Patent Application Publication No. 2006/0244011 are disclosed as related arts.
According to an aspect of the embodiments, A semiconductor device includes a substrate that contains a first nitride semiconductor, an uneven layer that is provided on the substrate, contains a second nitride semiconductor, and has unevenness in a surface, a channel layer that is provided on the uneven layer and contains a third nitride semiconductor, a barrier layer that is provided on the channel layer and contains a fourth nitride semiconductor, wherein, in the uneven layer, an area of a portion that falls within a range within a mode value±1 nm of a position of the surface in a height direction falls within a range of 46% to 75% with respect to an area of the entire surface.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.
In a semiconductor device such as a HEMT adopting a quantum confinement structure of a nitride semiconductor, there are some cases where confinement of electrons is weakened in the quantum confinement structure obtained by providing a barrier layer of the upper layer on a channel layer, when surface flatness of the channel layer provided on an underlying barrier layer becomes low. When the surface flatness of the channel layer becomes low and the confinement of electrons is weakened due to the low flatness, as described above, characteristics of the semiconductor device adopting the quantum confinement structure of a nitride semiconductor may not be able to be sufficiently improved.
In one aspect, an object of the embodiments is to implement a semiconductor device using a nitride semiconductor and having excellent characteristics.
In the one aspect, according to the embodiments, a semiconductor device using a nitride semiconductor and having excellent characteristics can be implemented.
First, an example of a semiconductor device using a nitride semiconductor will be described.
A semiconductor device 100 illustrated in
In the semiconductor device 100, a nitride semiconductor having a larger band gap than the nitride semiconductor of the channel layer 102 is used for the substrate 101 and the barrier layer 103. For example, AlN (band gap 6.2 eV) is used for the substrate 101 and the barrier layer 103, and GaN (band gap 3.4 eV) is used for the channel layer 102, as described above. Such a nitride semiconductor is used, and the substrate 101 and the barrier layer 103 are hetero-joined to the channel layer 102. In this case, as illustrated in
The stacked structure of the substrate 101, the channel layer 102, and the barrier layer 103 that can obtain an electron confinement effect is also called a quantum confinement structure. The above-described quantum confinement structure using a nitride semiconductor is also referred to as an AlN/GaN/AlN quantum confinement structure or the like. The semiconductor device 100 implements a low leakage current and high carrier mobility by adopting the above-described quantum confinement structure.
Formation of the semiconductor device 100 adopting the quantum confinement structure includes the following steps as illustrated in
The channel layer 102, for example, GaN is grown on the substrate 101, for example, AlN, as illustrated in
In this case, there is a relatively large lattice constant difference (about 2.6%) between AlN of the substrate 101 and GaN of the channel layer 102 grown on the substrate 101. When GaN of the channel layer 102 is directly grown on AlN of the substrate 101, a growth mode becomes Volmer-Weber mode due to the relatively large lattice constant difference between AlN of the substrate 101 and GaN of the channel layer 102, and, as illustrated in
When AlN of the barrier layer 103 is further grown on GaN of the channel layer 102 having low surface flatness to form the quantum confinement structure, a sufficient confinement effect may not be able to be obtained due to a defective heterojunction interface. In this case, the semiconductor device 100 may not be able to function as a high-performance HEMT in which a low leakage current and high carrier mobility are realized by the quantum confinement structure using a nitride semiconductor.
In view of the above points, here, a configuration to be exemplified is adopted as an embodiment, and a semiconductor device using a nitride semiconductor and excellent characteristics is implemented.
A semiconductor device 10A illustrated in
A predetermined nitride semiconductor, that is, for example, a nitride semiconductor functioning as a barrier layer on a lower side of the quantum confinement structure 30 or a nitride semiconductor on which the uneven layer 20 functioning as the barrier layer on the lower side of the quantum confinement structure 30 is formable (epitaxially growable), is used for at least a surface of the substrate 11. AlN is used for the nitride semiconductor of the substrate 11, for example. A nitride semiconductor that is a different type from the predetermined nitride semiconductor may be further used for the substrate 11 as long as the predetermined nitride semiconductor is provided for the surface. The substrate 11 is a substrate provided with a nitride semiconductor layer functioning as a nucleation layer or a buffer layer on a nitride semiconductor substrate or a predetermined substrate (not necessarily a nitride semiconductor). The substrate 11 may have a single-layer structure of one type of nitride semiconductor, or a stacked structure of one or more types of nitride semiconductors. An undoped nitride semiconductor is used for the substrate 11, for example.
The uneven layer 20 is provided on the substrate 11. A nitride semiconductor is used for the uneven layer 20. AlN is used for the nitride semiconductor of the uneven layer 20, for example. An undoped nitride semiconductor is used for the uneven layer 20, for example. For example, the uneven layer 20 is formed on the substrate 11, using an MOVPE method. The uneven layer 20 includes a terrace portion, a recessed portion depressed from the terrace portion, and a protruding portion protruding from the terrace portion on the surface (the surface where the channel layer 12 is provided). Details of the uneven layer 20 will be described below.
The channel layer 12 is provided on the uneven layer 20. A nitride semiconductor is used for the channel layer 12. GaN is used for the nitride semiconductor of the channel layer 12, for example. In addition, aluminum gallium nitride (AlGaN) or boron aluminum gallium nitride (BAlGaN) may be used for the nitride semiconductor of the channel layer 12. For example, BxAlyGa1-x-yN (0≤x<1, 0≤y<1, and 0≤x+y<1) can be used for the nitride semiconductor of the channel layer 12. The channel layer 12 may have a single-layer structure of one type of nitride semiconductor, or a stacked structure of one or more types of nitride semiconductors. An undoped nitride semiconductor is used for the channel layer 12, for example. For example, the channel layer 12 is formed on the uneven layer 20, using an MOVPE method. The channel layer 12 is also called an electron transit layer.
The barrier layer 13 is provided on the channel layer 12. A nitride semiconductor is used for the barrier layer 13. AlN is used for the nitride semiconductor of the barrier layer 13, for example. In addition, AlGaN may be used for the nitride semiconductor of the barrier layer 13. That is, for example, AlzGa1-zN (0<z≤1) can be used for the nitride semiconductor of the barrier layer 13. The barrier layer 13 may have a single-layer structure of one type of nitride semiconductor, or a stacked structure of one or more types of nitride semiconductors. An undoped nitride semiconductor is used for the barrier layer 13, for example. For example, the barrier layer 13 is formed on the channel layer 12, using an MOVPE method. The barrier layer 13 is also called an electron supply layer.
Here, nitride semiconductors having different band gaps are used for the channel layer 12 and the barrier layer 13 on the channel layer 12. By providing, on the channel layer 12, the barrier layer 13 using a nitride semiconductor having a larger band gap than the channel layer 12, a heterojunction structure having a band offset is formed. By setting a Fermi level to be higher than (on a higher energy side of) a conduction band at a junction interface between the channel layer 12 and the barrier layer 13, a 2DEG 14 is generated in the channel layer 12 at the junction interface. By providing, on the channel layer 12, the barrier layer 13 using a nitride semiconductor having a larger lattice constant than the channel layer 12, piezoelectric polarization is generated in the barrier layer 13. A high-concentration 2DEG 14 is generated in the channel layer 12 at the junction interface due to spontaneous polarization of the nitride semiconductor used for the barrier layer 13 and piezoelectric polarization generated due to the lattice constant of the nitride semiconductor. A combination of nitride semiconductors to generate the 2DEG 14 near the junction interface between the channel layer 12 and the barrier layer 13 is used for the channel layer 12 and the barrier layer 13.
Moreover, nitride semiconductors having different band gaps are used for the channel layer 12, and the uneven layer 20 or the uneven layer 20 and the substrate 11 below the channel layer 12. By providing, below the channel layer 12, the uneven layer 20 or the uneven layer 20 and the substrate 11 using a nitride semiconductor having a larger band gap than the channel layer 12, a heterojunction structure having a band offset is formed. The quantum confinement structure 30 is formed by the channel layer 12, the uneven layer 20 or the uneven layer 20 and substrate 11 on the lower side of the channel layer 12, and the barrier layer 13 on the upper side of the channel layer 12. In the quantum confinement structure 30, the channel layer 12 functions as a layer in which carrier electrons move, and the uneven layer 20 or the uneven layer 20 and the substrate 11 on the lower layer side and the barrier layer 13 on the upper layer side function as layers for confining carrier electrons in the channel layer 12. The quantum confinement structure 30 realizes a highly efficient and highly reliable HEMT in which diffusion of electrons as carriers to a deep portion is restricted and leakage from the channel layer 12 is suppressed. A combination of nitride semiconductors to form the quantum confinement structure 30 is used for the channel layer 12, and the uneven layer 20 or the uneven layer 20 and the substrate 11 below the channel layer 12.
The gate electrode 15 is provided on the barrier layer 13, for example. The gate electrode 15 functions as a Schottky electrode or a Schottky gate electrode. A metal is used for the gate electrode 15. For example, a metal electrode containing nickel (Ni) and gold (Au) on the nickel is provided as the gate electrode 15. The gate electrode 15 is formed using a vapor deposition method or the like.
Note that an insulating film such as an oxide, a nitride, or an oxynitride may be interposed between the gate electrode 15 and the barrier layer 13. Thereby, a metal insulator semiconductor (MIS) gate structure is implemented. A cap layer using a nitride semiconductor such as GaN or AlGaN may be interposed between the gate electrode 15 and the barrier layer 13.
Furthermore, a cap layer using a nitride semiconductor such as GaN or AlGaN containing p-type impurities or a cap layer using a nitride semiconductor such as indium gallium nitride (InGaN) may be interposed between the gate electrode 15 and the barrier layer 13. Thereby, the 2DEG 14 generated in the channel layer 12 is modulated to decrease the concentration below the gate electrode 15, and a normally-off HEMT is implemented.
The source electrode 16 and the drain electrode 17 are provided on the barrier layer 13 on both sides of the gate electrode 15, for example. The source electrode 16 and the drain electrode 17 are provided on the barrier layer 13 to function as ohmic electrodes. A metal is used for the source electrode 16 and the drain electrode 17. For example, metal electrodes containing tantalum (Ta) and aluminum (Al) on the tantalum are provided as the source electrode 16 and the drain electrode 17. The source electrode 16 and the drain electrode 17 are formed using a vapor deposition method or the like.
Note that the source electrode 16 and the drain electrode 17 may penetrate the barrier layer 13 and be directly connected with the channel layer 12 under the barrier layer 13, instead of being provided on the barrier layer 13. Alternatively, the source electrode 16 and the drain electrode 17 may penetrate the barrier layer 13 and be indirectly connected with the channel layer 12 via a contact layer using a nitride semiconductor such as GaN containing n-type impurities.
Formation of the semiconductor device 10A provided with the quantum confinement structure 30 as described above includes the following steps as illustrated in
First, as illustrated in
In the formation of the semiconductor device 10A, the uneven layer is first grown on the substrate 11, and the channel layer 12 is grown on the uneven layer 20, whereby the channel layer 12 with suppressed surface roughness and high flatness can be formed. In the formation of the semiconductor device 10A, to form the channel layer 12 with high flatness, an uneven shape of the uneven layer 20 to be grown on the substrate 11 is adjusted in advance before the formation of the channel layer 12.
Here, the uneven layer 20 will be described.
The uneven layer 20 includes a flat terrace portion 21, a recessed portion 22 depressed from the terrace portion 21, and a protruding portion 23 protruding from the terrace portion 21 on a surface 20a (a surface opposite to the substrate 11 side). In
The terrace portion 21 can include a terrace portion 21 having a relatively large area and a terrace portion 21 having a relatively small area. The recessed portion 22 can include a recessed portion 22 that is relatively shallow and a recessed portion 22 that is relatively deep in depth from the terrace portion 21. The protruding portion 23 may include a protruding portion 23 that is relatively low and a protruding portion 23 that is relatively high in height from the terrace portion 21. The uneven shape of the surface 20a of the uneven layer including the terrace portion 21, the recessed portion 22, and the protruding portion 23 is adjusted, and the flatness of the channel layer 12 grown on the uneven layer 20 is improved.
As Illustrated in
When the ratio S1/S of the area S1 to the area S is adjusted to be the predetermined ratio, side surfaces (an inner surface of the recessed portion 22 and an outer surface of a protruding portion 23) of a nitride semiconductor such as AlN used for the uneven layer 20 become present with adequate density on the surface 20a of the uneven layer 20. It is considered that growth nucleus groups of a nitride semiconductor such as GaN used for the channel layer 12 are formed on such side surfaces of the nitride semiconductor in addition to a flat surface (an upper surface of the terrace portion 21) on the surface 20a of the uneven layer 20. Then, it is considered that the nitride semiconductors grown from the large number of growth nucleus groups formed on the flat surface and side surfaces of the nitride semiconductors on the surface 20a of the uneven layer 20 are met, the height imbalance in a growth surface is reduced with the growth, and as a result, the channel layer 12 with high surface flatness can be obtained.
Meanwhile, in a case where the density of the side surfaces of the nitride semiconductor of the uneven layer 20, which is present in the surface 20a of the uneven layer 20, is too small (the area of the flat surface is too large), the density of the growth nucleus groups of the nitride semiconductors of the channel layer 12 becomes small. It is considered that the nitride semiconductors grown up to a certain size from a relatively small number of growth nucleus groups are met and the growth proceeds, and as a result, the channel layer 12 with large surface unevenness and low flatness is obtained. It can also be considered that a similar phenomenon to a case where the nitride semiconductor of the channel layer 12 is directly grown on a flat substrate 11 occurs.
Furthermore, in a case where the density of the side surfaces of the nitride semiconductors of the uneven layer 20, which are present in the surface 20a of the uneven layer 20, is too large (the area of the flat surface is too small), the height imbalance in the growth surface due to the nitride semiconductors grown from the growth nucleus groups of the nitride semiconductors of the channel layer 12 is less easily reduced. As a result, it is considered that the channel layer 12 with large surface unevenness and low flatness is obtained.
In a case where the density of the protruding portions 23 becomes large, the unevenness of the surface of the channel layer 12 obtained by the growth tends to become large. This is because the nitride semiconductor of the channel layer 12 tends to be abnormally grown from the growth nucleus formed on the protruding portion 23, and when the density of the protruding portions 23 becomes large, the unevenness of the surface of the obtained channel layer 12 tends to become large. Therefore, as illustrated in
Moreover, in a case where the density of the deep recessed portions 22 becomes large, the unevenness of the surface of the channel layer 12 obtained by the growth tends to become large. This is because the deep recessed portion 22 is not sufficiently buried with the nitride semiconductor of the channel layer 12 to be grown, and the nitride semiconductor of the channel layer 12 grown from the deep recessed portion 22 is more likely to remain depressed after growth than the nitride semiconductor grown from a shallower portion. Therefore, as illustrated in
The above-described position of the surface 20a of the uneven layer 20 in the height direction, that is, for example, the surface position z can be measured using a scanning probe microscope (SPM) such as a scanning tunneling microscope (STM) or an atomic force microscope (AFM). In addition, the surface position z can be measured using a laser displacement meter.
Table 1 illustrates an example of evaluation results obtained for the adjustment of the uneven shape of the underlying surface of the channel layer 12.
Table 1 illustrates an example of results of evaluating (determining pass or failure of) the surface flatness of a GaN layer corresponding to the channel layer 12 in a case where the GaN layer was grown under the same conditions for samples A, B, C, and D having different uneven shapes of a surface of an AlN substrate corresponding to the substrate 11.
From Table 1, the ratio S1/S of the area S1 of the portion falling within the range within the mode value±1 nm of the surface position of the surface of the AlN substrate in the height direction to the area S of the entire surface was 98.90% for the sample A, 75.20% for the sample B, 48.59% for the sample C, and 46.16% for the sample D. The ratio S2/S of the area S2 of the portion falling within the range of the mode value+1 nm or more of the surface position of the surface of the AlN substrate in the height direction to the area S of the entire surface was 0.01% for the sample A, 1.90% for the sample B, 18.92% for the sample C, and 2.57% for the sample D. The ratio S3/S of the area S3 of the portion falling within the range of the mode value−3 nm or less of the surface position of the surface of the AlN substrate in the height direction to the area S of the entire surface was 0.05% for the sample A, 2.74% for the sample B, 3.34% for the sample C, and 30.40% for the sample D.
When the GaN layer was grown on the AlN substrate of the samples A, B, C, and D, and the surface flatness of the GaN layer was evaluated, the sample A failed, the sample B passed, the sample C failed, and the sample D passed.
The sample A is a sample of a substrate in which the ratio S1/S of the area S1 of the portion falling within the range within the mode value±1 nm of the surface position of the surface of the AlN substrate in the height direction to the area S of the entire surface is significantly high, which can be considered to be almost flat. In the sample A having such high flatness, the surface flatness of the GaN layer grown on the substrate is low, and the sample A fails.
The ratio S1/S of the area S1 of the portion falling within the range within the mode value+1 nm of the surface position of the surface of the AlN substrate in the height direction to the area S of the entire surface can be set to fall within the range of 46 (46.16) % to 75 (75.20) % according to the results of the samples B and D that have passed.
Here, the sample C failed even if the ratio S1/S falls within the range of 46% to 75%. This is because the ratio S2/S of the area S2 of the portion falling within the range of the mode value+1 nm or more of the surface position of the surface of the AlN substrate in the height direction to the area S of the entire surface is higher than the other samples B, D, and the like, that is, for example, the surface has many relatively large protruding portions. From the above consideration, the ratio S2/S can be set to be less than 3 (2.57)% according to the results of the samples B and D that have passed. Note that the sample A is considered to fail because the ratio S1/S is high and the flatness is too high although the ratio S2/S is less than 3%.
Furthermore, the ratio S3/S of the area S3 of the portion falling within the range of the mode value−3 nm or less of the surface position of the surface of the AlN substrate in the height direction to the area S of the entire surface can be set to be less than 30 (30.40)% according to the results of the samples B and D that have passed. Note that, although the ratio S3/S is less than 30% in the samples A and C, the sample A is considered to fall because the ratio S1/S is high and the flatness is too high, and the sample C is considered to fail because the ratio S2/S is high and there are too many large protruding portions.
When the density of the AlN side surfaces is too small or too large, as illustrated in
The energy band structure of the substrate 11, the uneven layer 20, the channel layer 12, and the barrier layer 13 in the semiconductor device 10A having the above-described configuration is as illustrated in
The band offset between the uneven layer 20 (uneven AlN) and the channel layer 12 is smaller than a band offset between the substrate 11 (AlN) and the channel layer 12 in a case where the uneven layer 20 is not provided. However, carrier electrons (2DEG 14) gather near the junction interface between the upper barrier layer 13 (AlN) and the channel layer 12 due to an influence of polarization in the channel layer 12 (GaN). Therefore, it can be said that the influence of the band offset reduced by the uneven layer 20 on an electron confinement effect is small.
Note that a similar result is obtained in a case where AlGaN or BAlGaN is used for the channel layer 12, and in a case where AlGaN is used for the barrier layer 13.
As described above, in the semiconductor device 10A, the channel layer 12 is provided on the uneven layer 20 with an adjusted uneven shape, whereby the surface flatness is improved. The barrier layer 13 is provided on the channel layer 12 with such high surface flatness. Thereby, the quantum confinement structure 30 having a high electron confinement effect is implemented. The semiconductor device 10A provided with the quantum confinement structure 30, functioning as a HEMT having high carrier mobility and low leakage current, and having excellent characteristics is implemented.
Here, a first example of a semiconductor device having a configuration as described in the first embodiment and a method for forming the semiconductor device will be described.
First, as illustrated in
In growing each layer using the MOVPE method, tri-methyl-aluminum (TMAl) is used as an Al source. Tri-methyl-gallium (TMGa) is used as a gallium (Ga) source. Tri-ethyl boron (TEB), a diborane gas, or the like is used as a boron (B) source. A predetermined nitride semiconductor is grown using a mixed gas of one or more of the aforementioned gasses and ammonia (NH3) and further using hydrogen (H2) or nitrogen (N2) as a carrier gas. Supply and stop (switching) of TMAl, TMGa, and TEB, and a flow rate during supply (a mixing ratio with other materials) are appropriately set depending on the nitride semiconductor to be grown. A growth pressure is about 1 kPa to 100 kPa, and a growth temperature is about 700° C. to 1500° C.
Here, in the growth of AlN of the uneven layer 20, a condition is used in which a V/III ratio that is a molar ratio (supply ratio) of the NH3 gas and the TMAl gas supplied during the growth falls within a range of 22000 to 67000. Note that, to grow a flat layer, the V/III ratio is often set to several tens to several hundreds. In contrast, to the uneven layer 20, the condition of the significantly higher V/II ratio (22000 to 67000) is used.
By use of the condition of such a high V/III ratio, the uneven layer 20 with an adjusted uneven shape as described in the first embodiment is grown. That is, for example, the uneven shape of a surface 20a is adjusted such that a ratio S1/S of an area S1 of a portion falling within a range within a mode value M±1 nm of a surface position z of the surface 20a in a height direction to a surface S of the entire surface 20a falls within a range of 46% to 75%. Furthermore, the uneven shape of the surface 20a is adjusted such that a ratio S2/S of an area S2 of a portion falling within a range of a mode value M+1 nm or more of the surface position z of the surface 20a in the height direction to the surface S of the entire surface 20a becomes less than 3%. Furthermore, the uneven shape of the surface 20a is adjusted such that a ratio S3/S of an area S3 of a portion falling within a range of a mode value M−3 nm or less of the surface position z of the surface 20a in the height direction to the surface S of the entire surface 20a becomes less than 30%. By growing the channel layer 12 on the uneven layer 20 with an adjusted uneven shape of the surface 20a as described above, the channel layer 12 with high surface flatness can be obtained.
When the V/III ratio at the time of growing the uneven layer 20 falls below 22000, the surface 20a with high flat tends to be easily obtained. That is, for example, the possibility that the ratio S1/S exceeds 75% increases. When the V/III ratio at the time of growing the uneven layer 20 exceeds 67,000, a large protruding portion 23 and a deep recessed portion 22 tend to be easily obtained. That is, for example, the possibility that the ratio S2/S exceeds 3% or the possibility that the ratio S3/S exceeds 30% Increases.
After the growth of each layer, a resist having an opening in an element isolation region may be provided using a photolithography technique, and an element isolation region (not illustrated) may be formed by etching (such as dry etching using a chlorine-based gas) or on implantation.
Next, a resist having an opening in a region where a source electrode 16 and a drain electrode 17 are to be formed is provided using a photolithography technique, and etching is performed using a chlorine-based gas. Thereby, a part of the barrier layer 13 is removed, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, the gate electrode 15 is formed, as illustrated in
A semiconductor device 108 (
In the semiconductor device 108, the channel layer 12 is provided on the uneven layer 20 with an adjusted uneven shape, whereby the surface flatness is improved. Thereby, the quantum confinement structure 30 with an enhanced electron confinement effect is implemented. The semiconductor device 101 provided with the quantum confinement structure 30, functioning as a HEMT having high carrier mobility and low leakage current, and having excellent characteristics is implemented.
Note that the types and layer structures of the metals used for the gate electrode 15, the source electrode 16, and the drain electrode 17 of the semiconductor device 108 are not limited to the above examples, and the methods for forming the electrodes are also not limited to the above examples. Each of the gate electrode 15, the source electrode 16, and the drain electrode 17 may have a single-layer structure or a stacked structure. At the time of forming the source electrode 16 and the drain electrode 17, the above-described heat treatment may not be needed as long as ohmic connection is implemented by the formation of the electrode metal. At the time of forming the gate electrode 15, heat treatment may be further performed after the formation of the electrode metal. The structure of the gate electrode 15 is not limited to the above-described Schottky gate structure, and may be a MIS gate structure having an insulating film interposed between the gate electrode 15 and the barrier layer 13.
Here, a second example of a semiconductor device having a configuration as described in the first embodiment and a method for forming the semiconductor device will be described.
First, as illustrated in
Then, in this example, a cap layer 50, for example, a GaN cap layer 50 with the thickness of 2 nm is further grown on the barrier layer 13, as illustrated in
After the formation of the cap layer 50, an element isolation region (not illustrated) may be formed.
Next, a resist having an opening in a region where a source electrode 16 and a drain electrode 17 are to be formed is provided using a photolithography technique, and etching is performed using a chlorine-based gas. Thereby, each parts of the cap layer 50 and the barrier layer 13 are removed, as illustrated in
Next, as illustrated in
Next, the gate electrode 15 is formed, as illustrated in
A semiconductor device 10C (
In the semiconductor device 10C, the cap layer 50 is provided between the gate electrode 15 and the barrier layer 13, whereby generation of a gate leak current, diffusion of components of the gate electrode 15 into the barrier layer 13 and the channel layer 12, an increase in ON resistance, and the like are suppressed.
In the semiconductor device 10C, the channel layer 12 is provided on the uneven layer 20 with an adjusted uneven shape, whereby the surface flatness is improved. Thereby, the quantum confinement structure 30 with an enhanced electron confinement effect is implemented. The semiconductor device 10C provided with the quantum confinement structure 30, functioning as a HEMT having high carrier mobility and low leakage current, and having excellent characteristics is implemented.
Note that the types and layer structures of the metals used for the gate electrode 15, the source electrode 16, and the drain electrode 17 of the semiconductor device 10C are not limited to the above examples, and the methods for forming the electrodes are also not limited to the above examples. Each of the gate electrode 15, the source electrode 16, and the drain electrode 17 may have a single-layer structure or a stacked structure. At the time of forming the source electrode 16 and the drain electrode 17, the above-described heat treatment may not be needed as long as ohmic connection is implemented by the formation of the electrode metal. At the time of forming the gate electrode 15, heat treatment may be further performed after the formation of the electrode metal. The structure of the gate electrode 15 is not limited to the above-described Schottky gate structure, and may be a MIS gate structure having an insulating film interposed between the gate electrode 15 and the barrier layer 13.
Furthermore, the cap layer 50 may be selectively provided under the gate electrode 15, and a nitride semiconductor such as GaN or AlGaN containing p-type impurities or a nitride semiconductor such as InGaN may be used for the cap layer 50. By use of such a nitride semiconductor, a 2DEG 14 generated in the channel layer 12 due to fixed charges of the p-type nitride semiconductor and piezoelectric polarization generated in InGaN on the barrier layer 13 is modulated to decrease the concentration below the gate electrode 15. Thereby, the semiconductor device 10C functioning as a normally-off HEMT is implemented.
Here, a third example of a semiconductor device having a configuration as described in the first embodiment and a method for forming the semiconductor device will be described.
First, as illustrated in
Then, in this example, a surface protective film 60 is further formed on the barrier layer 13, using a plasma CVD method, an ALD method, a sputtering method, or the like, as illustrated in
Next, a resist having an opening in a region where a source electrode 16 and a drain electrode 17 are to be formed is provided using a photolithography technique, and each parts of the surface protective film 60, the barrier layer 13, and the channel layer 12 are removed by etching using a chlorine-based gas. Thereby, a state In which a groove 71 is formed as illustrated in
Next, as illustrated in
After the formation of the n-type contact layer 70, an element isolation region (not illustrated) may be formed.
Next, an electrode metal, that is, for example, a stacked body of Ta with the thickness of 20 nm and Al with the thickness of 200 nm is formed on the n-type contact layer 70, for example, on a region where the source electrode 16 and the drain electrode 17 are to be formed, using a photolithography technique, a deposition technique, and a lift-off technique. Thereafter, heat treatment is performed at 400° C. to 1000° C., for example, 550° C. in a nitrogen atmosphere, and the electrode metal is ohmic-connected. Thereby, as illustrated in
Next, as illustrated in
Next, the gate electrode 15 is formed, as illustrated In
A semiconductor device 10D (
The semiconductor device 10D is provided with the source electrode 16 and the drain electrode 17 on the n-type contact layer 70, whereby a contact resistance between the n-type contact layer 70, and the source electrode 16 and the drain electrode 17 is reduced. Thereby, low-resistance ohmic connection is implemented.
In the semiconductor device 10, the channel layer 12 is provided on the uneven layer 20 with an adjusted uneven shape, whereby the surface flatness is improved. Thereby, the quantum confinement structure 30 with an enhanced electron confinement effect is Implemented. The semiconductor device 10D provided with the quantum confinement structure 30, functioning as a HEMT having high carrier mobility and low leakage current, and having excellent characteristics is implemented.
Note that the types and layer structures of the metals used for the gate electrode 15, the source electrode 16, and the drain electrode 17 of the semiconductor device 10D are not limited to the above examples, and the methods for forming the electrodes are also not limited to the above examples. Each of the gate electrode 15, the source electrode 16, and the drain electrode 17 may have a single-layer structure or a stacked structure. At the time of forming the source electrode 16 and the drain electrode 17, the above-described heat treatment may not be needed as long as ohmic connection is implemented by the formation of the electrode metal. At the time of forming the gate electrode 15, heat treatment may be further performed after the formation of the electrode metal. The structure of the gate electrode 15 is not limited to the above-described Schottky gate structure, and may be a MIS gate structure having an insulating film interposed between the gate electrode 15 and the barrier layer 13.
Furthermore, in the semiconductor device 10D, a cap layer 50 using a nitride semiconductor may be provided on the barrier layer 13, according to the example of the semiconductor device 10C as described in the third embodiment.
A semiconductor device 10E illustrated in
A nitride semiconductor similar to the nitride semiconductor described for the semiconductor device 10B (
The semiconductor device 10E having the above configuration can be formed according to the example of the method described with reference to
That is, for example, first, according to the example in
Next, according to the example In
Next, according to the example above in
Next, a passivation film 40 is formed on the barrier layer 13, the cathode electrode 18, and the anode electrode 19 according to the example in
The semiconductor device 10E having the configuration illustrated in
According to the semiconductor device 10E, the quantum confinement structure 30 realizes a highly efficient and highly reliable SBD in which diffusion of electrons as carriers to a deep portion is restricted and leakage from the channel layer 12, that is, for example, generation of a leakage current is suppressed.
Note that the semiconductor device 10E described in the fifth embodiment may be mixedly mounted on one common substrate with the semiconductor device 10A described in the first embodiment or the semiconductor device 10B, 10C, or 10D described in the second, third, or fourth embodiment. For example, a semiconductor device in which the semiconductor device 10B and the semiconductor device 10E are mixedly mounted on one substrate can be obtained.
The semiconductor devices 10A, 10, 10C, 10D, 10E and the like having the configurations described in the first to fifth embodiments can be applied to various electronic devices. As examples, cases in which the semiconductor device having the above configuration is applied to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier will be described below.
Here, an application of a semiconductor device having a configuration as described above to a semiconductor package will be described as a sixth embodiment.
A semiconductor package 200 illustrated in
The semiconductor device 10A is mounted on a die pad 210a of the lead frame 210, using a die attach material or the like (not illustrated). The semiconductor device 10A includes a pad 15a connected to a gate electrode 15 described above, a pad 16a connected to a source electrode 16, and a pad 17a connected to a drain electrode 17. The pad 15a, the pad 16a, and the pad 17a are respectively connected to a gate lead 211, a source lead 212, and a drain lead 213 of the lead frame 210, using a wire 230 of Al or the like. The wire 230 connecting the lead frame 210 and the semiconductor device 10A mounted on the lead frame 210 is sealed by the resin 220 so as to partially expose the gate lead 211, the source lead 212, and the drain lead 213, respectively.
For example, the semiconductor package 200 using the semiconductor device 10A described in the first embodiment above and having such a configuration is obtained. Here, the semiconductor device 10A has been used as an example. However, a high-performance semiconductor package can be similarly obtained using another semiconductor device 10B, 10C, 10D, or the like functioning as an HEMT.
As described above, in the semiconductor devices 10A, 10B, 10C, 10D, and the like, the channel layer 12 is provided on the uneven layer 20 having an adjusted uneven shape, and the surface flatness of the channel layer 12 is improved. Thereby, the quantum confinement structure 30 with an enhanced electron confinement effect is implemented. The high-performance semiconductor package 200 using the semiconductor device 10A, 10B, 10C, 10D, or the like, having such a quantum confinement structure 30, functioning as a HEMT having a high carrier mobility and a low leakage current, and having excellent characteristics is implemented.
Furthermore, a discrete package can be obtained using the semiconductor device 10E or the like functioning as an SBD. As described above, in the semiconductor device 10E and the like, the channel layer 12 is provided on the uneven layer 20 having an adjusted uneven shape, and the surface flatness of the channel layer 12 is improved. Thereby, the quantum confinement structure 30 with an enhanced electron confinement effect is implemented. The high-performance semiconductor package 200 using the semiconductor device 10E or the like, having such a quantum confinement structure 30, functioning as an SBD having a high carrier mobility and a low leakage current, and having excellent characteristics is implemented.
Here, an application of a semiconductor device having a configuration as described above to a power factor correction circuit will be described as a seventh embodiment.
A power factor correction (PFC) circuit 300 illustrated In
In the PFC circuit 300, a drain electrode of the switch element 310 is connected to an anode terminal of the diode 320 and one terminal of the choke coil 330. A source electrode of the switch element 310 is connected to one terminal of the capacitor 340 and one terminal of the capacitor 350. The other terminal of the capacitor 340 and the other terminal of the choke coil 330 are connected. The other terminal of the capacitor 350 and a cathode terminal of the diode 320 are connected. Furthermore, a gate driver is connected to a gate electrode of the switch element 310. The AC power supply 370 is connected between both terminals of the capacitor 340 via the diode bridge 360, and a DC power supply (DC) is extracted from both terminals of the capacitor 350.
For example, the above-described semiconductor device 10A, 10B, 10C, 10D, or the like which functions as a HEMT is used for the switch element 310 of the PFC circuit 300 having such a configuration.
As described above, in the semiconductor devices 10A, 10B, 10C, 10D, and the like, the channel layer 12 is provided on the uneven layer 20 having an adjusted uneven shape, and the surface flatness of the channel layer 12 is improved. Thereby, the quantum confinement structure 30 with an enhanced electron confinement effect is implemented. The high-performance PFC circuit 300 using the semiconductor device 10A, 10B, 10C, 10D, or the like, having such a quantum confinement structure 30, functioning as a HEMT having a high carrier mobility and a low leakage current, and having excellent characteristics is implemented.
Furthermore, the above-described semiconductor device 10E or the like functioning as an SBD may be used for the diode 320 and the diode bridge 360 of the PFC circuit 300. As described above, in the semiconductor device 10E and the like, the channel layer 12 is provided on the uneven layer 20 having an adjusted uneven shape, and the surface flatness of the channel layer 12 is improved. Thereby, the quantum confinement structure 30 with an enhanced electron confinement effect is implemented. The high-performance PFC circuit 300 using the semiconductor device 10E or the like, having such a quantum confinement structure 30, functioning as an SBD having a high carrier mobility and a low leakage current, and having excellent characteristics is implemented.
Here, an application of a semiconductor device having a configuration as described above to a power supply device will be described as an eighth embodiment.
A power supply device 400 illustrated in
The primary-side circuit 410 includes a PFC circuit 300 as described in the above seventh embodiment, and an inverter circuit such as a full-bridge inverter circuit 440 connected between both terminals of a capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of (here, four as an example) switch elements 441, 442, 443, and 444.
The secondary-side circuit 420 includes a plurality of (here, three as an example) switch elements 421, 422, and 423.
For example, the above-described semiconductor device 10A, 10B, 10C, 10D, or the like functioning as a HEMT is used for the switch element 310 of the PFC circuit 300 and the switch elements 441 to 444 of the full-bridge inverter circuit 440 of the primary-side circuit 410 of the power supply device 400 having such a configuration. For example, a normal metal insulator semiconductor (MIS) field effect transistor using silicon is used for the switch elements 421 to 423 of the secondary-side circuit 420 of the power supply device 400.
As described above, in the semiconductor devices 10A, 10B, 10C, 10D, and the like, the channel layer 12 is provided on the uneven layer 20 having an adjusted uneven shape, and the surface flatness of the channel layer 12 is improved. Thereby, the quantum confinement structure 30 with an enhanced electron confinement effect is implemented. The high-performance power supply device 400 using the semiconductor device 10A, 10B, 10C, 10D, or the like, having such a quantum confinement structure 30, functioning as a HEMT having a high carrier mobility and a low leakage current, and having excellent characteristics is implemented.
Furthermore, the semiconductor device 10E or the like functioning as an SBD may be used for the diode 320 and the diode bridge 360 of the PFC circuit 300 included in the primary-side circuit 410, as described in the seventh embodiment above. The high-performance PFC circuit 300 is implemented using the semiconductor device 10E or the like having excellent characteristics, and the high-performance power supply device 400 is implemented using such a PFC circuit 300.
Here, an application of a semiconductor device having a configuration as described above to an amplifier will be described as a ninth embodiment.
An amplifier 500 illustrated In
The digital predistortion circuit 510 compensates for nonlinear distortion of an input signal. The mixer 520 mixes an input signal SI compensated for its nonlinear distortion with an AC signal. The power amplifier 540 amplifies a signal obtained by mixing the input signal SI with the AC signal. The amplifier 500 can, for example, mix an output signal SO with the AC signal using the mixer 530 by switching a switch and can send out the mixed signal to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-output amplifier.
The above-described semiconductor device 10A, 10B, 10C, 10D, or the like which functions as a HEMT is used for the power amplifier 540 of the amplifier 500 having such a configuration.
As described above, in the semiconductor devices 10A, 10B, 10C, 10D, and the like, the channel layer 12 is provided on the uneven layer 20 having an adjusted uneven shape, and the surface flatness of the channel layer 12 is improved. Thereby, the quantum confinement structure 30 with an enhanced electron confinement effect is implemented. The high-performance amplifier 500 using the semiconductor device 10A, 10B, 10C, 10D, or the like, having such a quantum confinement structure 30, functioning as a HEMT having a high carrier mobility and a low leakage current, and having excellent characteristics is implemented.
Furthermore, an SBD such as the semiconductor device 10E or the like may be used for a diode in a case where the diode is used for the amplifier 500. As described above, in the semiconductor device 10E and the like, the channel layer 12 is provided on the uneven layer 20 having an adjusted uneven shape, and the surface flatness of the channel layer 12 is improved. Thereby, the quantum confinement structure 30 with an enhanced electron confinement effect is implemented. The high-performance amplifier 500 using the semiconductor device 10E or the like, having such a quantum confinement structure 30, functioning as an SBD having a high carrier mobility and a low leakage current, and having excellent characteristics is implemented.
Various electronic devices to which the above-described semiconductor devices 10A, 10B, 10C, 10D, 10E or the like is applied (the semiconductor package 200, the PFC circuit 300, the power supply device 400, the amplifier 500, and the like described In the sixth to ninth embodiments) can be mounted on various types of electronic equipment. For example, such electronic devices can be mounted on various types of electronic equipment such as a computer (a personal computer, a supercomputer, a server, or the like), a smartphone, a portable telephone, a tablet terminal, a sensor, a camera, an audio apparatus, a measuring device, an inspection device, and a manufacturing device.
All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Number | Date | Country | Kind |
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2019-080975 | Apr 2019 | JP | national |