Patent Application
20120049281
Embodiments described herein relate generally to semiconductor devices (e.g., multi-gate non-planar field effect transistors) with effective work function controlled metal gates and methods of making semiconductor devices with effective work function controlled metal gates.
As transistor design is improved and evolved, the number of different types of transistors continues to increase. Multi-gate non-planar field effect transistors, including double-gate non-planar field effect transistors (e.g., finFETs) and tri-gate non-planar FETs, are developed to provide scaled devices with larger drive currents and reduced short channel effects over planar FETs.
Double-gate non-planar FETs are FETs in which a channel region is formed in a thin silicon fin sidewalls. Source and drain regions are formed in the opposing ends of the fin on either side of the channel region. Gates are formed over the thin silicon fin in areas corresponding to channel regions. FinFETs are a type of double-gate non-planar FETs in which the fin is so thin as to be fully depleted.
Tri-gate non-planar FETs have a similar structure to that of double-gate non-planar FETs; however, gates can be formed on three sides of the channel, including the top surface and the opposing sidewalls. The height to width ratio is generally larger than 1:1 so that the channel will remain fully depleted and the three-dimensional field effects of a tri-gate FET will give greater drive current and improved short-channel characteristics over a planar transistor.
One aspect of the innovation described herein can provide gate electrodes of a multi-gate metal field effect transistor. The devices, such as field effect transistors, can contain a semiconductor substrate; a dielectric layer over the semiconductor substrate; a fin over the dielectric layer; a gate insulating layer over the side surfaces of the fin; a gate electrode layer over the fin; and a polysilicon layer over the fin. The devices do not contain a gate insulating layer over the upper surface of the dielectric layer except portions of the upper surface of the dielectric layer that contact with the side surfaces of the gate insulating layer formed over the side surface of the fin.
Another aspect of the innovation can provide other gate electrodes of a multi-gate metal field effect transistor. The multi-gate metal field effect transistor can contain a semiconductor substrate; a dielectric layer over the semiconductor substrate; a fin over the dielectric layer; an oxygen diffusion barrier layer or a first oxygen diffusion layer over the upper surface of the dielectric layer; a gate insulating layer over the side surfaces of the fin; a gate electrode layer over the fin; and a polysilicon layer over the fin.
Yet another aspect of the innovation provides methods of making a gate electrode of a multi-gate metal field effect transistor. The method can involve forming a fin over a dielectric layer and a semiconductor substrate; forming a gate insulating layer over the side surfaces of the fin; foiining a gate electrode layer over the fin; and forming a polysilicon layer over the fin. The method, however, does not involve forming a gate insulating layer over the upper surface of the dielectric layer except portions of the upper surface of the dielectric layer that contact with the side surfaces of the gate insulating layer formed over the side surface of the fin.
Still yet another aspect of the innovation provides other methods of making a gate electrode of a multi-gate metal field effect transistor. The method can involve forming a fin over a dielectric layer and a semiconductor substrate; forming an oxygen diffusion barrier layer or a first oxygen diffusion layer over the upper surface of the dielectric layer; forming a gate insulating layer over the side surfaces of the fin; and forming a gate electrode layer over the fin; and forming a polysilicon layer over the fin.
In certain embodiments, effective work function of a gate electrode is controlled. The effective work function can be controlled by controlling an amount of oxygen diffusion from a transistor isolation region (e.g., a dielectric layer or buried silicon oxide (BOX) layer) to an interface of a gate insulating layer. The amount of oxygen diffusion can be controlled 1) by not forming a gate insulating layer over an upper surface of a dielectric layer, 2) by containing an oxygen diffusion barrier layer over an upper surface of a dielectric layer, 3) by containing an oxygen diffusion layer over an upper surface of a dielectric layer. The amount of oxygen diffusion can be decreased and the effective work function can be decreased by not forming a gate insulating layer over an upper surface of a dielectric layer and/or by containing an oxygen diffusion barrier layer over an upper surface of a dielectric layer. The amount of oxygen diffusion can be increased and the effective work function can be increased by containing an oxygen diffusion layer over an upper surface of a dielectric layer.
In certain embodiment, a multi-gate metal field effect transistor contains two or more gate electrodes that have different effective work functions from each other. For example, a multi-gate metal field effect transistor contains a first gate electrode and a second gate electrode and the effective work function of the first gate electrode is smaller than the effective work function of the second gate electrode.
The claimed subject matter is now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. It may be evident, however, that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram faun in order to facilitate describing the claimed subject matter.
The transistor of the subject innovation can contain any suitable number of fins. In one embodiment, the transistor contains one fin. In another embodiment, the transistor contains two or more fins. Although four fins are shown in
The channel of the transistor 102 can be doped to produce either an N-type semiconductor or a P-type semiconductor. In one embodiment, the transistor 102 is an N-type field effect transistor. In another embodiment, the transistor 102 is a P-type field effect transistor. In the subsequent embodiment, transistors can be an N-type field effect transistor or a P-type field effect transistor.
The fin typically contains silicon. The fin has a substantially rectangular parallelepiped shape. The dimensions of the substantially rectangular parallelepiped shape have a suitable length depending on the desired implementations of the transistor being fabricated. In one embodiment, the height of the fin is about 20 nm or more and about 200 nm or less. In another embodiment, the height of the fin is about 30 nm or more and about 180 nm or less. In yet another embodiment, the height of the fin is about 40 nm or more and about 160 nm or less.
In one embodiment, the short sides of the upper and lower surfaces of the fin are about 5 nm or more and about 100 nm or less. In another embodiment, the short sides of the upper and lower surfaces of the fin are about 7 nm or more and about 70 nm or less. In yet another embodiment, the short sides of the upper and lower surfaces of the fin are about 10 nm or more and about 50 nm or less.
In one embodiment, the long sides of the upper and lower surfaces of the fin are about 300 nm or more and about 1,500 nm or less. In another embodiment, the long sides of the upper and lower surfaces of the fin are about 400 nm or more and about 1,300 nm or less. In yet another embodiment, the long sides of the upper and lower surfaces of the fin are about 500 urn or more and about 1,000 nm or less.
The gate insulating layer is formed over the side surface of the fin. The gate insulating layer can be formed over the upper surface of the fin. The gate insulating layer, however, is not formed over the upper surface of the dielectric layer except portions of the upper surface of the dielectric layer that contact with the side surfaces (e.g., edges) of the gate insulating layer formed over the side surface of the fin. The gate insulating layer is not formed over the upper surface of the dielectric layer except adjacent portions of the upper surface of the dielectric layer to the side surfaces of the fin. The length of the adjacent portion over which the gate insulating layer is formed is about equal to the thickness of the gate insulating layer. Only the side surface or the edge of the gate insulating layer is in contact with the upper surface of the dielectric layer.
In one embodiment, about 80% or more and about 99.9% of less of the upper surface area of dielectric layer of the gate electrode is not covered with the gate insulating layer. In another embodiment, about 90% or more and about 99.9% of less of the upper surface area of dielectric layer of the gate electrode is not covered with the gate insulating layer. In yet another embodiment, about 95% or more and about 99.9% of less of the upper surface area of dielectric layer of the gate electrode is not covered with the gate insulating layer.
A portion of the gate electrode can be directly in contact with the upper surface of the dielectric layer. In one embodiment, about 80% or more and about 99.9% of less of the upper surface area of dielectric layer of the gate electrode is directly in contact with the gate electrode layer. In another embodiment, about 90% or more and about 99.9% of less of the upper surface area of dielectric layer of the gate electrode is directly in contact with the gate electrode layer. In yet another embodiment, about 95% or more and about 99.9% of less of the upper surface area of dielectric layer of the gate electrode is directly in contact with the gate electrode layer.
The gate insulating layer can contain any suitable insulating material. In one embodiment, heat of formation (AHf) of the gate insulating layer is negatively greater than heat of formation of the dielectric layer. In another embodiment, the gate insulating layer has heat of formation of about −900 kJ/mol or more and about −2300 kJ/mol or less, and the dielectric layer has heat of formation of about −100 kJ/mol or more and about −1700 kJ/mol or less. In yet another embodiment, the gate insulating layer has heat of formation of about −1100 kJ/mol or more and about −1800 kJ/mol or less, and the dielectric layer has heat of formation of about −300 kJ/mol or more and about −1500 kJ/mol or less. In still yet another embodiment, the gate insulating layer has heat of formation of about −1500 kJ/mol or more and about −1800 kJ/mol or less, and the dielectric layer has heat of formation of about −500 kJ/mol or more and about −1200 kJ/mol or less.
In one embodiment, a dielectric constant of (k) of the gate insulating layer is greater than a dielectric constant of the dielectric layer. The gate insulating layer typically has a dielectric constant of greater than about 3.9. In another embodiment, the gate insulating layer has a dielectric constant of about 4.5 or more and about 200 or less, and the dielectric layer has a dielectric constant of about 2 or more and about 50 or less. In yet another embodiment, the gate insulating layer has a dielectric constant of about 4.5 or more and about 50 or less, and the dielectric layer has a dielectric constant of about 2 or more and about 30 or less. In still yet another embodiment, the gate insulating layer has a dielectric constant of about 4.5 or more and about 25 or less, and the dielectric layer has a dielectric constant of about 2 or more and about 10 or less.
The gate insulating layer can contain a suitable high-k material. Examples of high-k materials include a metal oxide, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), hafnium oxide (HfO2), yttrium oxide (Y2O3), silicon zirconium oxide (SiZrO4), lanthanum oxide (La2O3), other corresponding silicates, or the like.
The gate insulating layer has a suitable thickness depending on the desired implementations of the transistor being fabricated. In one embodiment, the thickness of the gate insulating layer is about 0.1 nm or more and about 20 nm or less. In another embodiment, the thickness of the gate insulating layer is about 0.1 nm or more and about 10 nm or less. In yet another embodiment, the thickness of the gate insulating layer is about 0.1 nm or more and about 5 nm or less.
The gate electrode layer is formed over gate insulating layer and over the side surface of the fin. The gate electrode layer can be formed over the upper surface of the fin and the upper surface of the dielectric layer. The gate electrode layer can be directly in contact with the upper surface of the dielectric layer.
The gate electrode layer can contain a suitable electrically conductive material including metals and metal compounds. In one embodiment, the gate electrode layer contains metals, metal compounds, and combinations of thereof that have a melting point of about 500 degrees Celsius or more. Example of metals and metal compounds include tungsten (W), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), titanium carbide (TiC), titanium carbonitride (TiCN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), and combinations thereof.
The gate electrode layer has a suitable thickness depending on the desired implementations of the transistor being fabricated. In one embodiment, the thickness of the gate electrode layer is about 0.1 nm or more and about 20 nm or less. In another embodiment, the thickness of the gate electrode layer is about 0.1 nm or more and about 10 nm or less. In yet another embodiment, the thickness of the gate electrode layer is about 0.1 nm or more and about 5 nm or less.
Although not illustrated in
In another embodiment, the gate electrode contains ions in one or more components of the gate electrode to control (e.g., decrease or increase) an effective work function. The ions can be contained in at least the gate insulating layer, the interface between the fin and the gate electrode layer, the interface between the gate electrode layer and the gate insulating layer, or combinations thereof. Examples of ions include aluminum (Al), nitrogen (N), arsenic (As), fluorine (F), indium (In), or the like. The ions can be introduced into the one or more components by ion implantation. The ions can be implanted at a dose of about 1×1015 atoms/cm2 or more and about 5×1016 atoms/cm2 or less and at an energy level of about 2 KeV or more and about 40 KeV or less, for example.
The gate electrode can have an effective work function of about 4.6 eV or less. In one embodiment, the gate electrode has an effective work function of about 4.5 eV or less. In another embodiment, the gate electrode has an effective work function of about 4.2 eV or less. In yet another embodiment, the gate electrode has an effective work function of about 4.0 eV or less.
The gate electrode 200 contains the semiconductor substrate 204, the dielectric layer 206, the fin 208, the gate insulating layer 210, the gate electrode layer 212, and the polysilicon layer 214 in the same manner as the gate electrode 100 as described in connection with
The hard mask layer can contain any suitable material that has smaller oxygen diffusion coefficient so that the gate electrode can have a low effective work function. The hard mask layer can have smaller oxygen diffusion coefficient than the dielectric layer. In one embodiment, the hard mask has an oxygen diffusion coefficient that is smaller than that of the dielectric layer by about 1×10−25 cm2·s4 or more and about 1×1043 cm2·s4 or less. In another embodiment, the hard mask has an oxygen diffusion coefficient that is smaller than that of the dielectric layer by about 1×10−23 cm2·s4 or more and about 1×10−14 cm2·s−1 or less. In yet another embodiment, the hard mask has an oxygen diffusion coefficient that is smaller than that of the dielectric layer by about 1×10−20 cm2·s−1 or more and about 1×10−15 cm2·s−1 or less.
The hard mask can contain a smaller interstitial oxygen concentration than the dielectric layer. In one embodiment, the hard mask has an interstitial oxygen concentration that is smaller than that of the dielectric layer by about 1×1016 atoms·cm−3 or more and about 5×1021 atoms·cm−3 or less. In another embodiment, the hard mask has an interstitial oxygen concentration that is smaller than that of the dielectric layer by about 1×1017 atoms·cm−3 or more and about 2×1021 atoms·cm−3 or less. In yet another embodiment, the hard mask has an interstitial oxygen concentration that is smaller than that of the dielectric layer by about 1×1018 atoms·cm−3 or more and about 5×102° atoms·cm−3 or less.
The hard mask can contain a larger interstitial nitrogen concentration than the dielectric layer. In one embodiment, the hard mask has an interstitial nitrogen concentration that is larger than that of the dielectric layer by about 1×1020 atoms·cm−3 or more and about 5×1023 atoms·cm−3 or less. In another embodiment, the hard mask has an interstitial nitrogen concentration that is larger than that of the dielectric layer by about 1×1021 atoms·cm−3 or more and about 5×1023 atoms·cm−3 or less. In yet another embodiment, the hard mask has an interstitial nitrogen concentration that is larger than that of the dielectric layer by about 1×1022 atoms·cm−3 or more and about 5×1023 atoms·cm−3 or less. In still yet another embodiment, the hard mask has an interstitial nitrogen concentration of about 1×1020 atoms·cm3 or more. The hard mask can contain nitrides. Examples of nitrides include silicon oxynitride (SiON), silicon nitride (SiN), or the like.
The hard mask layer has a suitable thickness depending on the desired implementations of the transistor being fabricated. In one embodiment, the thickness of the hard mask layer is about 1 nm or more and about 50 nm or less. In another embodiment, the thickness of the hard mask layer is about 3 nm or more and about 40 nm or less. In yet another embodiment, the thickness of the hard mask layer is about 5 nm or more and about 30 nm or less.
The gate electrode does not necessarily contain the gate insulating layer and/or the gate electrode layer over the upper surface of the hard mask. Although now shown in
The gate electrode 300 contains the semiconductor substrate 304, the dielectric layer 306, the fin 308, the gate insulating layer 310, the gate electrode layer 312, and the polysilicon layer 314 in the same manner as the gate electrode 100 as described in connection with
The oxygen diffusion barrier layer can contain any suitable material that can prevent or mitigate oxygen diffusion from the dielectric layer 306 to the polysilicon layer 314. In other words, the oxygen diffusion barrier layer can have smaller oxygen diffusion coefficient than the dielectric layer. In one embodiment, the oxygen diffusion barrier layer has an oxygen diffusion coefficient that is smaller than that of the dielectric layer by about 1×10−25 cm−2·s−1 or more and about 1×10−13 cm2·s−1 or less. In another embodiment, the oxygen diffusion barrier layer has an oxygen diffusion coefficient that is smaller than that of the dielectric layer by about 1×10−23 cm2·s−1 or more and about 1×10−14 cm2·s−1 or less. In yet another embodiment, the oxygen diffusion barrier layer has an oxygen diffusion coefficient that is smaller than that of the dielectric layer by about 1×10−20 cm2·s−1 m2·s−1 or more and about 1×10−15 cm2·s−1 or less.
The oxygen diffusion barrier layer can contain a smaller interstitial oxygen concentration than the dielectric layer. In one embodiment, the oxygen diffusion barrier layer has an interstitial oxygen concentration that is smaller than that of the dielectric layer by about 1×1016 atoms-cm−3 or more and about 5×1021 atoms·cm−3 or less. In another embodiment, the oxygen diffusion barrier layer has an interstitial oxygen concentration that is smaller than that of the dielectric layer by about 1×1017 atoms·cm−3 or more and about 1×1021 atoms·cm−3 or less. In yet another embodiment, the oxygen diffusion barrier layer has an interstitial oxygen concentration that is smaller than that of the dielectric layer by about 1×1018 atoms·cm−3 or more and about 1×1020 atoms·cm−3 or less.
The oxygen diffusion barrier layer can contain a larger interstitial nitrogen concentration than the dielectric layer. In one embodiment, the oxygen diffusion barrier layer has an interstitial nitrogen concentration that is larger than that of the dielectric layer by about 1×1016 atoms·cm3 or more and about 5×1021 atoms·cm−3 or less. In another embodiment, the oxygen diffusion barrier layer has an interstitial nitrogen concentration that is larger than that of the dielectric layer by about 1×1017 atoms·cm−3 or more and about 1×1021 atoms·cm−3 or less. In yet another embodiment, the oxygen diffusion barrier layer has an interstitial nitrogen concentration that is larger than that of the dielectric layer by about 1×1018 atoms·cm−3 or more and about 1×1020 atoms·cm−3 or less. In still yet another embodiment, the oxygen diffusion barrier layer has an interstitial nitrogen concentration of about 1×1020 atoms·cm−3 or more.
The oxygen diffusion barrier layer has a suitable thickness depending on the desired implementations of the transistor being fabricated. In one embodiment, the thickness of the oxygen diffusion barrier layer is about 1 nm or more and about 50 nm or less. In another embodiment, the thickness of the oxygen diffusion barrier layer is about 3 nm or more and about 40 nm or less. In yet another embodiment, the thickness of the oxygen diffusion barrier layer is about 5 nm or more and about 30 nm or less.
The gate electrode 400 contains the semiconductor substrate 404, the dielectric layer 406, the fin 408, the gate insulating layer 410, the gate electrode layer 412, and the polysilicon layer 414 in the same manner as the gate electrode 300 as described in connection with
The gate electrode does not necessarily contain the gate insulating layer and/or the gate electrode layer over the upper surface of the hard mask. Although now shown in
The gate electrode 500 contains the semiconductor substrate 504, the dielectric layer 506, the fin 508, the gate insulating layer 510, the gate electrode layer 512, and the polysilicon layer 514 in the same manner as the gate electrode 100 as described in connection with
The gate electrode 600 contains the semiconductor substrate 604, the dielectric layer 606, the fin 608, the oxygen diffusion barrier layer 618; the gate insulating layer 610, the gate electrode layer 612, and the polysilicon layer 614 in the same manner as the gate electrode 500 as described in connection with
The gate electrode does not necessarily contain the gate insulating layer and/or the gate electrode layer over the upper surface of the hard mask. Although now shown in
The gate electrode 700 contains the semiconductor substrate 704, the dielectric layer 706, the fin 708, the hard mask layer 716, the gate insulating layer 710, the gate electrode layer 712, and the polysilicon layer 714 in the same manner as the gate electrode 100 as described in connection with
The first oxygen diffusion layer can contain any suitable material that can enhance oxygen diffusion from the dielectric layer 706 to the polysilicon layer 714. In other words, the first oxygen diffusion layer can have larger oxygen diffusion coefficient than the dielectric layer. In one embodiment, the first oxygen diffusion layer has an oxygen diffusion coefficient that is larger than that of the dielectric layer by about 1×10−20 cm2 s−1 or more and about 1×10−10 cm2 s−1 or less. In another embodiment, the first oxygen diffusion layer has an oxygen diffusion coefficient that is larger than that of the dielectric layer by about 1×10−18 cm2 s−1 or more and about 1×10−13 cm2 s−1 or less. In yet another embodiment, the first oxygen diffusion layer has an oxygen diffusion coefficient that is larger than that of the dielectric layer by about 1×10−16 m2 s−1 or more and about 1×10−15 m2 s−1 or less.
The first oxygen diffusion layer can contain a larger interstitial oxygen concentration than the dielectric layer. In one embodiment, the first oxygen diffusion layer has an interstitial oxygen concentration that is larger than that of the dielectric layer by about 5×1019 atoms·cm−3 or more and about 5×1023 atoms·cm−3 or less. In another embodiment, the first oxygen diffusion layer has an interstitial oxygen concentration that is larger than that of the dielectric layer by about 5×1020 atoms·cm3 or more and about 5×1023 atoms·cm−3 or less. In yet another embodiment, the first oxygen diffusion layer has an interstitial oxygen concentration that is larger than that of the dielectric layer by about 5×1021 atoms·cm−3 or more and about 5×1023 atoms·cm−3 or less.
The first oxygen diffusion layer can contain any suitable oxides. Specific examples of materials of first oxygen diffusion layer include disordered silicon oxide (e.g., SiO2), oxygen-rich silicon oxide, tetraethylorthosilicate (TEOS), high density plasma (HDP) oxide, or the like.
The first oxygen diffusion layer has a suitable thickness depending on the desired implementations of the transistor being fabricated. In one embodiment, the thickness of the first oxygen diffusion layer is about 5 nm or more and about 50 nm or less. In another embodiment, the thickness of the first oxygen diffusion layer is about 7 nm or more and about 40 nm or less. In yet another embodiment, the thickness of the first oxygen diffusion layer is about 10 nm or more and about 30 nm or less.
The gate electrode 700 can have an effective work function of about 4.6 eV or more. In one embodiment, the gate electrode has an effective work function of about 4.7 eV or more. In another embodiment, the gate electrode has an effective work function of about 5.0 eV or more. In yet another embodiment, the gate electrode has an effective work function of about 5.2 eV or more.
The gate electrode 800 contains the semiconductor substrate 804, the dielectric layer 806, the fin 808, the gate insulating layer 810, the gate electrode layer 812, and the polysilicon layer 814, the first oxygen diffusion layer 820 in the same manner as the gate electrode 700 as described in connection with
The gate electrode does not necessarily contain the gate insulating layer and/or the gate electrode layer over the upper surface of the hard mask. Although now shown in
The gate insulating layer and/or the gate electrode layer are not necessarily formed over the upper surface of the hard mask. Although now shown in
The gate electrode 900 contains the semiconductor substrate 904, the dielectric layer 906, the fin 908, the gate insulating layer 910, the gate electrode layer 912, and the polysilicon layer 914 in the same manner as the gate electrode 100 as described in connection with
The gate electrode 1000 contains the semiconductor substrate 1004, the dielectric layer 1006, the fin 1008, the first oxygen diffusion layer 1020; the gate insulating layer 1010, the gate electrode layer 1012, and the polysilicon layer 1014 in the same manner as the gate electrode 900 as described in connection with
The gate electrode does not necessarily contain the gate insulating layer and/or the gate electrode layer over the upper surface of the hard mask. Although now shown in
The gate electrode 1100 contains the semiconductor substrate 1104, the dielectric layer 1106, the fin 1108, the first oxygen diffusion layer 1120, the second oxygen diffusion layer 1122, the gate insulating layer 1110, the gate electrode layer 1112, and the polysilicon layer 1114 in the same manner as the gate electrode 700 as described in connection with
The gate electrode does not necessarily contain the gate insulating layer and/or the gate electrode layer over the upper surface of the second oxygen diffusion. Although now shown in
The gate electrode 1200 contains the semiconductor substrate 1204, the dielectric layer 1206, the fin 1208, the first oxygen diffusion layer 1220, the second oxygen diffusion layer 1222, the hard mask 1216, the gate insulating layer 1210, the gate electrode layer 1212, and the polysilicon layer 1214 in the same mariner as the gate electrode 1100 as described in connection with
The gate electrode does not necessarily contain the gate insulating layer and/or the gate electrode layer over the upper surface of the hard mask. Although now shown in
The gate electrode 1300 contains the semiconductor substrate 1304, the dielectric layer 1306, the fin 1308, the first oxygen diffusion layer 1320, the second oxygen diffusion layer 1322; the gate insulating layer 1310, the gate electrode layer 1312, and the polysilicon layer 1314 in the same manner as the gate electrode 1100 as described in connection with
The gate electrode does not necessarily contain the gate insulating layer and/or the gate electrode layer over the upper surface of the second oxygen diffusion. Although now shown in
The gate electrode 1400 contains the semiconductor substrate 1404, the dielectric layer 1406, the fin 1408, the first oxygen diffusion layer 1420, the second oxygen diffusion layer 1422, the gate insulating layer 1410, the gate electrode layer 1412, and the polysilicon layer 1414 in the same manner as the gate electrode 1300 as described in connection with
The gate electrode does not necessarily contain the gate insulating layer and/or the gate electrode layer over the upper surface of the hard mask. Although now shown in
The gate electrode 1700 contains the semiconductor substrate 1704, the dielectric layer 1706, the fin 1708, the oxygen diffusion barrier layer 1718, the second oxygen diffusion layer 1722; the gate insulating layer 1710, the gate electrode layer 1712, and the polysilicon layer 1714 in the same manner as the gate electrode 1500 as described in connection with
The gate electrode 1800 contains the semiconductor substrate 1804, the dielectric layer 1806, the fin 1808, the first oxygen diffusion barrier layer 1818, the second oxygen diffusion layer 1822, the hard mask 1816, the gate insulating layer 1810, the gate electrode layer 1812, and the polysilicon layer 1814 in the same manner as the gate electrode 1700 as described in connection with
In
The gate electrode 1950 can contain a fin 1958 over the dielectric layer; a hard mask layer 1966 over the fin; a gate insulating layer 1960 over the side surfaces of the fin; a gate electrode layer 1962 over the fin; and a polysilicon layer 1964 over the fin. Although not shown in
The first gate electrode 1900 can have a smaller effective work function than the second gate electrode 1950. In one embodiment, the first gate electrode can have a smaller effective work function than the second gate electrode. The first gate electrode can have an effective work function smaller than about 4.6 eV and the second gate electrode can have an effective work function larger than about 4.6 eV. In another embodiment, the first gate electrode can have a smaller effective work function than the second gate electrode by about 0.2 eV or more and about 1.2 eV or less. In yet another embodiment, the first gate electrode can have a smaller effective work function than the second gate electrode by about 0.4 eV or more and about 1.0 eV or less.
In another embodiment, the first gate electrode 1900 can have a larger effective work function than the second gate electrode 1950. In one embodiment, the first gate electrode can have a larger effective work function than the second gate electrode. The first gate electrode can have an effective work function larger than about 4.6 eV and the second gate electrode can have an effective work function smaller than about 4.6 eV. In another embodiment, the first gate electrode can have a larger effective work function than the second gate electrode by about 0.2 eV or more and about 1.2 eV or less. In yet another embodiment, the first gate electrode can have a larger effective work function than the second gate electrode by about 0.4 eV or more and about 1.0 eV or less.
The first gate electrode 2000 and the second gate electrode 2050 can be selected individually from the group consisting of gate electrodes 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, and 1800 as described in connection with
The two or more gate electrodes can have any suitable effective work function. The first gate electrode 2000 can have a smaller effective work function than the second gate electrode 2050. In one embodiment, the first gate electrode can have a smaller effective work function than the second gate electrode. The first gate electrode can have an effective work function smaller than about 4.6 eV and the second gate electrode can have an effective work function larger than about 4.6 eV. In another embodiment, the first gate electrode can have a smaller effective work function than the second gate electrode by about 0.2 eV or more and about 1.2 eV or less. In yet another embodiment, the first gate electrode can have a smaller effective work function than the second gate electrode by about 0.4 eV or more and about 1.0 eV or less.
Referring to
The dielectric layer can be a buried silicon oxide layer or a BOX layer, and can be formed over the semiconductor substrate by any suitable deposition technique. Examples of deposition techniques include chemical vapor deposition (CVD) such as plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), high-pressure chemical vapor deposition (HPCVD), or the like. The fin and the hard mask can be formed by forming a layer containing a fin material over the dielectric layer and a layer containing a hard mask material over the fin material layer, and removing portions of the layers by using a suitable patterned resist layer. The patterned resist layer can be formed by optical lithography, sidewall image transfer technique, or the like.
The portions of the fin material layer and the hard mask material layer can be removed by contacting the layers with any suitable etchant that does not substantially damage and/or remove other components of the transistor. Choice of a suitable process and reagents of etching depends on, for example, the fin material, the hard mask material, the width and height of the fin, the desired implementations of the transistor being fabricated, or the like.
Wet etching and/or dry etching containing isotropic etching and/or anisotropic etching can be employed. Examples of wet etchants for the silicon layer include tetraalkylammonium hydroxides (e.g., tetramethylammonium hydroxide (TMAH)) and alkali metal hydroxides (e.g., a potassium hydroxide (KOH) and cerium hydroxide (CeOH)). Examples of dry etching include reactive ion etching (RIB) using, for example, a mixture gas containing HBr (e.g., HBr and O2 mixture gas, HBr/NF3/He and O2 mixture gas, SF6, HBr and O2 mixture gas). The mixture may further include Cl2.
The gate insulating layer can be formed by forming a layer containing a gate insulating material and a protecting layer over the gate insulating material layer, removing portions of the gate insulating material layer and the protecting layer over the upper surface of the dielectric layer, and removing the remaining portions of the protecting layer. The portions of the gate insulating material layer and the protecting layer over the upper surface of the dielectric layer are removed so that the resultant gate insulating layer is not formed over the upper surface of the dielectric layer except portions of the upper surface of the dielectric layer that contact with the side surfaces (e.g., edges) of the gate insulating layer formed over the side surface of the fin. When removing portions of the gate insulating material layer and the protecting layer over the dielectric layer, portions of the gate insulating material layer and the protecting layer over the upper surface of the fin can be also removed.
The portions of the gate insulating material layer and the protecting layer can be removed by any suitable technique including anisotropic reactive ion etching (RIE). The remaining protecting layer can be removed by any suitable technique including wet etching. The protecting layer can contain any suitable material so that the protecting layer can protect the underlying gate insulating material layer from the removing process (e.g., RIB). For example, the protecting layer can contain the same material as the material of the gate metal layer 110 as described in connection with
The first oxygen diffusion layer 2552 can be formed by any suitable technique. In one embodiment, the oxygen diffusion layer is formed by introducing oxygen into the upper surface of the dielectric layer. Oxygen can be introduced by any suitable technique. Examples of techniques for introducing oxygen into the upper surface of the dielectric layer include implantation of ions of rare gas (e.g., xenon (Xe) or krypton (Kr)) followed by thermal oxidation, oxygen ion implantation followed by annealing, or the like. In another embodiment, the oxygen diffusion layer is formed by depositing oxides (e.g., silicon oxides). For example, a silicon oxide is formed by CVD using TEOS and oxygen. The first oxygen diffusion layer can be formed in the same manner as the second diffusion layer. Although not shown in
What has been described above includes examples of the disclosed innovation. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the disclosed innovation, but one of ordinary skill in the art can recognize that many further combinations and permutations of the disclosed innovation are possible. Accordingly, the disclosed innovation is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term “contain,” “includes,” “has,” “involve,” or variants thereof is used in either the detailed description or the claims, such term can be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim.
