The present invention relates to semiconductor packaging and more particularly to a semiconductor device having staggered leads and improved lead pitch.
A factor limiting the density of leads (number of leads per unit length) that a semiconductor device such as a quad flat leaded package (QFP) of a given size can contain is lead pitch. Native lead pitch (LP) is essentially the sum of native lead width (LW) plus native spacing between two leads (LS). A wider lead pitch avoids or at least reduces risk of circuit shortage and improves solderability when the semiconductor device is mounted using a surface-mount technology (SMT) process. It also allows wider leads to be formed, which in turn reduces incidence of lead stress and distortion. A narrower lead pitch on the other hand facilitates greater leads density.
Therefore it would be desirable to provide a semiconductor device that has a wider lead pitch without sacrificing leads density.
The following detailed description of a preferred embodiment of the invention will be better understood when read in conjunction with the appended drawings. The present invention is illustrated by way of example and is not limited by the accompanying figures in which like references indicate similar elements. It is to be understood that the drawings are not to scale and have been simplified for ease of understanding the invention
a-1d show a conventional QFP semiconductor package;
a-2d show a QFP package according to one embodiment of the present invention;
a-4b show the semiconductor device of
a-5b show the semiconductor device of
a-6b show the semiconductor device of
a-7b show the semiconductor device of
a-8b show the semiconductor device of
a-9b show the semiconductor device of
a-10b show a completed semiconductor device in accordance with an embodiment of the present invention;
a-11b show a further semiconductor device according to an embodiment of the present invention;
a-12b show a still further semiconductor device according to the present invention;
a-13d show a still further semiconductor package according to the present invention; and
a-14c show a variation of the semiconductor device of
According to one aspect of the present invention there is provided a process for assembling a semiconductor device comprising: providing a lead frame having a native plane and a plurality of leads having a native lead pitch; trimming and forming a first subset of said plurality of leads to provide a first row of leads; and trimming and forming a second subset of said plurality of leads to provide a second row of leads, wherein at least one subset of leads is formed with an obtuse angle relative to said native plane such that lead pitch associated with said first or second subset of leads is greater than said native lead pitch.
The process may further include trimming and forming a third subset of the plurality of leads to provide a third row of leads such that lead pitch associated with the third subset of leads is greater than the native lead pitch.
The first subset of leads may be trimmed to a first length and the second subset of leads may be trimmed to a second length shorter than the first length. In a preferred form the lead pitch associated with the formed leads may be substantially double the native lead pitch. The first and second subsets of leads may be formed with respective first and second obtuse angles relative to the native plane.
The first subset of leads may be formed with an acute angle relative to the native plane. The acute angle preferably is in the range from 70 to 90 degrees and in one form may be about 80 degrees. The first subset of leads may be trimmed to a first length and the second subset of leads may be trimmed to a second length longer than the first length.
The first subset of leads may be formed with an obtuse angle relative to the native plane. The obtuse angle preferably is in the range from 90 to 135 degrees and in one form may be about 120 degrees. The width of each lead may be substantially in the range NLW to NLP-M mm wherein NLW denotes native lead width, NLP denotes native lead pitch and M denotes a minimum margin between leads. Due to current capability of lead frame manufacturers the minimum preferred margin M is about 0.1 mm. In one form the width of each lead may be about 0.3 mm. The width of each lead may be greater at its tip than along its length.
The present invention also provides a semiconductor device comprising: a lead frame including a native plane and a plurality of leads having a native lead pitch; a first subset of said plurality of leads wherein said first subset of leads is trimmed and formed to a first row of leads; and a second subset of said plurality of leads wherein said second subset of leads is trimmed and formed to a second row of leads, wherein at least one subset of leads is formed with an obtuse angle relative to said native plane such that lead pitch associated with said first or second row of leads is greater than said native lead pitch.
a-1d shows a conventional QFP semiconductor device. A typical lead width (LW) for the QFP package is 0.16 mm. With a typical lead spacing (LS) of about 0.24 mm the lead pitch (LP) of the conventional package is about 0.16+0.24=0.4 mm.
An improved QFP device according to one embodiment of the present invention is shown in
Wider lead pitch in the revised QFP is achieved by forming the tips or feet of the leads into at least two staggered rows, namely a first or outer row 20 and a second or inner row 21 as shown in
a-4b show the first or outer row of leads 32 after being trimmed to a first length and
a-7b show a second or inner row of leads 33 after being trimmed to a second length and
a-10b show a completed semiconductor device 100 in respective side and isometric views after trimming of the tie bar 34.
a-11b show a semiconductor device 110 according to the present invention wherein the outer row of leads 111 is formed with an acute angle of about 80 degrees relative to the native plane. Leads 111 are comparable to outer row of leads 32 in the embodiment described with reference to
a-12b show a further semiconductor device 120 according to the present invention where the outer rows of leads 121 and the inner rows of leads 122 are formed and turned with respective first and second obtuse angles relative to the native plane instead of being formed with acute angles as was the case in the embodiment described with reference to
a-13d show a still further semiconductor device 130 according to the present invention wherein two rows of outer leads 131, 132 are formed with acute angles and two rows of inner leads 133, 134 are formed and turned with acute angles relative to the native plane.
Other combinations of inner and outer rows of leads may be formed and turned employing the same or similar concepts which in a general case may encompass N-rows of leads (N>2) in which different subsets of leads are trimmed to short or long leads and/or are formed to acute angles and/or turned and formed to obtuse angles such that adjacent leads are separated into respective rows whereby lead pitch associated with a given row or subset of leads is increased for improved solderability. For example lead 131 in
As with the embodiment of
a-14c, show a further variation of the embodiment of a semiconductor QFP package 140 wherein the tips 141 of inner and outer leads 142 are wider than prior art leads. Other than the tips 141 the width of the rest of each lead 142 is comparable to lead widths shown in prior art such as
As is evident from the foregoing discussion the present invention provides a method of producing a semiconductor device having staggered leads with improved lead pitch. While the preferred embodiments of the invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions and equivalents will be apparent to those skilled in the art without departing from the spirit and scope of the invention as defined in the claims.
Number | Date | Country | Kind |
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2011 1 0123304 | May 2011 | CN | national |
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