SEMICONDUCTOR DEVICE

Abstract

A semiconductor device may include first and second channel patterns, which are provided on first and second active patterns, respectively, and include first semiconductor patterns and second semiconductor patterns, respectively, and a gate electrode crossing over the first and second channel patterns in a first direction. The gate electrode may include first and second outer gate electrodes, which are provided on the uppermost ones of the first and second semiconductor patterns, respectively, and each of which includes a first metal pattern, a second metal pattern thinner than the first metal pattern, and a filling metal pattern sequentially stacked. A third metal pattern may be further provided between the first metal pattern and the first semiconductor patterns. The third and second metal patterns may include p- and n-type work function metals, respectively. The first and second metal patterns of the second outer gate electrode may have coplanar topmost surfaces.

Description

Claims

1. A semiconductor device, comprising: a first active pattern and a second active pattern respectively on a first region and a second region of a substrate;a first channel pattern on the first active pattern, the first channel pattern including first semiconductor patterns stacked to be spaced apart from each other;a second channel pattern on the second active pattern, the second channel pattern including second semiconductor patterns stacked to be spaced apart from each other; anda gate electrode on the first channel pattern and the second channel pattern, the gate electrode extending in a first direction,wherein the gate electrode includes a first outer gate electrode and a second outer gate electrode on a top surface of an uppermost one of the first semiconductor patterns and a top surface of an uppermost one of the second semiconductor patterns, respectively, each of the first outer gate electrode and the second outer gate electrode including a first metal pattern, a second metal pattern on the first metal pattern, and a filling metal pattern on the second metal pattern,wherein the first outer gate electrode further includes a third metal pattern between the first metal pattern and the first semiconductor patterns, the third metal pattern including a p-type work function metal,wherein the second metal pattern includes an n-type work function metal, a thickness of the first metal pattern being smaller than a thickness of the second metal pattern, andwherein a topmost surface of the first metal pattern of the second outer gate electrode is coplanar with a topmost surface of the second metal pattern of the second outer gate electrode.

2. The semiconductor device as claimed in claim 1, further comprising a gate insulating layer between the gate electrode and the first semiconductor patterns and the second semiconductor patterns, wherein the gate insulating layer includes an interface layer and a high-k dielectric layer, the gate insulating layer enclosing the first semiconductor patterns and the second semiconductor patterns, andwherein a topmost surface of the high-k dielectric layer is coplanar with the topmost surface of the first metal pattern.

3. The semiconductor device as claimed in claim 2, wherein the second metal pattern is spaced apart from an inner side surface of the high-k dielectric layer by the first metal pattern.

4. The semiconductor device as claimed in claim 1, wherein a lowermost level of a top surface of the first outer gate electrode is at a substantially same level as a lowermost level of a top surface of the second outer gate electrode.

5. The semiconductor device as claimed in claim 1, wherein the second outer gate electrode has a flat top surface.

6. The semiconductor device as claimed in claim 1, wherein the first metal pattern includes titanium nitride, and a thickness of the first metal pattern is smaller than a thickness of the third metal pattern.

7. The semiconductor device as claimed in claim 6, wherein: the second metal pattern includes at least one of aluminum-doped titanium carbide, aluminum-doped tantalum carbide, aluminum-doped vanadium carbide, silicon-doped titanium carbide, and silicon-doped tantalum carbide, andthe third metal pattern includes at least one of titanium nitride, tantalum nitride, titanium oxynitride, titanium silicon nitride, titanium aluminum nitride, tungsten carbon nitride, and molybdenum nitride.

8. The semiconductor device as claimed in claim 1, wherein the third metal pattern has a recessed topmost surface, the recessed topmost surface being at a level lower than a topmost surface of the first outer gate electrode, and the first metal pattern covering the recessed topmost surface.

9. The semiconductor device as claimed in claim 1, wherein a thickness of each of the first metal pattern and the second metal pattern of the first outer gate electrode is substantially equal to a thickness of each of the first metal pattern and the second metal pattern of the second outer gate electrode.

10. The semiconductor device as claimed in claim 1, wherein: the gate electrode further includes first inner gate electrodes in spaces between the first semiconductor patterns, and second inner gate electrodes in spaces between the second semiconductor patterns,each of the first inner gate electrodes includes the third metal pattern, andeach of the second inner gate electrodes includes the first metal pattern and the second metal pattern.

11. A semiconductor device, comprising: a substrate including a first region and a second region adjacent to each other in a first direction;a first active pattern on the first region and a second active pattern on the second region;a first channel pattern on the first active pattern and a second channel pattern on the second active pattern, the first channel pattern including first semiconductor patterns, which are stacked to be spaced apart from each other, and the second channel pattern including second semiconductor patterns, which are stacked to be spaced apart from each other;a gate electrode crossing the first channel pattern and the second channel pattern, the gate electrode extending in the first direction, and the gate electrode including a first gate portion on the first region and a second gate portion on the second region; anda gate insulating layer between the gate electrode and each of the first channel pattern and the second channel pattern,wherein each of the first gate portion and the second gate portion includes a first metal pattern, a second metal pattern on the first metal pattern, and a filling metal pattern on the second metal pattern,wherein the first gate portion further includes a third metal pattern between the first metal pattern and the first channel pattern, the third metal pattern including a p-type work function metal,wherein the second metal pattern includes an n-type work function metal, the second metal pattern being spaced apart from an inner side surface of the gate insulating layer by the first metal pattern,wherein a thickness of the first metal pattern is smaller than a thickness of each of the second metal pattern and the third metal patterns, andwherein a topmost surface of the first metal pattern is flat.

12. The semiconductor device as claimed in claim 11, wherein the third metal pattern is between the first semiconductor patterns, and the first metal pattern and the second metal pattern are between the second semiconductor patterns.

13. The semiconductor device as claimed in claim 11, wherein the topmost surface of the first metal pattern is at a level higher than a topmost surface of the third metal pattern.

14. The semiconductor device as claimed in claim 11, wherein the first region is a PMOSFET region, and the second region is an NMOSFET region.

15. The semiconductor device as claimed in claim 11, wherein the topmost surface of the first metal pattern is coplanar with a topmost surface of the second metal pattern.

16. A semiconductor device, comprising: a first active pattern and a second active pattern on a first region and a second region of a substrate, respectively, the first region and the second regions being PMOSFET and NMOSFET regions, respectively;a device isolation layer filling a trench between the first active pattern and the second active pattern;a first channel pattern on the first active pattern and a second channel pattern on the second active pattern, the first channel pattern including first semiconductor patterns, which are stacked to be spaced apart from each other, and the second channel pattern including second semiconductor patterns, which are stacked to be spaced apart from each other;a gate electrode crossing the first channel pattern and the second channel pattern, the gate electrode extending in a first direction and including: first inner gate electrodes between the first semiconductor patterns,second inner gate electrodes between the second semiconductor patterns,a first outer gate electrode on a top surface of an uppermost one of the first semiconductor patterns, anda second outer gate electrode on a top surface of an uppermost one of the second semiconductor patterns;a gate insulating layer between the gate electrode and each of the first channel pattern and the second channel pattern, the gate insulating layer including an interface layer enclosing the first and second semiconductor patterns and a high-k dielectric layer on the interface layer;a gate capping pattern on a top surface of the gate electrode;a first interlayer insulating layer on the gate capping pattern;a gate contact penetrating the first interlayer insulating layer and coupled to the gate electrode;a second interlayer insulating layer on the first interlayer insulating layer;a first metal layer in the second interlayer insulating layer;a third interlayer insulating layer on the second interlayer insulating layer; anda second metal layer in the third interlayer insulating layer,wherein each of the first outer gate electrode and the second outer gate electrode includes a first metal pattern, a second metal pattern on the first metal pattern, and a filling metal pattern on the second metal pattern,wherein the first outer gate electrode further includes a third metal pattern between the first metal pattern and the first semiconductor patterns, the third metal pattern including a p-type work function metal,wherein the second metal pattern includes an n-type work function metal,wherein a thickness of the first metal pattern is smaller than a thickness of each of the second metal pattern and the third metal pattern, andwherein a topmost surface of the first metal pattern of the second outer gate electrode is coplanar with a topmost surface of the second metal pattern of the second outer gate electrode.

17. The semiconductor device as claimed in claim 16, wherein the first metal pattern includes titanium nitride, the second metal pattern includes aluminum-doped titanium carbide, and the third metal pattern includes titanium aluminum nitride.

18. The semiconductor device as claimed in claim 16, wherein the second metal pattern is spaced apart from an inner side surface of the high-k dielectric layer by the first metal pattern.

19. The semiconductor device as claimed in claim 16, wherein the third metal pattern has a recessed topmost surface, the recessed topmost surface being at a level lower than a topmost surface of the first outer gate electrode, and the first metal pattern covering the recessed topmost surface.

20. The semiconductor device as claimed in claim 16, wherein a topmost surface of the high-k dielectric layer is coplanar with the topmost surface of the first metal pattern and the topmost surface of the second metal pattern.