The present invention relates to a semiconductor device.
Conventionally, there has been known a semiconductor device having a so-called shield gate structure (see patent literature 1, for example). As shown in
The conventional semiconductor device 900 includes the shield electrode 930 disposed in the inside of the trench 922 and positioned between the gate electrode 926 and the bottom of the trench 922. Accordingly, a distance from the gate electrode 926 to the bottom of the trench 922 becomes long and hence, a gate-drain capacitance CGD (see
PTL 1: Japanese Patent No. 4790908
However, from studies which the inventors of the present invention have made, it has been found that, in the conventional semiconductor device 900, there arises a case where ringing occurs or a high surge voltage is generated at the time of turning off a switch. Accordingly, the inventors of the present invention have considered the use of a high resistance shield electrode (for example, a shield electrode having higher resistance than the source electrode or the gate electrode) as the shield electrode (see
However, when the high resistance shield electrode is used as the shield electrode as described above, in the latter half of a switching period, a difference in potential is generated along a line of the shield electrode and hence, a gate voltage VGS rises through a gate-source capacitance CGS thus giving rise to a drawback that an erroneous operation (self turn-on) is liable to occur (see symbol A in
On the other hand, when a low resistance shield electrode is used as the shield electrode (see
The present invention has been made to overcome such drawbacks, and it is an object of the present invention to provide a semiconductor device which can suppress ringing which occurs at the time of turning off a switch, and can lower a surge voltage at the time of turning off a switch. The semiconductor device can also suppress an erroneous operation (self turn-on) which occurs due to rising of a gate voltage VGS at the time of turning off a switch and, at the same time, the semiconductor device can reduce a drawback that a switching loss is increased.
[1] According to one aspect of the present invention, there is provided a semiconductor device which includes:
a semiconductor base body having a drain region of a first-conductive-type, a drift region of the first-conductive-type disposed adjacently to the drain region, a base region of a second-conductive-type disposed adjacently to the drift region, and a source region of the first-conductive-type disposed adjacently to the base region;
a trench formed in the inside of the semiconductor base body, having a bottom disposed adjacently to the drift region and a side wall disposed adjacently to the base region and the drift region, and formed into a stripe pattern as viewed in a plan view;
a gate electrode disposed in the inside of the trench and opposedly facing the base region with a gate insulating film interposed therebetween on a portion of the side wall;
a shield electrode disposed in the inside of the trench and positioned between the gate electrode and the bottom of the trench;
an electric insulating region disposed in the inside of the trench, the electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along the side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom;
a source electrode formed above the semiconductor base body, electrically connected to the source region, and electrically connected to the shield electrode on at least one of both end portions of the trench as viewed in a plan view; and
a drain electrode formed adjacently to the drain region, wherein
the shield electrode has a high resistance region positioned at an end portion of the trench which is electrically connected to the source electrode out of both end portions of the trench as viewed in a plan view, and a low resistance region positioned at a position in front of the high resistance region as viewed from the source electrode.
The above-mentioned high resistance region can be also referred to as a first region positioned at both end portions of the trench as viewed in a plan view and having a first resistance, and the above-mentioned low resistance region can be also referred to as a second region positioned at a position sandwiched by the first regions and having a second resistance lower than the first resistance.
[2] In the semiconductor device of the present invention, it is preferable that both the high resistance region and the low resistance region be made of a same semiconductor material containing a dopant, and dopant concentration in the low resistance region be higher than dopant concentration in the high resistance region.
[3] In the semiconductor device of the present invention, it is preferable that the high resistance region and the low resistance region be made of different materials respectively, and electric resistivity of a material for forming the low resistance region be lower than electric resistivity of a material for forming the high resistance region.
[4] In the semiconductor device of the present invention, it is preferable that both the high resistance region and the low resistance region be made of a same material, and a cross-sectional area of the high resistance region taken along a plane orthogonal to a longitudinal direction of the trench be smaller than a cross-sectional area of the low resistance region taken along a plane orthogonal to a longitudinal direction of the trench.
[5] In the semiconductor device of the present invention, it is preferable that both the high resistance region and the low resistance region be made of a same semiconductor material containing a dopant, and the low resistance region has a high concentration dopant region containing a dopant having higher concentration than a dopant in the high resistance region and extending along a longitudinal direction of the trench.
[6] In the semiconductor device of the present invention, it is preferable that both the high resistance region and the low resistance region have a high concentration dopant region made of a same semiconductor material containing a dopant and extending along a longitudinal direction of the trench, and a cross-sectional area of the high concentration dopant region in the high resistance region taken along a plane orthogonal to a longitudinal direction of the trench be smaller than a cross-sectional area of the high concentration dopant region in the low resistance region taken along a plane orthogonal to a longitudinal direction of the trench.
[7] In the semiconductor device of the present invention, it is preferable that in the shield electrode, the shield electrode extending adjacently to a side of a chip as viewed in a plan view be wholly formed of the high resistance region.
[8] In the semiconductor device of the present invention, it is preferable that in the shield electrode, the shield electrode extending adjacently to a side of a gate pad as viewed in a plan view be configured such that a portion of the shield electrode extending adjacently to the side of the gate pad as viewed in a plan view is formed of the high resistance region.
[9] In the semiconductor device of the present invention, it is preferable that a contact structure for electrically connecting the shield electrode and the source electrode be formed on an end portion of the shield electrode connected to the source electrode out of both end portions of the shield electrode.
[10] In the semiconductor device of the present invention, it is preferable that the contact structure be formed in a second low resistance region having a lower resistance than the high resistance region.
[11] In the semiconductor device of the present invention, it is preferable that the source electrode be electrically connected to the shield electrode on both end portions of the trench as viewed in a plan view, the high resistance region be positioned on both end portions of the trench as viewed in a plan view, and the low resistance region be positioned at a position sandwiched by the high resistance regions.
According to the semiconductor device of the present invention, the semiconductor device includes the shield electrode having the high resistance region positioned at the end portion of the trench electrically connected to the source electrode out of both end portions of the trench, and the low resistance region positioned at the position in front of the high resistance region as viewed from the source electrode, as the shield electrode (see
Due to the presence of the low resistance region, a difference in potential of the shield electrode generated along a line of the shield electrode can be lowered whereby it is possible to suppress the occurrence of a phenomenon that VGS rises in the latter half of a switching period resulting in an erroneous operation (see symbol A in
Further, due to the presence of the high resistance region positioned on the end portion of the trench electrically connected to the source electrode out of both end portions of the trench, a potential generated in the shield electrode is increased and hence, the extension of a depletion layer in the drift region via Cds can be suppressed. At this stage of the operation, a switching operation of the MOSFET is gradually shifted from the end portion of the trench electrically connected to the source electrode out of both end portions of the trench to the center of the trench. Accordingly, the extension of the depletion layer at the end portion of the trench electrically connected to the source electrode out of both end portions of the trench can be suppressed, leading to the reduction of an adverse effect caused by a surge voltage from the outside.
In
Hereinafter, a semiconductor device according to the present invention is described in conjunction with embodiments shown in the drawings.
As shown in
The semiconductor device 100 according to the embodiment 1 is a power MOSFET.
In the semiconductor device 100 according to the embodiment 1, the shield electrode 130 has high resistance regions 130a positioned at both end portions of the trench 122 as viewed in a plan view, and a low resistance region 130b positioned at a position sandwiched by the high resistance regions 130a. Both the high resistance regions 130a and the low resistance region 130b are made of the same semiconductor material containing a dopant, and dopant concentration in the low resistance region 130b is higher than dopant concentration in the high resistance region 130a.
In the semiconductor device 100 according to the embodiment 1, in the shield electrode 130, the shield electrode extending adjacently to a side of a chip as viewed in a plan view is wholly formed of the high resistance region 130a. In the shield electrode 130, the shield electrode extending adjacently to a side of a gate pad 138 as viewed in a plan view is configured such that a portion of the shield electrode extending adjacently to the side of the gate pad 138 as viewed in a plan view is formed of the high resistance region 130a.
A thickness of the n+-type drain region 112 is set to a value which falls within a range of from 50 μm to 500 μm (for example, 350 μm), and dopant concentration in the n+-type drain region 112 is set to 1×1018cm−3 to 1×1020cm−3 (for example, 1×1019cm−3). A thickness of the n−-type drift region 114 is set to a value which falls within a range of from 10 μm to 50 μm (for example, 15 μm), and dopant concentration in the n−-type drift region 114 is set to 1×1014cm−3 to 1×1017cm−3 (for example, 1×1015cm−3). A thickness of the p-type base region 116 is set to a value which falls within a range of from 2 μm to 10 μm (for example, 5 μm), and dopant concentration in the p-type base region 116 is set to 1×1016cm−3 to 1×1018cm−3 (for example, 1×1017cm−3).
A depth of the trench 122 is set to a value which falls within a range of from 4 μm to 20 μm (for example, 12 μm), and a pitch of the trench 122 is set to a value which falls within a range of from 3 μm to 15 μm (for example, 10 μm).
The gate insulating film 124 is formed of a silicon dioxide film formed by a thermal oxidation method, for example, and a thickness of the gate insulating film 124 is set to a value which falls within a range of from 20 nm to 200 nm (for example, 100 nm).
The gate electrode 126 is formed of a low resistance polysilicon formed by a CVD method, for example, and a thickness of the gate electrode 126 is set to a value which falls within a range of from 2 μm to 10 μm (for example, 5 μm).
The shield electrode 130 is, as described previously, disposed in the inside of the trench 122 and positioned between the gate electrode 126 and the bottom of the trench 122. The high resistance region 130a is made of a high resistance polysilicon formed by a CVD method, for example, and a thickness of the high resistance region 130a is set to a value which falls within a range of from 1 μm to 4 μm (for example, 3 μm). The low resistance region 130b is made of a low resistance polysilicon formed by a CVD method, for example, and a thickness of the low resistance region 130b is set to a value which falls within a range of from 1 μm to 4 μm (for example, 3 μm).
A distance between the shield electrode 130 and the gate electrode 126 is set to a value which falls within a range of from 1 μm to 3 μm (for example, 2 μm), a distance between the shield electrode 130 and the bottom of the trench 122 is set to a value which falls within a range of from 1 μm to 3 μm (for example, 2 μm), and a distance between the shield electrode 130 and the side wall of the trench 122 is set to a value which falls within a range of from 1 μm to 3 μm (for example, 2 μm).
A depth of the n+-type source region 118 is set to a value which falls within a range of from 1 μm to 3 μm (for example, 2 μm), and dopant concentration in the n+-type source region 118 is set to 1×1018cm−3 to 1×1020cm−3 (for example, 2×1019cm−3).
A depth of a p+-type contact region 120 is set to a value which falls within a range of from 1 μm to 3 μm (for example, 2 μm), and dopant concentration in the p+-type contact region 120 is set to 1×1018cm−3 to 1×1020cm−3 (for example, 2×1019cm−3).
An interlayer insulating film 132 is formed of a silicon dioxide film formed by a CVD method, for example, and a thickness of the interlayer insulating film 132 is set to a value which falls within a range of from 0.5 μm to 3 μm (for example, 1 μm).
The source electrode 134 is formed of an Al film or an Al alloy film (for example, an AlSi film), for example, and a thickness of the source electrode 134 is set to a value which falls within a range of from 1 μm to 10 μm (for example, 3 μm).
The drain electrode 136 is formed of a lamination film in which Ti, Ni, and Au are laminated in this order, and a thickness of the drain electrode 136 is set to a value which falls within a range of from 0.2 μm to 1.5 μm (for example, 1 μm).
In the semiconductor device 100 according to the embodiment 1, electric resistivity, dopant concentration and the like of the high resistance region 130a and the low resistance region 130b are not particularly limited. However, it is preferable that electric resistivity of the high resistance region 130a be 10 times or more as large as electric resistivity of the low resistance region 130b. It is more preferable that electric resistivity of the high resistance region 130a be 100 times or more as large as electric resistivity of the low resistance region 130b. Lengths (one-side lengths) of the high resistance region 130a and the low resistance region 130b along the longitudinal direction of the trench 122 are also not particularly limited. However, it is preferable that the length of the high resistance region 130a be 0.2 times or less as large as the length of the low resistance region 130b. It is more preferable that the length of the high resistance region 130a be 0.1 times or less as large as the length of the low resistance region 130b.
According to the semiconductor device 100 of the embodiment 1, the semiconductor device 100 includes the shield electrode 130 having the high resistance regions 130a positioned at both end portions of the trench and the low resistance region 130b positioned at the position sandwiched by the high resistance regions 130a, as the shield electrode 130 (see
Further, the resistance value of the resistance Rb in the low resistance region 130b (see
Due to the presence of the high resistance regions 130a positioned on both end portions of the trench 122, a potential generated in the shield electrode 130 is increased and hence, the extension of a depletion layer in the n−-type drift region 114 via Cds can be suppressed. At this stage of the operation, a switching operation of the MOSFET is gradually shifted from both end portions of the trench 122 to the center of the trench 122. Accordingly, the extension of the depletion layer at both end portions of the trench 122 can be suppressed, leading to the reduction of an adverse effect caused by a surge voltage from the outside.
According to the semiconductor device 100 according to the embodiment 1, in the shield electrode 130, the shield electrode 130 extending adjacently to the side of the chip as viewed in a plan view is wholly formed of the high resistance region 130a. With such a configuration, in the shield electrode, a potential generated in the shield electrode 130 becomes higher and hence, the extension of the depletion layer of the n−-type drift region 114 via Cds can be suppressed more effectively. Accordingly, an adverse effect caused by a surge voltage from the outside of the chip can be reduced.
According to the semiconductor device 100 of the embodiment 1, in the shield electrode 130, the shield electrode 130 extending adjacently to the side of the gate pad 138 as viewed in a plan view is configured such that a portion of the shield electrode 130 extending adjacently to the side of the gate pad 138 as viewed in a plan view is formed of the high resistance region 130a. With such a configuration, in the shield electrode, a potential generated in the shield electrode 130 becomes higher and hence, the extension of the depletion layer of the n−-type drift region 114 via Cds can be suppressed more effectively. Accordingly, an adverse effect caused by a surge voltage from the gate pad 138 can be reduced.
The semiconductor device 100 according to the embodiment 1 includes, as the shield electrode 130 thereof, a shield electrode in which both the high resistance regions 130a and the low resistance region 130b are made of the same semiconductor material containing a dopant, and dopant concentration in the low resistance region 130b is higher than dopant concentration in the high resistance region 130a. Accordingly, by setting a doping amount of a dopant to a suitable value, it is possible to relatively easily set electric resistivity of the high resistance region 130a and electric resistivity of the low resistance region 130b to desired values.
The semiconductor device 100 according to the embodiment 1 can be manufactured by a manufacturing method having the following manufacturing steps (method of manufacturing a semiconductor device according to the embodiment 1).
As shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Next, by performing etching back of the high resistance polysilicon film 130a′ and the low resistance polysilicon film 130b′, the high resistance polysilicon film 130a′ and the low resistance polysilicon film 130b′ are removed in a state where the high resistance polysilicon film 130a′ and the low resistance polysilicon film 130b′ having predetermined thicknesses are made to remain.
By performing such a step, the high resistance region 130a and the low resistance region 130b are formed in the inside of the trench 122, and as a whole, the shield electrode 130 having the high resistance region 130a and the low resistance region 130b is formed (see
Then, a silicon oxide film having a predetermined thickness is formed on the high resistance region 130a and the low resistance region 130b in the inside of the trench 122 by a CVD method, and such a silicon oxide film forms a top portion of the electric insulating region 128 (see
Next, as shown in
Then, as shown in
Then, the silicon oxide film 124′ formed on the surface of the semiconductor base body 110 is removed. Next, a PSG film is formed from a surface side of the semiconductor base body 110 by a gas phase method. Thereafter, a thermally oxidized film of silicon and the PSG film are removed by etching while a predetermined upper portion of the gate electrode 126 remains. By performing such a step, as shown in
Then, as shown in
The semiconductor device 100 according to the embodiment 1 can be manufactured through the above-mentioned steps.
A semiconductor device according to an embodiment 2 basically has substantially the same configuration as the semiconductor device 100 according to the embodiment 1. However, the semiconductor device according to the embodiment 2 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of a shield electrode 130. That is, as shown in
As a material for forming the high resistance region 130a, for example, high resistance polysilicon which is formed by a CVD method can be used. As a material for forming the low resistance region 130b, metal having a high-melting point (for example, W, Mo, Ta, Nb or the like) or other metals (for example, Cu or the like) can be used.
In this manner, the semiconductor device according to the embodiment 2 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of the shield electrode 130. However, the semiconductor device according to the embodiment 2 includes, as the shield electrode 130, the shield electrode formed of the high resistance regions 130a positioned at both end portions of the trench 122 as viewed in a plan view and the low resistance region 130b positioned at the position sandwiched by the high resistance regions 130a. Accordingly, in the same manner as the semiconductor device 100 according to the embodiment 1, it is possible to realize the suppression of ringing and a surge voltage, the suppression of an erroneous operation, the prevention of the increase of a switching loss, and the reduction of an adverse effect caused by a surge voltage from the outside.
According to the semiconductor device according to the embodiment 2, by suitably selecting a material for forming the high resistance region 130a and a material for forming the low resistance region 130b, it is possible to select electric resistivity of the high resistance region 130a and electric resistivity of the low resistance region 130b within a wide range.
A semiconductor device 102 according to an embodiment 3 basically has substantially the same configuration as the semiconductor device 100 according to the embodiment 1. However, the semiconductor device 102 according to the embodiment 3 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of a shield electrode 130. That is, as shown in
In this manner, the semiconductor device 102 according to the embodiment 3 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of the shield electrode 130. However, the semiconductor device 102 according to the embodiment 3 includes, as the shield electrode 130, the shield electrode formed of the high resistance regions 130a positioned at both end portions of the trench 122 as viewed in a plan view and the low resistance region 130b positioned at the position sandwiched by the high resistance regions 130a. Accordingly, in the same manner as the semiconductor device 100 according to the embodiment 1, it is possible to realize the suppression of ringing and a surge voltage, the suppression of an erroneous operation, the prevention of the increase of a switching loss, and the reduction of an adverse effect caused by a surge voltage from the outside.
As shown in
A semiconductor device according to an embodiment 4 basically has substantially the same configuration as the semiconductor device 100 according to the embodiment 1. However, the semiconductor device according to the embodiment 4 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of a shield electrode. That is, as shown in
In this manner, the semiconductor device according to the embodiment 4 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of the shield electrode 130. However, the semiconductor device according to the embodiment 4 includes, as the shield electrode 130, the shield electrode formed of the high resistance regions 130a positioned at both end portions of the trench 122 as viewed in a plan view and the low resistance region 130b positioned at the position sandwiched by the high resistance regions 130a. Accordingly, in the same manner as the semiconductor device 100 according to the embodiment 1, it is possible to realize the suppression of ringing and a surge voltage, the suppression of an erroneous operation, the prevention of the increase of a switching loss, and the reduction of an adverse effect caused by a surge voltage from the outside.
The semiconductor device according to the embodiment 4 can be manufactured by a method substantially equal to the method of manufacturing the semiconductor device according to the embodiment 1 except for steps of forming the high resistance regions 130a and the low resistance region 130b (see
A semiconductor device according to an embodiment 5 basically has substantially the same configuration as the semiconductor device 100 according to the embodiment 1. However, the semiconductor device according to the embodiment 5 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of a shield electrode 130. That is, as shown in
In this manner, the semiconductor device according to the embodiment 5 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of the shield electrode 130. However, the semiconductor device according to the embodiment 5 includes, as the shield electrode 130, the shield electrode formed of the high resistance regions 130a positioned at both end portions of the trench 122 as viewed in a plan view and the low resistance region 130b positioned at the position sandwiched by the high resistance regions 130a. Accordingly, in the same manner as the semiconductor device 100 according to the embodiment 1, it is possible to realize the suppression of ringing and a surge voltage, the suppression of an erroneous operation, the prevention of the increase of a switching loss, and the reduction of an adverse effect caused by a surge voltage from the outside.
The semiconductor device according to the embodiment 5 can be manufactured by a method substantially equal to the method of manufacturing the semiconductor device according to the embodiment 1 except for steps of forming the high resistance regions 130a and the low resistance region 130b (see
In the semiconductor devices according to the embodiments 1 to 5 of the present invention, as shown in
A semiconductor device 105 according to an embodiment 6 basically has substantially the same configuration as the semiconductor device 100 according to the embodiment 1. However, the semiconductor device 105 according to the embodiment 6 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of a shield electrode 130 extending adjacently to a side of a chip as viewed in a plan view. That is, as shown in
In this manner, the semiconductor device 105 according to the embodiment 6 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of the shield electrode 130 extending adjacently to the side of the chip as viewed in a plan view. However, the semiconductor device 105 according to the embodiment 6 includes, as the shield electrode 130, the shield electrode formed of the high resistance regions 130a positioned at both end portions of the trench 122 as viewed in a plan view and the low resistance region 130b positioned at the position sandwiched by the high resistance regions 130a. Accordingly, in the same manner as the semiconductor device 100 according to the embodiment 1, it is possible to realize the suppression of ringing and a surge voltage, the suppression of an erroneous operation, and the prevention of the increase of a switching loss.
A semiconductor device 106 according to an embodiment 7 basically has substantially the same configuration as the semiconductor device 100 according to the embodiment 1. However, the semiconductor device 106 according to the embodiment 7 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of a gate finger for connecting a gate pad 138 and a gate electrode 126 to each other. That is, although not shown in the drawings, the semiconductor device 100 according to the embodiment 1 includes, as a gate finger, a gate finger 142 extending from a gate pad 138 along an outer peripheral portion of a chip. On the other hand, the semiconductor device 106 according to the embodiment 7 includes, as shown in
In this manner, the semiconductor device 106 according to the embodiment 7 differs from the semiconductor device 100 according to the embodiment 1 with respect to the configuration of the gate finger. However, the semiconductor device 106 according to the embodiment 7 includes, as the shield electrode 130, the shield electrode formed of high resistance regions 130a positioned at both end portions of the trench 122 as viewed in a plan view and a low resistance region 130b positioned at a position sandwiched by the high resistance regions 130a. Accordingly, in the same manner as the semiconductor device 100 according to the embodiment 1, it is possible to realize the suppression of ringing and a surge voltage, the suppression of an erroneous operation, the prevention of the increase of a switching loss, and the reduction of an adverse effect caused by a surge voltage from the outside.
Further, the semiconductor device 106 according to the embodiment 7 can also acquire an advantageous effect that an adverse effect caused by a surge voltage from the second gate finger 144 can be reduced.
Although the present invention has been described based on the above-mentioned embodiments heretofore, the present invention is not limited to the above-mentioned embodiments. The present invention can be carried out in various modes without departing from the gist of the present invention, and the following modifications also are conceivable, for example.
(1) In the above-mentioned embodiment 1, for forming the high resistance region 130a, for example, high resistance polysilicon which is formed by a CVD method is used and, for forming the low resistance region 130b, for example, low resistance polysilicon which is formed by a CVD method is used. However, the present invention is not limited to these materials. Materials other than these materials may be used.
(2) In the above-mentioned embodiment 2, for forming the high resistance region 130a, for example, high resistance polysilicon which is formed by a CVD method is used and, for forming the low resistance region 130b, metal having a high-melting point (for example, W, Mo, Ta, Nb or the like) or other metals (for example, Cu or the like) is used. However, the present invention is not limited to these materials. Materials other than these materials may be used.
(3) In the above-mentioned embodiment 1, the description has been made with respect to the case where the semiconductor device 100 is a power MOSFET. However, the present invention is not limited to such a case. The present invention is applicable to various other devices besides the power MOSFET without departing from the gist of the present invention.
(4) The semiconductor device 100 according to the embodiment 1 can be manufactured also by a method different from the method described in the embodiment 1. For example, a shield electrode 130 and a gate electrode 126 are formed and, thereafter, an n+-type source region 118 and a p+-type contact region 120 may be formed. Further, for example, a shield electrode 130 and a gate electrode 126 are formed and, thereafter, an n+-type source region 118, a p-type base region 116 and a p+-type contact region 120 may be formed.
(5) In the above-mentioned respective embodiments, the source electrode is electrically connected to the shield electrode on both end portions of the trench as viewed in a plan view, the high resistance regions are positioned at both end portions of the trench as viewed in a plan view, and the low resistance region is positioned at a position sandwiched by the high resistance regions. However, the present invention is not limited to such a configuration. For example, the source electrode may be electrically connected to the shield electrode on one of both end portions of the trench as viewed in a plan view, the high resistance region may be positioned at the end portion of the trench electrically connected to the source electrode out of both end portions of the trench as viewed in a plan view, and the low resistance region may be positioned at a position in front of the high resistance region as viewed from the source electrode.
The present application is a National Phase of International Application Number PCT/JP2016/050957, filed Jan. 14, 2016.
Filing Document | Filing Date | Country | Kind |
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PCT/JP2016/050957 | 1/14/2016 | WO | 00 |