This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. JP2008-027246 filed on Feb. 7, 2008, the entire content of which is hereby incorporated by reference.
The present invention relates to a semiconductor device with high precision, and a method of manufacturing the same.
A further enhancement to the precision of power ICs, such as voltage detectors (VDs), voltage regulators (VRs), and lithium battery protection ICs, is required in recent years. Variances, which occur in a wafer manufacturing process (wafer process), are usually smoothed by trimming of fuses made of polysilicon with a laser or the like in a wafer testing process (assembly and testing process) to obtain a uniform characteristic value in order to accomplish high precision.
Even in a chip that has achieved high precision in this way a change in characteristics during a packaging process or a mounting process of a chip to a print board may still cause failure to meet product specifications in some cases. A change in characteristics of an element induced by thermal stress can be a cause of the change in characteristics along the packaging process or the board mounting process. Specifically, application of a stress to the semiconductor chip during these processes or a change in the application of the stress caused by applied heat, results in a change in resistance of a polysilicon resistor and a change in threshold voltage of a transistor.
JP 2000-124343 A, for example, discloses an invention for preventing these changes by adjusting the characteristics of a semiconductor product after the mounting to a print board. However, the cited invention shows a complicated process and it would be difficult to put into practice from the standpoint of cost. A simpler and more cost-effective method for stabilizing the characteristic value is required.
Problems to be solved by the invention of the present application are shown as is follows:
A change occurs in a characteristic of a high-precision semiconductor product during the assembling of the semiconductor product. A stress-induced change in the characteristics of an element is, as mentioned above, suspected to be a cause. For example, stress is applied to the semiconductor chip from a sealing resin and the resistance and characteristics of the element change through the piezo-resistance effect. In recent years, packaging a semiconductor chip in a small-sized package has become popular to meet requests for parts size reduction, and the thickness of semiconductor chips are becoming thinner in response. A thinner semiconductor chip is more severely distorted even from the same magnitude of stress, causing an apprehension of a greater change in the characteristics. The amount of the change in the characteristics is, in the case of the overcharge detection voltage of a lithium battery protection IC, for example, merely about a few mV, but this amount of change cannot be ignored in a high precision product.
On the other hand high precision semiconductor products accomplish high precision by utilizing identical characteristics between paired transistors. For instance, a current mirror circuit operates to make currents in two current paths equal to each other by utilizing the fact that the same amount of current flows in each of the paired P-channel MOS transistors. It is usually desirable to place the paired transistors as close as possible to each other or adjacent to each other if possible, within the semiconductor product, in order that the characteristics of the paired transistors do not differ from each other significantly. Aligning the channel directions of the paired transistors as well contributes to stabilizing the characteristics.
Application of a stress to such semiconductor products, however, causes a change in the characteristic value. In this case, if the applied stress is uneven between the paired transistors, that is, if different levels of stress are applied to paired transistors, the change in the characteristic value of one transistor differs from the change in the characteristic value of the other transistor.
An object of the present invention is to provide a semiconductor device capable of reducing such a stress-induced change in characteristic value. In order to solve the above-mentioned problems, the present invention employs the following means.
A semiconductor device is provided in which a change in characteristics is reduced by utilizing an angular dependency of a stress to an angle formed by a carrier traveling direction to cancel out stress-induced change.
Another means is to provide a semiconductor device in which application of stress is uniformed between paired transistors to reduce a change in characteristics.
With the present invention, a change in characteristic value during assembling of the semiconductor device can be reduced compared to the prior art, and the semiconductor device with even higher precision can be provided.
Embodiments of the present invention are described below with reference to
A semiconductor element is known to show a shift in resistance or in electric current value as a result of a change in carrier mobility caused by stress applied upon assembling through the piezo-resistance effect. In a MOS transistor, in particular, a mobility change causes a prominent shift in the mutual conductance Gm. Then, the change in characteristic value induced by stress upon assembling becomes too large to be ignored in a current mirror circuit and other circuits built on the premise that the Gm value between paired transistors is constant. Taking the current mirror circuit as an example here, a change in a characteristic value of the circuit occurs when an amount of shift in Gm, ΔGm, differs between paired transistors.
Accordingly, changes in characteristic value of paired transistors, here, shifts in Gm value, which have great influence over the circuit's characteristic value, are made equal to each other, to thereby cancel out changes in characteristic value of paired transistors. Measuring an amount of stress applied to a chip upon assembling or predicting through simulation, the layout is determined in a manner that makes the magnitude of stress applied to the element, as well as the angle formed by the stress and the channel, equal between the paired transistors. This equalizes shifts between the paired transistors, and ultimately reduces the characteristics change that occurs in assembling.
The piezo-resistance effect of a silicon semiconductor exhibits plane orientation dependency. A method of reducing a shift by utilizing the plane orientation dependency is employed here. The hole mobility in the <110> direction, for example, is known to change in opposite manners when the channel is perpendicular to the direction of stress and when parallel to the direction of the stress. This effect is utilized in designing a layout for forming one transistor such that channels are at right angles with each other, instead of keeping to one channel formation direction. Accordingly, the direction of one shift with respect to stress is opposite to the direction of another shift with respect to the stress, and hence the shifts are canceled out. A change in characteristic value is reduced as a result.
In an actual circuit, a plurality of transistors having varying channel angles are arranged to form more pairs in this manner. A high-precision circuit where the change in characteristic value is small is thus obtained.
As another embodiment, transistors are arranged in a manner illustrated in
In this arrangement, there are two or more angles each formed by a channel and stress which are similar to those in the above-mentioned embodiments, except that the angles here are not orthogonal to one another. However, arranging transistors diagonally in an intersecting manner reduces the shift in the end. This arrangement has an effect of giving equal average values of stress applied to paired transistors when there is stress distribution within the semiconductor chip. The effect ultimately reduces the change in characteristic value.
Number | Date | Country | Kind |
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JP2008-027246 | Feb 2008 | JP | national |