This application claims the benefit of Taiwan Patent Application serial No. 99138700, filed Nov. 10, 2010, the subject matter of which is incorporated herein by reference.
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device of chip on film package constraining lead extension to reduce or avoid lead residue left on puncher.
Semiconductor devices, such as semiconductor integrated circuits of various packages, have become the most important hardware foundations of modern information society.
Among various kinds of semiconductor devices, one kind of semiconductor devices has integrated circuit(s) formed on a flexible base; for example, semiconductor devices of COF (chip on film or chip on flex) package or TCP (tap carrier package) have multiple chips packaged on flexible film bases or tap bases to form multiple integrated circuits. Corresponding to each chip in each integrated circuit, leads are formed on conductive layer(s) of the base; when the chip is packaged on the base, the chip is coupled to the leads so the chip can communicate with other circuits via the leads. This kind of semiconductor devices has been broadly adopted; for example, driving integrated circuits (drivers) for liquid crystal display panels are formed on flexible bases.
For semiconductor devices of flexible base, because multiple integrated circuits are formed on a same base, each of the integrated circuits needs to be punched from the base by a puncher. The puncher punches according to a cut line corresponding to each integrated circuit; for known semiconductor devices of flexible base, leads of each integrated circuit extend across the corresponding cut line. However, by analysis of the invention, it is recognized that leads across the cut line will cause conductive residue left on the puncher while punched, and the conductive residue causes erroneous short circuit of different leads to impact normal operation of integrated circuit and to lower yield of semiconductor devices.
To address the issues, one objective of the invention is to provide a semiconductor device including a base and one or multiple integrated circuits. Each integrated circuit is formed on the base and includes a chip and a plurality of conductive leads set interior to a predetermined range which has a boundary, i.e., a cut line. In each integrated circuit, each lead extends from the chip toward the boundary to a bonding area inside the predetermined range with a predetermined distance separated away from the boundary.
In an embodiment of the invention, each integrated circuit further corresponds to a plurality of extension segments and a plurality of external segments. Each of the external segments is set exterior to the predetermined range, and is coupled to one of the leads through one of the extension leads extending across the boundary. A width of each extension segment is less than a width of each lead.
Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.
The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
Please refer to
When each integrated circuit 12 is separated from the base 14, the semiconductor device 10 will be placed on a puncher 11; a punch head 13 of the puncher 11 cuts each integrated circuit 12 off the base 14 along the cut line 18. As shown in
To address issues of residual remains of the semiconductor device 10, the invention provides a semiconductor with a better lead design. Please refer to
Each integrated circuit 22 of the semiconductor device 20 includes a chip 26 and multiple leads L1. The chip 26 is set inside a predetermined range 30 of the base 24; the predetermined range 30 is surrounded by a boundary 28, the boundary 28 can be a cut line of punch. Each lead L1 is set inside the predetermined range 30; each lead L1 is coupled to the chip 26 (e.g., to a pad of the chip 26), and extends from the chip 26 toward the boundary 28, so the chip 26 can be coupled to other external circuit(s) (e.g., other chip(s), integrated circuit(s) and/or circuit board(s), not shown) for exchanging signal/data and draining operation power.
However, as shown in
As each lead L1 of the integrated circuit 22 does not reach nor cross the boundary 28, each lead L1 will not contact the punch head of the puncher when the integrated circuit 22 is punched off from the base 24, and therefore no conductive residue will be left on the puncher. Accordingly, impact of lead residue for the integrated circuit 22 can be avoided; time and cost for punch process is also reduced since there in no need to frequently clean residue left on the puncher.
Please refer to
Each integrated circuit 32 of the semiconductor device 30 includes a chip 36 and multiple leads L2a and L2b; a boundary (e.g., a cut line of punch) 38 defines a range 40 where the integrated circuit 32 locates, the boundary 38 can be a cut line of punch. The chip 36, the leads L2a and L2b are set inside the range 40, each of the leads L2a and L2b is coupled (connected) to the chip 36, and extends from the chip 36 toward the boundary 38 to reach the bonding area R, so the chip 36 can be coupled to other external circuit(s) (e.g., other chip(s), integrated circuit(s) and/or circuit board(s), not shown) via the leads L2a and L2b for exchanging signal/data and draining operation power.
Similar to the embodiment of
For example, a test pad can be set on the external segment TP; when the semiconductor device 30 is manufactured but each integrated circuit 32 is not punched off, a tester can be coupled to the external segments TP of each integrated circuit 32 via probes for testing functions of the integrated circuit 32 by signal/data exchange. After the test, the integrated circuit 32 can be punched off along the boundary 38, and the external segments TP and portions of the extension segments TP are cut off the integrated circuit 32.
As shown in
In the embodiment of
Please refer to
To sum up, comparing to prior art, the invention effectively reduces or avoid conductive residue left on puncher, not only erroneous short circuit of integrated circuits owing to conductive residue can be prevented, but also efficiency of punch process can be increased.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Number | Date | Country | Kind |
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99138700 | Nov 2010 | TW | national |