Patent Application
20080089160
FIG, 5 is a timing chart to explain the operation of the semiconductor device according to the first embodiment of the present invention.
The preferred embodiments of the present invention will be explained below with reference to the accompanying drawings.
The general structure of a semiconductor device according to a first embodiment of the present invention is shown in
In this embodiment, a clock generator 110 is configured to generate internal clock signals after receiving clock signals CK, /CK and a clock enable signal CKE which are input externally. The internal clock signal is distributed to the command decoder 130, the control logic circuit 140, the column decoder 430, and the data latch circuit 600. The internal clock signal is used as a standard of the operating timing of each circuit.
The mode register 120 is configured to store various operation parameters such as burst length, latency and the like. The operation parameters are entered from the outside by making use of the address signals A0 to A13.
The command decoder 130 is configured to decode the operation commands such as a read command, a write command and the like. The operation commands are entered from outside by using a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, and a write enable signal /WE.
The control logic 140 is configured to generate various signals to execute operation command decoded by the command decoder 130.
The row address buffer 210 is configured to load, from among the address signals A0 to A13 and the bank address signals BA0, BA1, and BA2 inputted from outside, the row address signals to select a row in a memory cell array 300. This row address buffer 210 is provided with a refresh counter for stepping the row address in a refresh operation.
The column address buffer 220 is configured to load, from among the address signals A0 to A13 and the bank address signals BA0, BA1, and BA2 inputted from outside, the column address signals to select a column in the memory cell array 300. This column address buffer 220 is provided with a burst counter for counting the burst length.
The memory cell array 300 is configured by a matrix array of the memory cells in a matrix form. A plurality of word lines extends in its row direction. A plurality of bit lines extends in its column direction. The memory cells are located at the crossing points of the word lines and the bit lines. Only one cell is selected for each memory cell by selecting a word line and a bit line.
The row decoder 410 is configured to select only one word line from the memory cell array 300 based on the row address signal outputted from the row address buffer 210.
The sense amplifier 420 is configured to amplify weak data signals from the memory cell appeared on the bit line of the memory cell array 300.
The column decoder 430 is configured to select a bit line from the memory cell array 300. In this embodiment, the memory cell array 300, the row decoder 410, and the sense amplifier 420 are provided for each of the plurality of banks, and each bank is selected by the bank address signals BA0, BA1, and BA2.
The data control circuit 500 is configured to control the output order of the data readout from the memory cell array 300 in a burst mode.
The data latch circuit 600 is configured to store the input and output data temporarily.
The data input output buffer 700 is configured to supply data DQ to the external terminal and to receive data DQ from the external terminal.
The delayed locked loop (DLL) 800 is configured to delay the external clock signals CK and /CK, thereby generating the internal clock signals to decide operating timing of the data input output buffer 700.
The fuse-circuit 900 is configured to store data that is to define various circuit configurations such as data for defining a circuit configuration relating to the redundancy structure to remedy defects, data for defining a circuit configuration relating to the word organization of the output data, data for defining a circuit configuration relating to the voltage of the internal electrical power source, and data for defining a circuit configuration relating to the operating timing of the inner circuit.
The configuration of the fuse circuit 900 will be described in detail with reference to
In this embodiment, the fuse block 910 is configured with a plurality of unit blocks 910A. Each unit block 910A includes fuse element circuits 911-0, 911-1, 911-2, . . . , 911-N, 912, 913 and an AND gate circuit 914. Among these, a group of fuse element circuits 911 including the fuse element circuits 911-0, 911-1, 911-2, . . . , and 911-N is configured to store bit data B0, B1, B2, . . . , and BN (N is natural number) of a defective address. The fuse element circuit 912 is configured to store a flag data F indicating whether the data stored in the group of fuse element circuits 911 are valid or not. The defective addresses stored in the group of fuse element circuits 911 and the flag data F stored in the fuse element circuit 912 forms a data defining the circuit configuration relating to the redundancy structure.
The fuse element circuit 913 is configured to store a data S which expresses inhibition of programming of the group of fuse element circuits 911 and the fuse element circuit 912. The AND gate circuit 914 is configured to prohibit the control logic circuit 140 from programming the unit block 910A under the condition that the fuse element circuit 913 has been programmed and the data S has been stored in the fuse element circuit 913.
Although
The fuse block 920, which is used when the circuit configuration relating to the word organization and the like of the output data is defined, includes a plurality of unit blocks 920A. In this embodiment, the first unit bock 920A includes a fuse element circuit 921 to store a bit data W which defines the circuit configuration relating to the word organization, a fuse element circuit 923 to store program inhibition data which expresses inhibition of programming the fuse element circuit 921, and an AND gate circuit 924 to inhibit programming the fuse element circuit 921 on condition that a program inhibition data has been programmed and/or stored in the fuse element circuit 923. While other fuse element circuits 920A are configured similarly, in this embodiment, a data V which defines the circuit configuration relating to the voltage of the internal electrical power source is stored in the second fuse element circuit 920A, and a data T which defines the circuit configuration relating to the operating timing of the inner circuit is stored in the third fuse element circuit 920A.
Although
Next, the aforementioned fuse element circuits will be described in more detail with reference to
Programming operation of the anti-fuse AF is performed by applying a predetermined program voltage to the circuit between the gate and the source drain of the MOS transistor, thereby breaking down the gate oxide film thereof According to this anti-fuse AF, when the gate oxide film is broken down and thus the connection between the gate and source/drain form a short-circuit, the connection between the gate and the source/drain will never recover to the open state, so that the data written in the anti-fuse AF will never be lost.
That is, since such anti-fuses of a destructive type can be programmed only once, they are also called one-time type. When the anti-fuse is of this type, only a measure to prevent an unprogrammed anti-fuse from being programmed after the shipment of the product to customers is required to be provided, but not a measure to prevent data loss of already-programmed anti-fuse. In the present embodiment, once the fuse element circuits 913 and 923, in which the data indicating program inhibition are stored, are programmed, the data will never be lost thereafter, so that misprogramming the group of fuse element circuits 911, for example, including the pre-programmed anti-fuse can be prevented effectively.
According to the configuration of this fuse element circuit 911-0, a low level signal is outputted as a signal SAF in the pre-programmed state, and a high level signal is outputted as the signal SAF in the post-programmed state. Accordingly, by selectively programming the fuse element circuits 911-0, 911-1, 911-2, . . . , and 911-N, each bit data of a defective address can be written in the group of fuse element circuits 911.
Next, the operation of the semiconductor device of the present invention will be described with reference to a timing chart shown in
The special command MRS is decoded by the command decoder shown in FIG. 1, and based on the decoded result, the control logic 140 provides a control signal necessary for defining the redundancy structure to the fuse circuit 900. When the control signal is provided to the fuse circuit 900, the control logic circuit 140 outputs the program signals SB for programming the group of fuse element circuits 911 and the fuse element circuits 912 and 913, thereby programming the group of fuse element circuits 911 and the fuse element circuits 912 and 913 and then storing the defective address data, the flag data F, and the program inhibition data S respectively.
In a default state before the fuse element circuit 913 is programmed, since the signal SA outputted from the fuse element circuit 913 is of a high level, when the program signal SB is outputted from the control logic circuit 140, the AND gate circuit 914 passes through the program signal SB, and then provides them to the group of fuse element circuits 911 and the fuse element circuits 912 and 913 as the program signal SC. That is, when the command MRS is entered in a state in which the fuse element circuit 913 is not programmed, the group of fuse element circuits 911 and the fuse element circuits 912 and 913 are programmed.
At this time, if the signal SA becomes the low level as the program of the fuse element circuit 913 proceeds, the output signal SC of the AND gate circuit 914 to which the signal SA is inputted is fixed to the low level, so that programs of each fuse element circuit in the unit block circuit 910A will end in an incomplete state. Therefore, the AND gate circuit 914 forcibly maintains the program signal SA at the high level for a certain period of time from when the program signal SB is outputted from the control logic circuit 140 till all the fuse element circuits in the unit block circuit 910A are programmed completely.
Consequently, each bit data of the defective address and the flag data F are stored in the group of fuse element circuits 911 and in the fuse element circuit 912, respectively, and the program inhibition data S is stored in the fuse element circuit 913. In the example shown in
Next, the operation in a case in which the control logic circuit 140 outputs the program signal SB improperly due to the special command MRS entered improperly because an improper signal is impressed to the semiconductor device after the completion of the above-described program will be described with reference to
As a result, programming of the unit block 910A (the group of fuse element circuits 911 and the fuse element circuits 912 and 913) is inhibited, thereby preventing misprogramming based on an improper special command MRS, so that the following defective remedy operations are properly carried out. In the present embodiment, since an anti-fuse AF of destructive type is used, the data of the fuse element circuit 913 programmed once will never change. Thus, the signal SA is fixed stably at the low level, thereby preventing misprogramming thereafter in a stable manner.
While the operation of the fuse element circuit 900 has been described above exemplifying the case in which the redundancy structure is defined, the operation in a case in which the word organization is defined can also be described similarly. That is, when the word organization is defined, the fuse element circuits 921 and 923, which compose the unit block 920A of the fuse block 920 shown in
Next, an example of a test process of a case in which the modification of the word organization is carried out by the semiconductor device of the present invention will be described with reference to
First of all, a wafer test of a wafer, on which a semiconductor device provided with the above-described fuse circuit 900 including only one unit block 920A for modifying the word organization is formed, is carried out (step SI). Then, an assembly process to mount the semiconductor device on a package is operated (step S2) and a final screening test is carried out (step S3). After that when the word organization is modified according to the demand of customers (step S4; YES), a program is run on the fuse element circuit 921 of the unit block 920A for modifying the word organization to modify the word organization to ×4-bit organization (step S5), and then the fuse element circuit 923 is programmed and the data S for program inhibition is stored therein (step S6). As a result, a product with the word organization of ×4-bit organization can be obtained.
On the other hand, when the word organization is not modified in the above-described step S4 (step S4; NO), the fuse element circuit 921 is not programmed but the fuse element circuit 923 for program inhibition is programmed and the program inhibition data S is stored therein (step S7). As a result, a product with the word organization of ×8-bit organization can be obtained. According to the semiconductor device of the present invention, it is necessary to perform the final screening test only once.
In this flow chart, the above-described step S6 may be omitted because it is very rare that the already-programmed fuse element circuit 921 is restored to a high resistance state (pre-destruction state) from a low resistance state (post-destruction state), and the data will not be written over as a matter of fact. That is, even in the case in which the fuse element circuit 923 is not programmed, the data is unchanged even if the fuse element circuit 921 is misprogrammed by a customer after the shipment of the product, since the fuse element circuit 921 has already been programmed. Moreover, the fuse element circuit 923 is used in order to prevent misprogramming, so that even if a customer misprograms it after the shipment of the product, the word organization is not modified by the misprogramming, and will not have an effect on the functions of the product.
Next, an example of a test process of the semiconductor device of the present invention will be described with reference to
In this case, in the same manner as the above-described steps S1 to S3 shown in
Next, it is judged whether the operating timing of the inner circuits needs to be adjusted or not based on the result of the aforementioned final screening test (step S106). When the operating timing needs to be adjusted (step S106; YES), the fuse unit 920A for adjusting the operating timing is programmed (step S107). If the adjustment of the operating timing is not necessary (step S106; NO), the aforementioned step S107 is skipped and the process jumps to the next step.
Then, it is judged whether the defect caused by defective memory cells needs to be remedied or not based on the aforementioned final screening test (step S808). When the defect needs to be remedied (step S108; YES), the fuse unit 910A for defect remedy is programmed (step S109). If the remedy of the defect is not necessary (step S108; NO), the aforementioned step S109 is skipped and the process jumps to the next step.
Next, it is judged whether the word organization needs to be modified or not (step S110). When the word organization needs to be modified (step S110; YES), the fuse unit 910A for modifying the word organization is programmed (step S111). Then, all the fuse units 913 and 923 for program inhibition are programmed (step S112). Consequently, a non-defective product with ×4-bit organization, in which the voltage of the internal electrical power source and the operating timing were adjusted and the defect was remedied based on the results of the final screening test, can be obtained.
On the other hand, if the modification of the word organization is not necessary in the aforementioned step S110 (step S110; NO), the aforementioned step S111 is skipped, and all the fuse units 913 and 923 for program inhibition are programmed (step S113). Consequently, based on the results of the final screening test, the voltage of the internal electrical power source and the operating timing are adjusted and the defect is remedied. Accordingly, a product intended to have an improved yield rate can be obtained due to modification of the word organization, optimization of the voltage of the internal electrical power source and of the operating timing, and remedy of a defective memory.
Just for reference, a test process of a conventional device, which is structured so that the word organization is switched by a laser fuse or a bonding option, will be described with reference to
On the other hand, for those devices in which no defective bit is detected in the wafer test, the word organization is switched to ×8-bit organization by a laser fuse or a bonding option in the assembly process (step S24). Then, a final screening test as a product with ×8-bit organization is carried out (step S25), and if the test is passed, a product with ×8-bit organization can be obtained. Thus, according to the conventional devices, a final screening test according to respective word organization should be carried out, thereby making the test process complicated.
A second embodiment of the present invention will be described with reference to
A third embodiment of the present invention will be described with reference to
A fourth embodiment of the present invention will be described with reference to
Sharing one fuse element circuit 960 by a plurality of fuse blocks 920C in a part of the unit blocks 920C in this way make it possible for the rest of the plurality of unit blocks 910B to be kept in a programmable state while misprogramming of the plurality of unit blocks 920C can be prevented. Furthermore, this structure can simplify the configuration of the fuse block 920C.
While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Modifications can be made without departing from the spirit or scope of the present invention. For example, in the above-described preferred embodiments, an MOS transistor was cited and described as an example of an anti-fuse. However, the anti-fuse is not limited thereto, and nonvolatile storage elements such as a flash memory and an EPROM, electric fuses and the like can be used. Moreover, although in the above-described preferred embodiments, a case in which the present invention is applied to a semiconductor memory has been described as an example, it is also possible to apply the present invention to logic products such as a CPU (Central Processing Unit), an FPLD (Field Programmable Logic Device) or the like.
Further, in the above-described first embodiment, for example, the fuse element circuit 913 for storing the program inhibition data is to be programmed by the program signal SB provided from the control logic circuit 140 through the AND gate circuit 914. However, when the fuse element circuit 913 is composed of an anti-fuse of a destructive type, the program signal SB may be directly provided from the control logic circuit 140 to the fuse element circuit 913. In this case, the fuse element circuit 913 which has been programmed once will not lose the data stored therein even if it might be misprogrammed afterwards. Consequently, the function to prevent misprogramming of the group of fuse element circuits 911 will not be lost. The same statements are true for the other embodiments.
Still further, in the above-described embodiments, the unit block 910A for defective remedy, and unit blocks 920A for adjusting the word organization, the voltage of the internal electrical power source, and the operating timing, respectively were cited and described as examples. However, unit blocks are not limited thereto, and any unit block may be provided according to demand, and another optional unit block may be added. In the above-described embodiments, a case in which ×8-bit organization is modified to ×4-bit organization was cited and described as an example. However, the word organization is not limited thereto, and the invention may be extended such that the word organization is modified arbitrarily. Still further, in the above-described embodiments, the anti-fuses of destructive type were used for the group of fuse element circuits 911. However, it is not limited thereto, and another fuse may also be used. Furthermore, in the above-described embodiments, the semiconductor device of the present invention was described such that the circuit configuration is definable in the fuse circuits. However, the semiconductor device of the present invention includes those in which the circuit is programmable, modifiable, changeable, or the like.
While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-277564 | Oct 2006 | JP | national |
