Claims
- 1. A semiconductor memory device comprising:
- a rectangular semiconductor chip having a top surface and longitudinal and lateral sides;
- at least first, second, third, and fourth memory arrays positioned on said top surface in a staggered, eccentric configuration on said semiconductor chip relative to said longitudinal sides of said semiconductor chip such that a first edge of said first and third memory arrays are spaced a first predetermined distance from respective opposing longitudinal sides of said chip, and a first edge of said second and fourth memory arrays are spaced a second predetermined distance, less than said first predetermined distance, from each of said opposing longitudinal sides of said chip to form a narrow space and a wide space between said first edges of respective memory arrays and each said longitudinal side of said chip; and
- a plurality of bonding pads positioned on said top surface of said chip in said wide space between said first edges of respective ones of said memory arrays and respective longitudinal sides of said chip.
- 2. A semiconductor memory device according to claim 1, wherein each memory array is substantially rectangular with longitudinal and lateral sides and said lateral sides of said memory arrays are positioned opposite the longitudinal sides of said semiconductor chips.
- 3. A semiconductor memory device according to claim 1, wherein said memory arrays are spaced from said lateral sides of said semiconductor chip to form bonding spaces therebetween.
- 4. A semiconductor device comprising:
- a rectangular semiconductor chip having a top surface and longitudinal and lateral sides;
- at least first, second, third, and fourth element regions positioned on said top surface in a staggered, eccentric configuration relative to said longitudinal sides of said semiconductor chip such that a first edge of said first and third element regions are spaced a first predetermined distance from opposite longitudinal sides of said chip, and a first edge of said second and fourth element regions are spaced a second predetermined distance, less than said first predetermined distance, from opposite longitudinal sides of said chip to form a narrow space and a wide space between said first edges of respective ones of said element regions and each said longitudinal side of said chip; and
- a plurality of bonding pads positioned on said top surface of said chip in said wide region between respective first edges of said element regions and respective longitudinal sides of said chip.
Priority Claims (1)
Number |
Date |
Country |
Kind |
59-160517 |
Jul 1984 |
JPX |
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Parent Case Info
This is a continuation of application Ser. No. 717,646, filed Mar. 9, 1985, now abandoned.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
4467400 |
Stopper |
Aug 1974 |
|
Foreign Referenced Citations (2)
Number |
Date |
Country |
0142544 |
Aug 1983 |
JPX |
0197747 |
Nov 1983 |
JPX |
Continuations (1)
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Number |
Date |
Country |
Parent |
717646 |
Mar 1985 |
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