Patent Application
20210391323
The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation.
Complementary-metal-oxide-semiconductor (CMOS) processes may be used to build a combination of p-type and n-type field-effect transistors that are used to construct, for example, logic cells. Field-effect transistors generally include a semiconductor body supplying a channel region in a substrate, a source, a drain, and a gate structure over the semiconductor body. When a control voltage exceeding a characteristic threshold voltage is applied to a gate electrode of the gate structure, carrier flow occurs in the channel region between the source and drain to produce a device output current.
A fin-type field-effect transistor (FinFET) is a non-planar device structure that may be more densely packed in an integrated circuit than a planar field-effect transistor. A fin-type field-effect transistor may include a fin providing a semiconductor body, a gate structure that wraps about the fin, and heavily-doped source/drain regions arranged on opposite sides of the gate structure. The source/drain regions may be epitaxially grown in cavities that are etched in the fin. In an application, fin-type field-effect transistor structures may be used to form diodes for an electrostatic discharge circuit.
Improved structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation are needed.
In an embodiment of the invention, a structure includes a semiconductor body having a cavity, a first gate structure and a second gate structure extending over the semiconductor body, and a semiconductor layer having a first section on the semiconductor body and a second section on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section of the semiconductor layer is laterally positioned between the cavity and the second gate structure. The structure includes an isolation structure laterally positioned between the first section and the second section of the semiconductor layer. The isolation structure including a dielectric layer and a sidewall spacer having a first section and a second section. The dielectric layer includes a first portion in the cavity and a second portion between the first section and the second section of the sidewall spacer.
In an embodiment of the invention, a method includes forming a cavity in a semiconductor body, forming a first gate structure and a second gate structure extending over the semiconductor body, forming a first section and a second section of a semiconductor layer on the semiconductor body, and forming an isolation structure laterally positioned between the first section and the second section of the semiconductor layer. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section of the semiconductor layer is laterally positioned between the cavity and the second gate structure. The isolation structure includes a dielectric layer and a sidewall spacer having a first section and a second section. The dielectric layer includes a first portion in the cavity and a second portion between the first section and the second section of the sidewall spacer.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.
With reference to
Shallow trench isolation 24 may be formed that surrounds the fins 10, 12. The shallow trench isolation 24 may be composed of a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition or grown by thermal oxidation, and may be etched back following deposition to reveal the fins 10, 12. A well (not shown) may be formed in the substrate 18 by ion implanting a concentration of a dopant species, such as an n-type dopant, and activating the dopant species by thermal annealing.
Gate structures 26 are formed that extend transversely across the fins 10 and transversely across the fins 12 with a lateral spacing. The gate structures 26 may include an upper layer comprised of a conductor, such as polycrystalline silicon (i.e., polysilicon), and lower layer composed of an electrical insulator, such as silicon dioxide. A deposited layer stack including the upper and lower layers may be patterned by lithography and etching processes to define the gate structures 26. Each gate structure 26 may include a cap 27 comprised of a dielectric material, such as silicon nitride, that is a remnant of their formation. The gate structures 26 may be dummy gate structures that are subsequently replaced in a replacement-metal-gate process. The gate structures 26 may be arranged parallel or substantially parallel to each other. The gate structures 26 have an arrangement that is characterized by a lateral spacing given by a pitch, P1, which may be a one times (1×) contacted poly pitch (CPP) arrangement.
Sidewall spacers 28 are formed that respectively surround a sidewall of each gate structure 26. The sidewall spacers 28 may be formed by depositing a conformal layer composed of a dielectric material and etching the deposited conformal layer with an anisotropic etching process, such as reactive ion etching. The sidewall spacers 28 may be comprised of a low-k dielectric material (e.g., hydrogen-enriched silicon oxycarbide (SiCOH)) characterized by a relative permittivity or dielectric constant that is less than the dielectric constant (i.e., approximately 3.9) of silicon dioxide.
With reference to
The epitaxial growth process may be selective in that the semiconductor material does not grow from dielectric surfaces, such as the surfaces of the shallow trench isolation 24, the caps 27, and the sidewall spacers 28. The sections of the semiconductor layer 32 in device region 20 may be doped after epitaxial growth by, for example, a masked ion implantation to introduce a dopant (e.g., phosphorus and/or arsenic) that provides n-type electrical conductivity. The sections of the semiconductor layer 32 in device region 22 may be doped after epitaxial growth by, for example, a masked ion implantation to introduce a dopant (e.g., boron) that provides p-type electrical conductivity. The sections of the semiconductor layer 32 may define source/drain regions of a field-effect transistor. As used herein, the term “source/drain region” means a doped volume of semiconductor material that can function as either a source or a drain of a field-effect transistor.
The cavities 30 may exhibit an improvement in filling by the epitaxial semiconductor material of the semiconductor layer 32 in comparison with conventional processes having a wider gate pitch at the time of filling and exhibiting cavity underfilling. The cavities 30 and sections of the semiconductor layer 32 are formed with a 1× CPP arrangement for the gate structures 26. The cavities 30 are volumetrically smaller than in conventional processes characterized by a large gate pitch (e.g., a 2× CPP arrangement) at the time of cavity formation. The cavities 30 therefor define comparatively small volumes to be filled by the sections of the semiconductor layer 32. The semiconductor material contained in the multiple sections of the semiconductor layer 32 between adjacent gate structures in the completed device structure may be overall larger due to alleviation of cavity underfilling. The related gouging of the epitaxial semiconductor material during the subsequent formation of source/drain contacts may also be reduced.
With reference to
With reference to
Cavities 38 are formed in the fins 10 at the locations of the exposed areas on their top surfaces 14. Cavities 38 are formed in the fins 12 at the locations of the exposed areas on their top surfaces 16. Sections 28a of the sidewall spacer 28 are positioned on the top surfaces 14 of the fins 10, and each cavity 38 is laterally positioned in one of the fins 10 between a spaced-apart pair of the sections 28a of the sidewall spacer 28. Sections 28a of the sidewall spacer 28 are also positioned on the top surfaces 16 of the fins 12, and each cavity 38 is laterally positioned in one of the fins 12 between a spaced-apart pair of the sections 28a of the sidewall spacer 28. In an embodiment, each cavity 38 may be centered between the pair of sections 28a of the sidewall spacer 28.
The cavities 38 in the fins 10, 12 may be formed by a self-aligned selective etching process, such as a reactive ion etching process. In an embodiment, the same etching process may be employed to form the cavities 36 and the cavities 38. The hardmask 34 may be removed after the cavities 36, 38 are formed.
Multiple cavities 38 are associated with each of the cavities 36. Each individual cavity 36 intersects with cavities 38 in the fins 10 in device region 20 and intersects with cavities 38 in the fins 12 in device region 22. A portion of cavity 36 is positioned directly over each cavity 38, a portion of cavity 36 is positioned adjacent to one side of each cavity 38, and a portion of cavity 36 is positioned adjacent to an opposite side of each cavity 38. Sections 28a of the sidewall spacer 28 are positioned adjacent to the portion of cavity 36 positioned directly over each cavity 38. Other sections of the sidewall spacer 28 are positioned adjacent to the portions of cavity 36 positioned adjacent to each cavity 38.
The cavities 38 may have a depth relative to the top surface 14 of the fins 10 and relative to the top surface 16 of the fins 12 that is greater than the depth of the cavities 30 holding the sections of the semiconductor layer 32. The greater depth places the bottoms of the cavities 38 closer to the top surface 11 of the substrate 18 than the bottoms of the cavities 30. Each of the fins 10, 12 includes portions 39 that are respectively positioned between each section of the semiconductor layer 32 and the adjacent cavity 38. The portions 39 result from the self-aligned masking of the fins 10, 12 by the sidewall spacers 28 during the etching process forming the cavities 38.
With reference to
A dielectric layer 40 is also formed in the spaces surrounding the gate structures 26 and over the sections of the semiconductor layer 32. The dielectric layers 40, 42 may be comprised of a dielectric material, such as silicon dioxide, that is deposited by chemical vapor deposition and planarized by chemical-mechanical polishing. The dielectric layers 40, 42 may be concurrently formed and have the same composition. Prior to depositing the dielectric layers 40, 42, a contact etch-stop layer (not shown) comprised of, for example, silicon nitride may be deposited to provide a conformal liner. Each sidewall spacer 28 provides self-alignment for the formation of each dielectric layer 42 during deposition. The composition of the dielectric material contained in the dielectric layers 40, 42 differs from the composition of the dielectric material contained in the sidewall spacers 28.
The dielectric layer 42 in each cavity 36 is separated from the dielectric layer 40 in the spaces around the isolation structures 48 by one of the sidewall spacers 28. The dielectric layer 42 in each cavity 36 may be surrounded on all sides by one of the sidewall spacers 28. Each portion 42a of the dielectric layer 42 is laterally positioned in one lateral direction (e.g., the x-direction in an x-y plane) between adjacent sections 28a of one of the sidewall spacers 28. Each portion 42b of the dielectric layer 42 is laterally positioned in one lateral direction (e.g., the x-direction in an x-y plane) between adjacent sections of the semiconductor layer 32. The portions 39 of the fins 10, 12 are positioned between these adjacent sections of the semiconductor layer 32 and the portion 42b of the dielectric layer 42 in each cavity 38. In an embodiment, each portion 42b of the dielectric layer 42 may be centered between the pair of sections 28a of the sidewall spacer 28. The portion 42b of the dielectric layer 42 in each cavity 38 is laterally positioned in the other lateral direction (e.g., the y-direction in an x-y plane) between other portions of the dielectric layer 42.
The dielectric layers 42 of the isolation structures 48 are late-formed after the gate structures 26 and the sections of the semiconductor layer 32 are formed. The isolation structures 48 may define single diffusion breaks in the fins 10, 12 that provide electrical isolation. The formation of the isolation structures 48 differs from conventional processes in which fin cuts for single diffusion breaks are formed before the gate structures 26 are formed.
With reference to
Multiple sections of the semiconductor layer 32 are laterally positioned between the gate structure 44 and the gate structure 45. One of the isolation structures 48 is laterally positioned between gate structure 44 and the gate structure 45 and is also laterally positioned between the section of the semiconductor layer 32 adjacent to the gate structure 44 and the section of the semiconductor layer 32 adjacent to the gate structure 45.
Multiple sections of the semiconductor layer 32 are laterally positioned between the gate structure 45 and the gate structure 46. One of the isolation structures 48 is laterally positioned between gate structure 45 and the gate structure 46 and is also laterally positioned between the section of the semiconductor layer 32 adjacent to the gate structure 45 and the section of the semiconductor layer 32 adjacent to the gate structure 46.
Source/drain contacts 50 may be formed in contact openings defined by lithography and etching processes in an interlayer dielectric layer 52. The source/drain contacts 50 may contain a metal silicide, such as tungsten silicide, titanium silicide, nickel silicide, or cobalt silicide, formed by silicidation. The interlayer dielectric layer 52 may be comprised of a dielectric material, such as silicon dioxide. The source/drain contacts 50 are connected to the sections of the semiconductor layer 32. Portions of the interlayer dielectric layer 52 are laterally arranged in the space between the sidewall spacers 28 and the source/drain contacts 50.
An interconnect structure 51 is formed by middle-of-line and back-end-of-line processing that includes formation of upper contacts 54 connected to the source/drain contacts 50 and wiring 56 connected by vias 57 with the upper contacts 54. The upper contacts 54, wiring 56, and vias 57 may be formed in one or more interlayer dielectric layers 55. The gate structure 45 may be physically connected by one or more contacts 58 and one or more vias with other wiring (not shown). The gate structure 44 and the gate structure 46 represent dummy gates that lack electrical and physical connections to the interconnect structure 51.
In the device structure, the isolation structures 48 define an elongated dielectric bar that is arranged between adjacent gate structures 44, 45 and another elongated dielectric bar that is arranged between adjacent gate structures 45, 46. The gate structures 44, 45, 46 in the device structure have a lateral spacing with a pitch, P2, providing a multiple CPP arrangement that is established after the sections of the semiconductor layer 32 are epitaxially grown. In the representative embodiment, the multiple CPP arrangement is a 2× CPP arrangement.
In an embodiment, the sections of the semiconductor layer 32 may be connected by the wiring 56 in the interconnect structure 51 to define a diode for an electrostatic discharge (ESD) circuit. The parasitic capacitance of the ESD diode is reduced by reducing the dummy gate density and replacing pulled gate structures 26 with isolation structures 48. The dummy gate density is reduced after forming the sections of the semiconductor layer 32 and, in the completed device structure, the on-resistance of the ESD diode is improved due to the associated improvement in the quality of the sections of the semiconductor layer 32.
With reference to
With reference to
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane.
References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate+/−10% of the stated value(s).
A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
