Patent Application
20200090944
Korean Patent Application No. 10-2018-0109473, filed on Sep. 13, 2018, in the Korean Intellectual Property Office, and entitled: “Semiconductor Devices,” is incorporated by reference herein in its entirety.
Embodiments relate to a semiconductor device.
In manufacturing a semiconductor device, it is needed to form a contact plug contacting a conductive structure.
Embodiments are directed to a semiconductor device, including a conductive structure on a substrate, an etch stop layer on the conductive structure, an insulation layer on the etch stop layer, and a contact plug extending through the etch stop layer and the insulation layer and contacting the conductive structure. The contact plug may include first and second conductive pattern structures sequentially stacked and contacting with each other. A width of an upper surface of the first conductive pattern structure may be greater than that of a lower surface of the second conductive pattern structure. At least an upper portion of the first conductive pattern structure may have a sidewall not perpendicular but inclined to an upper surface of the substrate.
Embodiments are also directed to a semiconductor device, including a conductive structure on a substrate, an etch stop layer on the conductive structure, an insulation layer on the etch stop layer, and a contact plug extending through the etch stop layer and the insulation layer, extending in a vertical direction substantially perpendicular to an upper surface of the substrate, and contacting the conductive structure. The contact plug may include a protrusion portion at least at a central portion thereof in the vertical direction, the protrusion portion protruding in a horizontal direction substantially parallel to the upper surface of the substrate.
Embodiments are also directed to a semiconductor device, including an insulating interlayer on a substrate, the insulating interlayer containing a conductive line, an etch stop layer on the conductive line and the insulating interlayer, an insulation layer on the etch stop layer, a contact plug extending through the etch stop layer and the insulation layer and contacting the conductive line, a lower electrode on the contact plug, an MTJ structure on the lower electrode, and an upper electrode on the MTJ structure. The contact plug may include first and second conductive pattern structures. A width of an upper surface of the first conductive pattern structure may be greater than that of a lower surface of the second conductive pattern structure. At least an upper portion of the first conductive pattern structure may have a sidewall not perpendicular but inclined to an upper surface of the substrate.
Features will become apparent to those of skill in the art by describing in detail example embodiments with reference to the attached drawings in which:
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey example implementations to those skilled in the art.
In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
A semiconductor device in accordance with an example embodiment will be described more fully hereinafter with reference to the accompanying drawings.
Referring to
The substrate 100 may include, e.g., semiconductor materials, e.g., silicon, germanium, silicon-germanium, etc., or III-V compounds e.g., GaP, GaAs, GaSb, etc. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.
The insulating interlayer 110 may include, e.g., an oxide, e.g., silicon oxide, and the conductive structure 120 may include, e.g., a low resistance metal, e.g., aluminum (Al), copper (Cu), tantalum (Ta), etc., or a nitride thereof.
The conductive structure 120 may be formed by, e.g., forming a first opening extending through the insulating interlayer 110 to expose an upper surface of the substrate 100, forming a first conductive layer on the exposed upper surface of the substrate 100 and an upper surface of the insulating interlayer 110 to fill the first opening, and planarizing the first conductive layer until the upper surface of the insulating interlayer 110 is exposed.
The planarization process may be performed by, e.g., a CMP process and/or an etch back process.
The conductive structure 120 may be formed in a single number or plural numbers.
Referring to
The etch stop layer 130 may include, e.g., silicon nitride (SiNx) or silicon carbonitride (SiCN), and the insulation layer 140 may include, e.g., silicon oxide (SiO2).
The first etching mask 145 may include, e.g., a photoresist pattern, silicon-on-hardmask (SOH), an amorphous carbon layer (ACL), etc.
Referring to
The first etching process may be performed by, e.g., a dry etching process using a fluorine-based gas such as hexafluorobutyne (C4F6), octafluorocyclobutane (C4F8), or the like.
The second opening 160 may have a sidewall substantially perpendicular to the upper surface of the substrate 100.
Referring to
The ashing process and/or the stripping process may use e.g., oxygen (O2) plasma, and an exposed upper portion of the etch stop layer 130 may be reacted with oxygen plasma to form a denatured layer 150. The denatured layer 150 may include e.g., silicon oxynitride (SiON) or silicon oxycarbonitride (SiOCN).
The denatured layer 150 may be formed on the upper portion of the etch stop layer 130 exposed by the second opening 160, and may be formed on a portion of the etch stop layer 130 adjacent thereto.
During the ashing process and/or the stripping process, the first etching mask 145 may be partially or totally removed.
Referring to
The cleaning process may be performed by, e.g., an isotropic wet etching process using, e.g., a hydrogen fluoride (HF) aqueous solution. The aqueous hydrogen fluoride (HF) solution may have a concentration of, e.g., about 1% to about 5%. In another implementation, the cleaning process may be performed by an isotropic dry etching process using, e.g., hydrogen fluoride (HF) alone or a mixture of ammonia (NH3) and hydrogen fluoride (HF).
The trench 165 may have a sidewall inclined from the perpendicular relative to the upper surface of the substrate 100, and an upper portion of the trench 165 may have a width greater than that of a lower portion of the second opening 160.
Referring to
As a result, the second opening 160 and the third opening 170 may be connected with each other to form a contact hole 180.
The second etching process may be performed by e.g., a dry etching process using a fluorine-based gas such as hexafluorobutyne (C4F6), octafluorocyclobutane (C4F8), or the like.
An upper portion of the third opening 170 may have a width greater than that of the lower portion of the second opening 160, and the upper portion of the third opening 170 may have a sidewall inclined from the perpendicular relative to the upper surface of the substrate 100. A lower portion of the third opening 170 may have a sidewall substantially perpendicular to the upper surface of the substrate 100.
As described above, when the contact hole 180 is formed, the cleaning process may be performed before the second etching process to remove the denatured layer 150 at the upper portion of etch stop layer 130. Accordingly, when the second etching process is performed, the etch stop layer 130 may be easily removed, and the third opening 170 may efficiently expose the upper surface of the conductive structure 120.
Referring to
A barrier layer may be formed on a sidewall of the contact hole 180, the exposed upper surface of the conductive structure 120, and the upper surface of the insulation layer 140. A second conductive layer may be formed on the barrier layer to fill a remaining portion of the contact hole 180. The second conductive layer and the barrier layer may be planarized until the upper surface of the insulation layer 140 is exposed to form the contact plug 250 in the contact hole 180.
The contact plug 250 may include first and second conductive pattern structures 230 and 240, which may be stacked in the vertical direction to contact each other and may fill the third and second openings 170 and 160, respectively. The first conductive pattern structure 230 may include a first conductive pattern 210 and a first barrier pattern 190 covering a sidewall and a lower surface of the first conductive pattern 210. The second conductive pattern structure 240 may include a second conductive pattern 220 and a second barrier pattern 200 covering a sidewall of the second conductive pattern 220.
An upper surface of the first conductive pattern structure 230 may have a width greater than that of a lower surface of the second conductive pattern structure 240, and an upper portion of the first conductive pattern structure 230 may have a sidewall not perpendicular but inclined to the upper surface of the substrate 100. A lower portion of the first conductive pattern structure 230 may have a sidewall substantially perpendicular to the upper surface of the substrate 100. The second conductive pattern structure 240 may also have a sidewall substantially perpendicular to the upper surface of the substrate 100.
As described above, due to the shape of the sidewall of the first conductive pattern structure 230, the contact plug 250 may have a protrusion portion, which may protrude in a horizontal direction substantially parallel to the upper surface of the substrate 100 at a central portion in the vertical direction of the contact plug 250.
The first and second conductive patterns 210 and 220 may include, e.g., a metal, e.g., copper, tungsten, aluminum, etc., and the first and second barrier patterns 190 and 200 may include, e.g., a metal, e.g., titanium, tantalum, etc., or a metal nitride, e.g., titanium nitride, tantalum nitride, etc.
Upper wirings connected to the contact plug 250 may be further formed to complete the fabrication of the semiconductor device.
In a method of manufacturing a semiconductor device in accordance with an example embodiment, in a process for forming a contact hole that extends through a structure including an etch stop layer and an insulation layer to expose a conductive structure thereunder, a cleaning process may be further performed to remove a denatured layer that may be formed after a first etching process for etching the insulation layer, and thus the contact hole may effectively expose the conductive structure. In detail, referring to
Even if the lower sidewall of the first conductive pattern structure 230 and the sidewall of the second conductive pattern structure 240 have inclined sidewalls, respectively, first and second slopes of the lower sidewall of the first conductive pattern structure 230 and the sidewall of the second conductive pattern structure 240, respectively, with respect to the upper surface of the substrate 100 may be smaller than a third slope of an upper sidewall of the first conductive pattern structure 230 with respect to the upper surface of the substrate 100. In one embodiment, the first and second slopes may be substantially the same as each other.
Referring to
The sidewall of the second conductive pattern structure 240 may be perpendicular, or may be inclined to the upper surface of the substrate 100, as shown in
Referring to
The shape of the upper sidewall of the first conductive pattern structure 230 may be caused by the shape of the denatured layer 150 formed during the ashing process and/or the stripping process described in
Accordingly, the upper sidewall of the first conductive pattern structure 230 may have a smoothly curved shape. Thus, a protrusion portion at a central portion of the contact plug 250 in the vertical direction may have the smoothly curved shape. Thus, the central portion of the contact plug 250 may have a convex shape.
Referring to
The shape of the contact plug 250 may be formed when the denatured layer 150 is formed to have substantially the same thickness as the etch stop layer 130, or when the etch stop layer 130 under the denatured layer 150 is removed together with the denatured layer 150 during the cleaning process for removing the denatured layer 150.
Accordingly, an upper portion of the contact plug 250 may have a uniform width, while the lower portion may have a width gradually increasing and then decreasing downwardly. In another implementation, the upper portion of the contact plug 250 may have a gradually decreasing width downwardly, which may be similar to that of the contact plug 250 described in
This method of manufacturing the semiconductor device may include processes substantially the same as or similar to the processes described in
Referring to
The active fin 305 may include a lower active pattern 305b of which a sidewall may be covered by the isolation pattern, and an upper active pattern 305a protruding from an upper portion of the isolation pattern. In example embodiments, the active fin 305 may extend in a first direction substantially parallel to an upper surface of the substrate 300, and a plurality of active fins 305 may be formed in a second direction substantially parallel to the upper surface of the substrate 300 and intersecting with the first direction.
A dummy gate structure 360 may be formed on the active fin 305. For example, after sequentially forming a dummy gate insulation layer, a dummy gate electrode layer and a dummy gate mask layer on the active fin 305 of the substrate 300 and the isolation pattern, the dummy gate mask layer may be patterned to form a dummy gate mask 350, and the dummy gate electrode layer and the dummy gate insulation layer under the dummy gate mask 350 may be sequentially etched using the dummy gate mask 350 as an etching mask to form a dummy gate electrode 340 and a dummy gate insulation pattern 330, respectively. Accordingly, the dummy gate structure 360 including the dummy gate insulation pattern 330, the dummy gate electrode 340 and the dummy gate mask 350 sequentially stacked on the active fin 305 and the isolation pattern may be formed. In an example embodiment, the dummy gate structure 360 may extend in the second direction, and a plurality of dummy gate structures 360 may be formed in the first direction.
Referring to
The gate spacer 370 may be formed by forming a spacer layer on the active fin 305 and the isolation pattern to cover the dummy gate structure 360, and anisotropically etching the spacer layer.
The source/drain layer 400 may be formed by removing the upper portion of the active fin 305 through a dry etching process using the gate spacer 370 and the dummy gate structure 360 as an etching mask form a second recess, and filling the second recess. In an example embodiment, the source/drain layer 400 may be formed by performing a selective epitaxial growth (SEG) process using an exposed upper surface of the active fin 305 as a seed.
The first insulating interlayer 410 may be formed on the substrate 300 to cover the dummy gate structure 360, the gate spacer 370 and the source/drain layer 400, and an upper portion of the first insulating interlayer 410 may be planarized until an upper surface of the dummy gate electrode 340 of the dummy gate structure 360 is exposed.
The exposed dummy gate electrode 340 and the dummy gate insulation pattern 330 thereunder may be removed to form a fourth opening exposing an inner sidewall of the gate spacer 370 and the upper surface of the active fin 305, and a gate structure 460 may be formed to fill the fourth opening.
The gate structure 460 may be formed by, e.g., performing following processes. First, a thermal oxidation process may be performed on the upper surface of the active fin 305 exposed by the fourth opening to form an interface pattern 420 a gate insulation layer and a work function control layer may be sequentially formed on the interface pattern 420, the isolation pattern, gate spacer 370 and the first insulating interlayer 410 and a gate electrode layer may be formed on the work function control layer to sufficiently fill a remaining portion of the fourth opening.
Then, the gate electrode layer, the work function control layer and the gate insulation layer may be planarized until an upper surface of the first insulating interlayer is exposed, so that a gate insulation pattern 430 and a work function control pattern 440 sequentially stacked on an upper surface of the interface pattern 420, an upper surface of the isolation pattern and the inner sidewall of the gate spacer 370 may be formed, and a gate electrode 450 may be formed on the work function control pattern 440 to fill the remaining portion of the fourth opening. Accordingly, a lower surface and a sidewall of the gate electrode 450 may be covered by the work function control pattern 440.
The interface pattern 420, the gate insulation pattern 430, the work function control pattern 440, and the gate electrode 450, sequentially stacked, may form the gate structure 460. The gate structure 460 may form a transistor together with the source/drain layer 400. The transistor may form a PMOS transistor or an NMOS transistor according to the conductivity type of the source/drain layer 400.
Referring to
Before forming the source line 500 a first metal silicide pattern 490 may be further formed on an upper portion of the first source/drain layer. For example, a fifth opening may be formed to extend through the first insulating interlayer 410, the capping layer 470, and the second insulating interlayer 480 to expose an upper surface of the first source/drain layer. A first metal layer may be formed on the upper surface of the first source/drain layer, a sidewall of the fifth opening, and an upper surface of the second insulating interlayer. A heat treatment process may be performed to form the first metal silicide pattern 490 on the upper portion of the first source/drain layer.
The source line 500 may include a metal, a metal nitride, and/or doped polysilicon, and may have a structure of a conductive pattern and a barrier pattern covering a lower surface and a sidewall thereof. In an example embodiment, the source line 500 may extend in the second direction by a given length, and a plurality of source lines 500 may be formed in the first direction.
After forming a third insulating interlayer 510 on the second insulating interlayer 480 and the source line 500, a first contact plug 530 may be formed to extend through the first insulating interlayer 410, the capping layer 470, the second insulating interlayer 480, and the third insulating interlayer 510 to contact an upper surface of a portion of the source/drain layers 400 (hereinafter referred to as a second source/drain layer). The first contact plug 530 may correspond to the conductive structure 120 in the method of manufacturing the semiconductor device described in
A second metal silicide pattern 520 may be further formed between the first contact plug 530 and the second source/drain layer. The first contact plug 530 may also have a structure of a conductive pattern and a barrier pattern covering a lower surface and a sidewall thereof.
Referring to
In example embodiments, the first etch stop layer 540 may include a silicon nitride (SiNx) or a silicon carbonitride (SiCN).
Referring to
Referring to
Referring to
In an example embodiment, the ashing process and/or the stripping process may use oxygen (O2) plasma, and thus the denatured layer 580 may include, e.g., silicon oxynitride (SiON) or silicon oxycarbonitride (SiOCN).
Referring to
In an example embodiment, the second trench 595 may have a sidewall not perpendicular but inclined to the upper surface of the substrate 300, and a width of an upper portion of the second trench 595 may be greater than that of a lower portion of the first opening 590.
In an example embodiment, the cleaning process may be performed by an isotropic wet etching process using a hydrogen fluoride (HF) aqueous solution. The aqueous hydrogen fluoride (HF) solution may have a concentration of about 1% to about 5%. In another implementation, the cleaning process may be performed by an isotropic dry etching process using hydrogen fluoride (HF) alone, or a mixture of ammonia (NH3) and hydrogen fluoride (HF).
Referring to
The first and second openings 590 and 600 may be connected with each other to form a first contact hole 610.
In an example embodiment, an upper portion of the second opening 600 may have a sidewall not perpendicular but inclined to the upper surface of the substrate 300, and a width of the upper portion of the second opening 600 may be greater than that of the lower portion of the first opening 590.
Referring to
The second contact plug 680 may include first and second conductive pattern structures 660 and 670 sequentially stacked and contacting each other. The first conductive pattern structure 660 may include a third conductive pattern 640 and a third barrier pattern 620 covering a sidewall and a lower surface of the third conductive pattern 640. The second conductive pattern structure 670 may include a fourth conductive pattern 650 and a fourth barrier pattern 630 covering a sidewall of the fourth conductive pattern 650.
In an example embodiment, a width of an upper surface of the first conductive pattern structure 660 may be greater than that of a lower surface of the second conductive pattern structure 670, and an upper portion of the first conductive pattern structure 660 may have a sidewall not perpendicular but inclined to the upper surface of the substrate 300. A lower portion of the first conductive pattern structure 660 and the second conductive pattern structure 670 may have sidewalls substantially perpendicular to the upper surface of the substrate 300. In another implementation, the lower portion of the first conductive pattern structure 660 and the second conductive pattern structure 670 may have sidewalls not perpendicular but inclined to the upper surface of the substrate 300.
The first wiring 700 may include a fifth conductive pattern 695 and a fifth barrier pattern 690 covering a sidewall and a portion of a lower surface of the fifth conductive pattern 695, and may contact the second contact plug 680 thereunder.
In an example embodiment, the first wiring 700 and the second contact plug 680 may be simultaneously formed by a dual damascene process. The first wiring 700 and the second contact plug 680 may be each formed by a single damascene process.
Referring to
The third contact plug 790 may be formed by a process similar to the process for forming the second contact plug 680, and may have a shape similar to that of the second contact plug 680. Accordingly, the third contact plug 790 may include third and fourth conductive pattern structures 770 and 780 sequentially stacked. The third conductive pattern structure 770 may include a sixth conductive pattern 750 and a sixth barrier pattern 730 covering a sidewall and a lower surface of the sixth conductive pattern 750. The fourth conductive pattern structure 780 may include a seventh conductive pattern 760 and a seventh barrier pattern 740 covering a sidewall of the seventh conductive pattern 760.
Referring to
In an example embodiment, a lower electrode layer, a blocking layer, an adhesive layer, a seed layer, an magnetic tunnel junction (MTJ) structure layer, and an upper electrode layer may be sequentially formed on the third contact plug 790. The MTJ structure layer may include a fixed layer, a tunnel barrier layer, and a free layer, sequentially stacked. The upper electrode layer, the MTJ structure layer, the seed layer, the adhesive layer, the blocking layer, and the lower electrode layer may be etching by a etching process to form the memory unit including the lower electrode 815, the blocking pattern 825, the adhesive pattern 835, the seed pattern 845, the MTJ structure 885, and the upper electrode 895 sequentially stacked on the third contact plug 790.
The lower electrode 815 may include a metal nitride, e.g., titanium nitride, tantalum nitride, etc. The blocking pattern 825 may include a metal boride, e.g., tantalum boride, titanium boride, e.g., a metal boronitride, e.g., tantalum boronitride, titanium boronitride, e.g., or a metal compound, e.g., tantalum carbon fluoroborate (CFBTa). The adhesive pattern 835 may include a metal, e.g., tantalum, titanium, etc. The seed pattern 845 may include a metal, e.g., ruthenium (Ru), rhenium (Re), etc.
The fixed layer pattern 855 may include a ferromagnetic material, e.g., cobalt, platinum, iron, nickel, etc. In an example embodiment, the fixed layer pattern 855 may include an alloy of cobalt and platinum, i.e., CoPt, or a multi-layered structure including a cobalt layer and a platinum layer alternately stacked. The tunnel barrier pattern 865 may include, e.g., magnesium oxide or aluminum oxide. The free layer pattern 875 may include a ferromagnetic material, e.g., cobalt, platinum, iron, nickel, etc.
The MTJ structure layer may include a free layer, a tunnel barrier layer, and a fixed layer sequentially stacked. At least one of the fixed layer, the tunnel barrier layer and the free layer may be formed at a plurality of levels.
The upper electrode 895 may include a metal, e.g., titanium, tantalum, etc., and/or a metal nitride, e.g., titanium nitride, tantalum nitride, etc.
A protection layer 900 may be formed to cover the memory unit. A sixth insulating interlayer 910 may be formed on the protection layer 900. A via 920 and a second wiring 930 sequentially stacked may be formed to extend through an upper portion of the sixth insulating interlayer 910.
In an example embodiment, the second wiring 930 and the via 920 may be simultaneously formed by a dual damascene process. In another implementation, the second wiring 930 and the via 920 may be each formed by a single damascene process. In an example embodiment, the via 920 may be formed by processes substantially the same as or similar to the processes for forming the second and third contact plugs 680, 790, and thus may include a protrusion portion at a central portion of the via 920.
Upper wirings connected with the sixth insulating interlayer 910 and the second via 920 may be further formed to complete the fabrication of the semiconductor device.
The above semiconductor device may be applied to various types of memory devices and systems including contact plugs. For example, the semiconductor may be applied to logic devices such as central processing units (CPUs), main processing units (MPUs), or application processors (APs), or the like, including contact plugs. Additionally, the semiconductor device may be applied to volatile memory devices such as DRAM devices or SRAM devices, or the like, or non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, RRAM devices, or the like, including contact plugs.
By way of summation and review, in a general process for forming a contact plug extending through an etch stop layer and an insulation layer sequentially stacked on a conductive structure to contact an upper surface of the conductive structure the insulation layer may be etched by a first etching process using a first etching mask to expose an upper surface of the etch stop layer, the first etching mask may be removed, the etch stop layer may be etched by a second etching process using a second etching mask to form a contact hole exposing the upper surface of the conductive structure. However, the contact hole may not expose the upper surface of the conductive structure, and thus the contact plug may not contact the upper surface of the conductive structure.
As described above, embodiments relate to a semiconductor device including a contact plug. Example embodiments may provide a semiconductor device having improved characteristics.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2018-0109473 | Sep 2018 | KR | national |
