Claims
- 1. A method used to de-process a semiconductor device comprising the following steps:
providing a semiconductor wafer section; providing a holder having an opening therein; placing said semiconductor wafer section into said opening and generally aligning a first side of said wafer section with a first side of said holder; securing said wafer section in generally fixed relation to said holder; and subsequent to securing said wafer section to said holder, removing a portion of said first side of said wafer section.
- 2. The method of claim 1 wherein said step of providing said holder comprises the step of providing a semiconductor wafer having at least one layer formed thereover, and said method further comprises the step of polishing said at least one layer formed over said wafer during said step of polishing said first side of said wafer section.
- 3. The method of claim 1 wherein said step of securing said wafer section to said holder comprises the steps of:
dispensing a potting material between said wafer section and said holder; curing said potting material; and subsequent to said step of curing said potting material, back grinding said wafer section and said holder to remove excess cured potting material.
- 4. The method of claim 1 wherein said step of placing said semiconductor wafer section into said opening includes the step of contacting said first side of said wafer section and said first side of said holder with a generally planar alignment surface, thereby aligning said first sides of said wafer section and said holder.
- 5. The method of claim 4 wherein said generally planar alignment surface comprises an adhesive release layer.
- 6. A method for removing a layer from a semiconductor device comprising the following steps:
providing a semiconductor wafer having a generally planar front side and a die-shaped opening therein; providing a semiconductor die having a generally planar surface; placing said die into said opening in said wafer; securing said die to said wafer; and subsequent to said step of securing said die to said wafer, polishing said generally planar surface of said die.
- 7. The method of claim 6 wherein said polishing step removes at least one layer from said generally planar surface of said die.
- 8. The method of claim 7 wherein said semiconductor wafer comprises at least one layer formed thereover and said polishing step removes at least a portion of said at least one layer from said wafer.
- 9. The method of claim 6 wherein said die-shaped opening comprises a length and a width, wherein said length is between about 1 and about 20 mils greater than a length of said die and said width is between about 1 and about 20 mils greater than a width of said die.
- 10. The method of claim 6 wherein said step of securing said die to said wafer comprises the step of dispensing a potting material around a perimeter of said die into a space between said die and said wafer.
- 11. The method of claim 10 further comprising the following steps:
providing an optical flat; and positioning said wafer on said optical flat, then performing said step of placing said die into said opening in said wafer, wherein said optical flat aligns said generally planar front side of said wafer with said generally planar surface of said die.
- 12. The method of claim 11 further comprising the step of applying an adhesive release layer to said optical flat prior to said step of positioning said wafer on said optical flat.
- 13. The method of claim 6 wherein said polishing step comprises the use of chemical mechanical polishing.
- 14. The method of claim 6 wherein said generally planar surface of said die is a circuit side of said die.
- 15. A method of removing material from a first face of a semiconductor die, comprising the steps of:
securing a semiconductor die in a support member, said support member having an exposed face removable at a rate proximate to a rate at which material will be removed from said die when subjected to chemical mechanical polishing; and performing chemical mechanical polishing on said die and said support member sufficiently to remove a desired amount of material from said die.
- 16. The method of claim 15 wherein said die is secured with said first face in generally coplanar relation with said exposed face of said support member.
- 17. The method of claim 15 wherein said support member has an aperture therein, and wherein said die is secured within said aperture.
- 18. The method of claim 15 wherein said support member comprises at least one dielectric layer wherein a desired amount of material is removed during said step of performing chemical mechanical polishing on said die and said support member.
- 19. The method of claim 15 wherein said step of securing said die to said support member includes the step of providing an adhesive between said die and said support member.
- 20. The method of claim 19 further comprising the steps of:
curing said adhesive; and subsequent to curing said adhesive, backgrinding said adhesive from said support member.
- 21. An apparatus used to de-process a semiconductor device, comprising:
a holder having an opening therein, said opening adapted to receive a semiconductor device, said holder further having at least one layer of material formed thereover; and an alignment fixture having a generally planar surface for receiving and aligning a surface of said holder with a surface of a semiconductor device received by said opening in said holder.
- 22. The apparatus of claim 21 in combination with a semiconductor device having a generally planar surface, wherein said planar surface of said semiconductor device and said surface of said holder contact said generally planar surface of said alignment fixture.
- 23. The apparatus of claim 22 wherein said semiconductor device has a length and a width and said opening has a length between about 1 and about 20 mils longer than said length of said semiconductor device and a width between about 1 and about 20 mils wider than said width of said semiconductor device.
- 24. The apparatus of claim 23 further comprising a potting material which fills a space between said semiconductor device and said holder and secures said semiconductor device to said holder.
- 25. The apparatus of claim 22 wherein said holder is a semiconductor wafer.
- 26. The apparatus of claim 22 further comprising a potting jig comprising:
a block contacting said holder and having a hole and a recess therein; a shaft received by said hole in said block; and a spring received by said recess which urges said shaft toward said semiconductor device and holds said semiconductor device in alignment against said alignment fixture.
RELATED US APPLICATION DATA
[0001] This is a division of US application Ser. No. 09/369,740, filed Aug. 6, 1999 and issued Jun. 19, 2001 as US Pat. No. 6,248,001.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09369740 |
Aug 1999 |
US |
Child |
09885314 |
Jun 2001 |
US |