Patent Application
20120275244
The present application claims priority of Korean Patent Application No. 10-2011-0040350, filed on Apr. 28, 2011, which is incorporated herein by reference in its entirety.
1. Field
Exemplary embodiments of the present invention relate to a semiconductor integrated circuit design technology, and more particularly, to a fuse circuit of a semiconductor integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit includes circuits of the same patterns, and redundancy circuits are disposed in the semiconductor integrated circuit so that the semiconductor integrated circuit can be sorted as a good product even though fails have occurred in some circuits due to process variants.
In detail, in the case of a semiconductor memory device, a large number of memory cells are integrated in one chip. If a fail occurs in any one of the memory cells, the corresponding memory chip is sorted as a bad product and cannot be used.
As a semiconductor integrated circuit is highly integrated, a gradually increasing number of memory cells are integrated in a chip with a limited size. In this regard, if the entire memory chip is sorted as a bad product when a fail occurs in any one cell, the number of memory chips to be discarded will markedly increase, and due to this fact, mass-producing a semiconductor memory device with economic efficiency may be very difficult.
To efficiently mass-produce a semiconductor memory device, a conventional semiconductor memory device has a fuse circuit and a redundancy cell array. The fuse circuit includes a plurality of fuses each having the shape of a metal line, and a failed cell is replaced with a redundancy cell in a repair process depending upon whether or not a fuse is blown. The redundancy cell array and the fuse circuit are formed during a semiconductor manufacturing processes. The repair process, which replaces the failed memory cell with the redundancy cell, is performed to selectively cut a fuse constituted by a metal line mainly through using a laser beam.
Even after the fuse is blown, a fail is likely to occur again because the cut fuse may be connected again due to electrical and chemical migration phenomena by metal ions. Such a fail is generally called a HAST (highly accelerated stress testing) fail. The HAST fail frequently occurs because aluminum, which is the material of a metal line, is replaced with copper. The HAST fail mainly occurs when testing reliability under a condition including a high temperature, a high voltage, and 100% of moisture.
While the HAST fail occurs as copper is used for the manufacture of a semiconductor integrated circuit to operate at a high speed, the HAST fail may also occur where aluminum or other materials are used. Since the HAST fail occurs after blowing a fuse in a repair process, finding and also repairing the HAST fail may be difficult. The HAST fail serves as a factor that deteriorates the productivity and the reliability of a semiconductor integrated circuit.
Referring to
The NMOS transistor MN1 constitutes an inverting latch together with the inverter IV0.
Operations of the fuse circuit shown in
First, the fuse sensing signal IN1 has a logic high level in an initial state. Accordingly, the NMOS transistor MN0 is turned on and discharges the sensing node A. As a result, the output signal OUT is outputted at a logic high level. The NMOS transistor MN1 constituting the latch is turned on such that the state of the sensing node A is maintained.
Thereafter, if the fuse sensing signal IN1 is activated to a logic low level, the NMOS transistor MN0 is turned off, and the PMOS transistor MP0 is turned on. At this time, fuse state discrimination is implemented by the pull-down capability of the NMOS transistor MN1 for maintaining the initial state and the pull-up capability of the PMOS transistor MP0 and the fuse FUSE. Where the fuse FUSE is not blown (see
Conversely, where the fuse FUSE is blown (see
The following Table 1 represents logic level changes in the respective nodes of the fuse circuit shown in
Referring to Table 1, Table 1 shows that, in the case where the fuse sensing signal IN1 is activated to a logic low level, the logic level of the output signal OUT is changed depending upon whether the fuse FUSE is cut or not.
However, when the fuse FUSE is cut, a voltage of VDD-VSS is applied between the node B and the sensing node A with the fuse sensing signal IN1 having a logic low level, and a corresponding electric field promotes electrical and chemical migration phenomena of metal ions as aforementioned above.
The electrical and chemical migration phenomena of the metal ions cause the cut fuse FUSE to be connected again, which reverses a fuse programming result and leads to an error in the operations of the integrated circuit.
While the electrical and chemical migration phenomena of the metal ions result from changes in processing, since the electrical and chemical migration phenomena is difficult to prevent in terms of processing, technologies for preventing the electrical and chemical migration phenomena in terms of design have been suggested. A typical example of such technologies is disclosed in U.S. Pat. No. 6,021,078. In this technology, potentials of both ends of a fuse are maintained the same so that the electrical and chemical migration phenomena of metal ions are prevented. Nevertheless, because a fuse circuit is configured by circuit elements, the number of which is two times greater than that of a basic fuse circuit, a substantial increase in a circuit area is caused in a semiconductor integrated circuit. In a semiconductor memory device that uses a large number of fuse circuits, productivity of the semiconductor integrated circuit cannot help but deteriorate because of the additional circuit area for the larger fuse circuits.
Embodiments of the present invention are directed to a semiconductor integrated circuit and a semiconductor memory device that can prevent electrical and chemical migration phenomena of metal ions forming a fuse while minimizing an increase in the number of circuit elements constituting a fuse circuit.
In accordance with an embodiment of the present invention, a semiconductor integrated circuit includes: a fuse; a first driving unit configured to drive a sensing node in response to a first fuse sensing signal; a second driving unit configured to drive the sensing node in response to a second fuse sensing signal, wherein the second driving unit and the fuse form a driving path; a bypass resistor unit connected in parallel with the fuse; and a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.
In accordance with another embodiment of the present invention, a semiconductor integrated circuit includes: a fuse; an NMOS transistor configured to pull-down drive a sensing node in response to a first fuse sensing signal; a PMOS transistor configured to pull-up drive the sensing node in response to a second fuse sensing signal, wherein the PMOS transistor and the fuse form a driving path; a bypass resistor unit connected in parallel with the fuse; and a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.
In accordance with another embodiment of the present invention, a semiconductor integrated circuit includes: a fuse; an NMOS transistor configured to pull-down drive a sensing node in response to a first fuse sensing signal; a first PMOS transistor configured to pull-up drive the sensing node in response to a second fuse sensing signal; a second PMOS transistor configured to pull-up drive the sensing node in response to the first fuse sensing signal, wherein the first and second PMOS transistor and the fuse form a driving path; a bypass resistor unit connected in parallel with the fuse; and a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.
In accordance with another embodiment of the present invention, a semiconductor integrated circuit includes: a fuse; a PMOS transistor configured to pull-up drive a sensing node in response to a first fuse sensing signal; an NMOS transistor configured to pull-down drive the sensing node in response to a second fuse sensing signal, wherein the NMOS transistor and the fuse form a driving path; a bypass resistor unit connected in parallel with the fuse; and a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.
In accordance with yet another embodiment of the present invention, a semiconductor integrated circuit includes: a fuse; a PMOS transistor configured to pull-up drive a sensing node in response to a first fuse sensing signal; a first NMOS transistor configured to pull-down drive the sensing node in response to a second fuse sensing signal; a second NMOS transistor the first NMOS transistor and configured to pull-down drive the sensing node in response to the first fuse sensing signal, wherein the first and second NMOS transistor and the fuse form a driving path; a bypass resistor unit connected between both ends of the fuse; and a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.
In accordance with still another embodiment of the present invention, a semiconductor memory device includes: a plurality of fuses; a first driving unit configured to pull-up drive a common sensing node in response to a precharge signal; a plurality of second driving units configured to pull-down drive the common sensing node in response to corresponding address information, wherein the plurality of second driving units and corresponding fuses form driving paths; a plurality of bypass resistor units connected in parallel with corresponding fuses; and a sensing unit configured to sense a programming state of each of the plurality of fuses in response to a voltage of the common sensing node.
Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
Referring to
The fuse FUSE and the bypass resistor unit 24 may be disposed anywhere on a pull-up path, and may be disposed on a pull-down path as the occasion demands.
The detailed circuit configuration of the fuse circuit exemplified in
The first driving unit 20 includes an NMOS transistor MN10 having a source that is connected to a ground voltage VSS, a drain that is connected to the sensing node A, and a gate that receives the first fuse sensing signal IN1.
The second driving unit 22 includes a PMOS transistor MP10 having a source that is connected to a power supply terminal VDD, a drain that is connected to a node B, and a gate that receives the second fuse sensing signal IN2.
The fuse FUSE is connected between node B and the sensing node A, and the bypass resistor unit 24 includes a resistor R that is connected between the node B and the sensing node A in parallel to the fuse FUSE.
The sensing unit 26 includes an inverter IV10 that has an input terminal connected to the sensing node A and outputs an output signal OUT, and an inverter IV11 that receives the output signal OUT and has an output terminal connected to the sensing node A.
First, in an initialization period (a first operation period) of the fuse circuit, the first and second fuse sensing signals IN1 and IN2 are both deactivated to a logic high level. At this time, the NMOS transistor MN10 is turned on to discharge the sensing node A, and the output signal OUT becomes a logic high level.
Next, in a fuse state sensing period (a second operation period) of the fuse circuit, the first and second fuse sensing signals IN1 and IN2 are both activated to a logic low level. Accordingly, the NMOS transistor MN10 is turned off and the PMOS transistor MP10 is turned on. Also, the pull-down NMOS transistor of the inverter IV11 continues driving for maintaining an initial value.
Where the fuse is not cut, the PMOS transistor MP10 performs pull-up driving for the sensing node A, and the pull-down NMOS transistor of the inverter IV11 performs pull-down driving for the sensing node A. More specifically, transition of the sensing node A is effected depending upon a ratio between the effective resistance value of pull-up devices (the PMOS transistor MP10, the fuse FUSE and the resistor R) and the effective resistance value of the pull-down device (the pull-down NMOS transistor of the inverter IV11). If a voltage level Va of the sensing node A becomes higher than a threshold logic value ViH of the inverter IV10 (Va>ViH) for a stable operation, the output signal OUT becomes a logic low level. The output signal OUT is fed back and turns on the PMOS transistor of the inverter IV11 such that the sensing node A can stably maintain a logic high level. This operation is not different from the operation of the fuse circuit shown in
Where the fuse FUSE is cut, while both ends of the fuse FUSE are actually not in an insulated state because both ends of the fuse FUSE are connected by the resistor R (for reference, a cut fuse has ideally a very high resistance value and has usually a resistance value equal to or greater than 1 MΩ), the voltage level Va of the sensing node A does not become unconditionally a logic low level. As described above, the voltage level Va of the sensing node A is determined by the ratio between the effective resistance value of the pull-up devices (the PMOS transistor MP10, the fuse FUSE and the resistor R) and the effective resistance value of the pull-down device (the pull-down NMOS transistor of the inverter IV11). As the voltage level Va of the sensing node A determined in this way is kept lower than the threshold logic voltage of the inverter IV10 (Va<ViL) for a stable operation, the output signal OUT becomes a logic high level and represents the cut state of the fuse FUSE.
The relationship between the DC characteristic curve (
Referring to
Also, referring to
VI and ViH are regulated as an input voltage Vin that defines a slope dVout/dVin of −1 in the DC characteristic curve showing the relationship of Vin and Vout of the inverter IV10. For reference, when assuming that the resistor R is connected to a general fuse circuit, a resistance value can be set approximately to 10 kΩ˜100 kΩ.
Next, in a third operation period (after the fuse state sensing period), the first fuse sensing signal IN1 maintains a logic low level, and the second fuse sensing signal IN2 transitions to a logic high level. Accordingly, the NMOS transistor MN10 maintains a turned-off state, and the PMOS transistor MP10 is turned off.
First, where the fuse FUSE is not cut, because the sensing node A transitioned to a logic high level in the second operation period that caused the output signal OUT to have a logic high level, the pull-up PMOS transistor of the feedback inverter IV11 is turned on and still maintains stably the sensing node A to a logic high level. At this time, since both ends of the fuse FUSE are connected to the resistor R, they maintain the same potential as a high level.
Where the fuse FUSE is cut, because the PMOS transistor MP10 is in a turned-off state, the sensing node A that has been maintained at a voltage level lower than the threshold logic value of the inverter IV10 during the second operation period is stabilized completely to a low level. At this time, since both ends of the fuse FUSE are connected to the resistor R, they maintain the same potential as a low level.
In the fuse circuit in accordance with the above embodiment of the invention, the programming state of the fuse can be stably sensed in the fuse state sensing period, and the same potential can be formed on both ends of the fuse after the fuse state sensing period, whereby electrical and chemical migration phenomena of metal ions can be originally prevented.
Hereinbelow, various embodiments will be described.
When comparing the fuse circuit of the present embodiment with the fuse circuit of the first embodiment shown in
Even in this embodiment, since only the positions of the pull-up devices are changed, the first and second fuse sensing signals IN1 and IN2 and operations of the entire fuse circuit are the same as those of the first embodiment.
When comparing the fuse circuit of the present embodiment with the fuse circuit of the first embodiment shown in
Similarly to the third embodiment shown in
Even in the third and fourth embodiments, since one PMOS transistor to be controlled by the first fuse sensing signal IN1 is added as a pull-up device when compared to the first and second embodiments, circuit operations are substantially the same. Sizes of the respective devices should be determined by adding the effective resistance value of the PMOS transistor to the above-stated design conditions.
Referring to
The inverter IV20 and the inverter IV21 constitute an inverting latch.
When compared to the fuse circuits of the first through fourth embodiments, the fuse circuit of the fifth embodiment is distinguished in that the fuse FUSE and the resistor R are disposed not on a pull-up path but on a pull-down path.
First, in an initialization period (a first operation period) of the fuse circuit, the first and second fuse sensing signals IN11 and IN12 are both deactivated to a logic low level. At this time, the PMOS transistor MP15 is turned on to charge the sensing node A1, and the output signal OUT becomes a logic low level.
Next, in a fuse state sensing period (a second operation period) of the fuse circuit, the first and second fuse sensing signals IN11 and IN12 are both activated to a logic high level. Accordingly, the PMOS transistor MP15 is turned off and the NMOS transistor MN15 is turned on. Also, the pull-up PMOS transistor of the inverter IV21 continues driving for maintaining an initial value.
Where the fuse FUSE is cut, while both ends of the fuse FUSE are actually not in an insulated state because both ends of the fuse FUSE are connected by the resistor R, the voltage level Va of the sensing node A1 does not become unconditionally a logic high level. As described above, the voltage level Va of the sensing node A1 is determined by the ratio between the effective resistance value of the pull-down devices (the NMOS transistor MN15, the fuse FUSE and the resistor R) and the effective resistance value of the pull-up device (the pull-up PMOS transistor MP16 of the inverter IV21). As the voltage level Va of the sensing node A1 determined in this way is kept higher than the threshold logic voltage of the inverter IV20 (Va>ViH) for a stable operation, the output signal OUT becomes a logic low level and represents a the cut state of the fuse FUSE.
Next, in a third operation period (after the fuse state sensing period), the first fuse sensing signal IN1 maintains a logic high level, and the second fuse sensing signal IN2 transitions to a logic low level. Accordingly, the PMOS transistor MP15 maintains a turned-off state, and the NMOS transistor MN15 is turned off.
First, where the fuse FUSE is not cut, because the sensing node A1 transitioned to a logic low level in the second operation period that caused the output signal OUT to have a logic high level, the pull-down NMOS transistor of the feedback inverter IV21 is turned on and still maintains stably the sensing node A1 to a logic low level.
At this time, since both ends of the fuse FUSE are connected to the resistor R, they maintain the same potential as a low level.
Where the fuse FUSE is cut, because the NMOS transistor MP15 is in a turned-off state, the sensing node A1 that has been maintained at a voltage level higher than the threshold logic value of the inverter IV20 during the second operation period is stabilized completely to a high level. At this time, since both ends of the fuse FUSE are connected to the resistor R, they maintain the same potential as a high level.
In the fuse circuit in accordance with the above embodiment of the invention, the programming state of the fuse can be stably sensed in the fuse state sensing period, and the same potential can be formed on both ends of the fuse after the fuse state sensing period, whereby electrical and chemical migration phenomena of metal ions can be originally prevented.
In the fifth embodiment of the present invention, because basic operations are the same except that the pull-up device performs an initializing function, and the fuse is disposed at the side of the pull-down devices as mentioned above. The circuit may be modified in the same manner as the second through fourth embodiments.
Referring to
A precharge signal PCGB is a signal that is deactivated to a logic high level when an active command ACT is applied and is activated to a logic low level when a precharge command PCG is applied. Fuse enable signals EN<0:x> include row address information that is applied when the active command ACT is applied and that is assigned to a cell block generally distinguished by a bit line sense amplifier (BLSA). An example of an optional fuse enable signal ENi is activated to a logic high level by receiving the active command ACT and is deactivated to a logic low level before a column address is applied. Accordingly, the activation period of the fuse enable signal ENi is realized to be shorter than a tRCDmin (a Ras to Cas delay time), which should be ensured in a DRAM.
Because the fuse enable signals EN<0:x> are not simultaneously activated, the states of respective nodes including a fuse output terminal (the sensing node), which is commonly used, are the same as those of
For reference, in
As is apparent from the above description, in the present invention, due to the fact that the same potential is realized at both ends of a fuse without modifying a process or physically changing a fuse, the occurrence of a fail due to electrical and chemical migration phenomena of metal ions may be prevented. Also, an increase in the number of circuit elements constituting a fuse circuit may be minimized, and a circuit area is not increased.
While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
For example, the logics exemplified in the above embodiments may be replaced with other logics or may be omitted, depending upon kinds and activation levels of used signals.
Also, while it was described in the above embodiments that the power supply voltage VDD is used as a pull-up voltage source and the ground voltage VSS is used as a pull-down voltage source, the present invention may be applied to a case in which these voltages being voltage sources are changed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2011-0040350 | Apr 2011 | KR | national |
