Semiconductor integrated circuit apparatus and control method thereof

Abstract

A semiconductor integrated circuit apparatus includes an internal logic circuit unit, a first memory, a second memory and a control circuit unit. The internal logic circuit unit includes scan chains which test circuit normality. The first memory is accessed by the internal logic circuit. The second memory stores valid bits associated with the first memory, wherein the valid bits indicates one of validity and invalidity of data stored in the first memory. The control circuit unit saves internal state data stored in the scan chains to the first memory, and resets the internal state data saved in the first memory to the scan chains.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic view for describing a first embodiment of the present invention;

FIG. 2 is a block diagram showing configuration of a semiconductor integrated circuit in accordance with the first embodiment of the present invention;

FIG. 3 is a view for describing correspondence between a cache memory and a valid bit memory;

FIGS. 4A to 4M are timing charts for describing a saving operation in accordance with the first embodiment;

FIGS. 5A to 5M are timing charts for describing a recovery operation in accordance with the first embodiment;

FIG. 6 is a schematic view for describing a second embodiment of the present invention;

FIG. 7 is a block diagram showing configuration of a semiconductor integrated circuit in accordance with the second embodiment of the present invention;

FIGS. 8A to 8O are timing charts (1) for describing a saving operation in accordance with the second embodiment;

FIGS. 9A to 90 are timing charts (2) for describing the saving operation in accordance with the second embodiment;

FIGS. 10A to 10N are timing charts (1) for describing a recovery operation in accordance with the second embodiment;

FIGS. 11A to 11N are timing charts (2) for describing a recovery operation in accordance with the second embodiment;

FIGS. 12A to 12O are timing charts (1) for describing a saving operation in accordance with a third embodiment;

FIGS. 13A to 13O are timing charts (2) for describing the saving operation in accordance with the third embodiment; and

FIGS. 14A to 14I are timing charts (3) for describing the saving operation in accordance with the third embodiment.

Claims

1. A semiconductor integrated circuit apparatus comprising: an internal logic circuit unit configured to include scan chains which test circuit normality;a first memory configured to be accessed by said internal logic circuit;a second memory configured to store valid bits associated with said first memory, wherein said valid bits indicates one of validity and invalidity of data stored in said first memory; anda control circuit unit configured to save internal state data stored in said scan chains to said first memory, and reset said internal state data saved in said first memory to said scan chains.

2. The semiconductor integrated circuit apparatus according to claim 1, wherein after said internal state data stored in said scan chains are saved to said first memory, power supply to said internal logic circuit unit is stopped while power supply to said first memory and said second memory is continued, and when power supply to said internal logic circuit unit is restarted, said internal state data saved in said first memory are reset to said scan chains.

3. The semiconductor integrated circuit apparatus according to claim 1, wherein said control circuit unit saves said internal state data to a sequence area from a certain address of said first memory, said control circuit unit saves said valid bits indicating invalidity associated with said sequence area to said second memory, andsaid control circuit unit resets said internal state data saved to said sequence area to said scan chains.

4. The semiconductor integrated circuit apparatus according to claim 1, wherein said control circuit unit includes: a scan enable creation portion configured to determine whether or not said valid bits stored in said second memory indicate invalidity,wherein said control circuit unit saves said internal state data to invalid area of said first memory, said invalid area is associated with said valid bits indicating invalidity which is determined by said scan enable creation portion.

5. The semiconductor integrated circuit apparatus according to claim 4, wherein when said first memory is deficient in said invalid area to be selected for saving said internal state data, said control circuit unit saves said internal state data to an area, of which said valid bits indicate invalidity, included in a first area of said first memory, and all of a second area of said first memory, andsaid control circuit unit saves said valid bits indicating invalidity and associated with said area of said first memory saving said internal state data to said second memory.

6. The semiconductor integrated circuit apparatus according to claim 5, wherein said first area and said second area are continued, and said control circuit unit dynamically determines a start address which indicates a boundary between said first area and said second area and is included in said second memory, based on a size of said area, where said valid bits indicate invalidity, and which is included in said first area.

7. The semiconductor integrated circuit apparatus according to claim 5, wherein said first area and said second area are continued, and said control circuit unit determines an end address of said second memory, based on a size of said area, where said valid bits indicate invalidity, and which is included in said first area and said second area.

8. The semiconductor integrated circuit apparatus according to claim 4, wherein said control circuit resets data, which are saved to an area of said first memory and are associated with said valid bits indicating invalid and saved to said second memory, as said internal state data to said scan chains.

9. The semiconductor integrated circuit apparatus according to claim 1, wherein said first memory is a cache memory which is provided for reducing access to a low speed memory.

10. A control method of a semiconductor integrated circuit apparatus, comprising: (a) providing a semiconductor integrated circuit apparatus which includes:an internal logic circuit unit configured to include scan chains which test circuit normality,a first memory configured to be accessed by said internal logic circuit, anda second memory configured to store valid bits associated with said first memory, wherein said valid bits indicates one of validity and invalidity of data stored in said first memory;(b) saving internal state data stored in said scan chains to said first memory; and(c) resetting said internal state data saved in said first memory to said scan chains.

11. The control method of a semiconductor integrated circuit apparatus according to claim 10, wherein said step (b) includes: (b1) after saving said internal state data stored in said scan chains to said first memory, stopping power supply to said internal logic circuit unit while continuing power supply to said first memory and said second memory, and(b2) restarting power supply to said internal logic circuit unit,wherein said step (c) is carried out after said step (b2) is carried out.

12. The control method of a semiconductor integrated circuit apparatus according to claim 10, wherein said step (b) includes: (b3) saving said internal state data to a sequence area from a certain address of said first memory, and(b4) saving said valid bits indicating invalidity associated with said sequence area to said second memory,wherein said step (c) includes;(c1) resetting said internal state data saved to said sequence area to said scan chains.

13. The control method of a semiconductor integrated circuit apparatus according to claim 10, wherein said step (b) includes: (b5) determining whether or not said valid bits stored in said second memory indicate invalidity, and(b6) saving said internal state data to invalid area of said first memory, said invalid area is associated with said valid bits indicating invalidity which is determined by said scan enable creation portion.

14. The control method of a semiconductor integrated circuit apparatus according to claim 13, wherein said step (b) further includes: (b7) when said first memory is deficient in said invalid area to be selected for saving said internal state data, saving said internal state data to an area, of which said valid bits indicate invalidity, included in a first area of said first memory, and all of a second area of said first memory, and(b8) saving said valid bits indicating invalidity and associated with said area of said first memory saving said internal state data to said second memory.

15. The control method of a semiconductor integrated circuit apparatus according to claim 14, wherein said first area and said second area are continued, and wherein said step (b1) includes:(b71) dynamically determining a start address which indicates a boundary between said first area and said second area and is included in said second memory, based on a size of said area, where said valid bits indicate invalidity, and which is included in said first area.

16. The control method of a semiconductor integrated circuit apparatus according to claim 14, wherein said first area and said second area are continued, and wherein said step (b7) includes:(b72) determining an end address of said second memory, based on a size of said area, where said valid bits indicate invalidity, and which is included in said first area and said second area.

17. The control method of a semiconductor integrated circuit apparatus according to claim 13, wherein said step (c) includes: (c1) resetting data, which are saved to an area of said first memory and are associated with said valid bits indicating invalid and saved to said second memory, as said internal state data to said scan chains.

18. The control method of a semiconductor integrated circuit apparatus according to claim 10, wherein said first memory is a cache memory which is provided for reducing access to a low speed memory.