Semiconductor integrated circuit device and dummy pattern arrangement method

Abstract

A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer 12, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 2 is a sectional view of the semiconductor integrated circuit device of the first embodiment;

FIG. 3 shows a data rate example of dummy patterns of the semiconductor integrated circuit device of the first embodiment;

FIG. 4 is a block diagram of a semiconductor chip according to a second embodiment of the present invention;

FIG. 5 shows an arrangement example of dummy patterns of the second embodiment;

FIG. 6 is a plan view of a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 7 is a sectional view of the structure of the semiconductor integrated circuit device of the third embodiment;

FIGS. 8A to 8E show a shape example of dummy patterns of the third embodiment;

FIG. 9 is a plan view of the structure of a conventional semiconductor integrated circuit device;

FIG. 10 is a plan view of the structure of the conventional semiconductor integrated circuit device; and

FIG. 11 shows a data rate example of dummy patterns of the conventional semiconductor integrated circuit device.

Claims

1. A semiconductor integrated circuit device, comprising: a functional circuit region formed on a semiconductor substrate;a dummy region formed on the semiconductor substrate; anda plurality of dummy MOSFETs arranged in the dummy region, each of the dummy MOSFETs having a dummy diffusion region and a dummy gate electrode region,wherein a first data rate of the dummy diffusion region arranged in a predetermined section and a second data rate of the dummy gate electrode region arranged in the predetermined section is substantially constant.

2. The semiconductor integrated circuit device according to claim 1, wherein the plurality of dummy MOSFETs are arranged at substantially regular intervals in the dummy region.

3. The semiconductor integrated circuit device according to claim 1, wherein the plurality of dummy MOSFETs are arranged regularly and two-dimensionally in the dummy region.

4. The semiconductor integrated circuit device according to claim 1, wherein a size of the dummy diffusion region of the dummy MOSFET is substantially equal to a size of the dummy gate electrode of the dummy MOSFET as viewed from above.

5. The semiconductor integrated circuit device according to claim 1, wherein the dummy region is provided between adjacent functional circuit regions.

6. The semiconductor integrated circuit device according to claim 1, wherein the dummy diffusion region of the dummy MOSFET extends in the same direction as that of a diffusion region of a MOSFET in the functional circuit region, and the dummy gate electrode of the dummy MOSFET extends in the same direction as that of a gate electrode of a MOSFET in the functional circuit region.

7. The semiconductor integrated circuit device according to claim 1, wherein the first data rate of the dummy diffusion region of the dummy MOSFET and the second data rate of the dummy gate electrode of the dummy MOSFET is within a range of 25% to 75% in the predetermined section.

8. The semiconductor integrated circuit device according to claim 1, wherein the dummy diffusion region of one of the plurality of dummy MOSFETs is connected to a predetermined reference potential.

9. The semiconductor integrated circuit device according to claim 8, wherein the predetermined reference potential is a substrate potential or a well potential.

10. The semiconductor integrated circuit device according to claim 8, wherein a P-type diffusion region among the dummy diffusion regions of the plurality of dummy MOSFETs is connected to a ground potential, and an N-type diffusion region among the dummy diffusion regions of the plurality of dummy MOSFETs is connected to a power supply potential.

11. The semiconductor integrated circuit device according to claim 8, wherein a dummy MOSFET having a P-type diffusion region among the dummy diffusion regions is formed in a P-type semiconductor substrate or a P-type well, and a dummy MOSFET having an N-type diffusion region among the dummy diffusion regions is formed in an N-type semiconductor substrate or N-type well.

12. The semiconductor integrated circuit device according to claim 1, wherein the dummy gate electrode of one of the plurality of dummy MOSFETs is connected to a predetermined potential.

13. The semiconductor integrated circuit device according to claim 1, wherein at least one of the plurality of dummy MOSFETs is a spare element connected to the functional circuit of the functional circuit region and operating as a component of the functional circuit.

14. The semiconductor integrated circuit device according to claim 13, wherein a dummy MOSFET having a P-type diffusion region among the dummy diffusion regions is formed in an N-type semiconductor substrate or N-type well, and a dummy MOSFET having an N-type diffusion region among the dummy diffusion regions is formed in a P-type semiconductor substrate or P-type well.

15. The semiconductor integrated circuit device according to claim 13, wherein the dummy diffusion region and gate electrode of the plurality of dummy MOSFETs are connected to metal wiring, and the metal wiring is connected to the functional circuit.

16. The semiconductor integrated circuit device according to claim 15, wherein the metal wiring is connected to the functional circuit due to a change of a mask pattern in a metal wiring step of forming the metal wiring or connected to the functional circuit in a step after the metal wiring step.

17. A dummy pattern arrangement method, comprising: arranging a functional circuit region on a semiconductor substrate; andarranging a plurality of dummy MOSFETs in a dummy region on the semiconductor substrate, each of the dummy MOSFETs having a dummy diffusion region and a dummy gate electrode region, and the plurality of dummy MOSFETs are arranged in a manner such that a first data rate of the dummy diffusion region arranged in a predetermined section and a second data rate of the dummy gate electrode region arranged in the predetermined section is set substantially constant.

18. The dummy pattern arrangement method according to claim 17, wherein the plurality of dummy MOSFETs are arranged at substantially regular intervals in the dummy region.

19. The dummy pattern arrangement method according to claim 17, wherein a size of the dummy diffusion region is substantially equal to a size of the dummy gate electrode as viewed from above.

20. The dummy pattern arrangement method according to claim 17, wherein a plurality of dummy MOSFETs are arranged between adjacent functional circuit regions.