Semiconductor integrated circuit device and method of controlling the same

Abstract

Sub bit lines are connected to associated main bit lines, which are common to a plurality of memory blocks, through respective first MOS field effect transistors. The main bit lines are grounded through respective second MOS field effect transistors. When the first and second MOS field effect transistors are turned on, charges accumulated in drain regions of nonvolatile memory cells are extracted via the first MOS field effect transistors, the main bit lines and the second MOS field effect transistors.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuit device and the method of controlling the same.

An EEPROM (electrically erasable programmable read-only memory), one of different kinds of nonvolatile memories, has a plurality of memory cells. A known memory Ad cell consists of a floating gate field effect transistor (FET) with a double-layer electrode structure composed of a source region, a drain region, a channel region, a floating gate electrode provided on the channel region via an insulating film, and a control gate electrode provided on the floating gate electrode via an insulating film. A control signal is sent to the control gate electrode via a word line. As a structure of the word line, a structure constituted by a main word line and a sub word line connected to the main word line via a switching element is known. Such a structure is employed in a conventional flash memory, in which a large amount of currents flow into memory cells during a read or write operation. This is because, when a structure composed of a bit line and a sub bit line is employed in the flash memory, a voltage across the switching element for connecting the main bit line and the sub bit line falls markedly and this may result in misreading of the memory cells or an increased load on a circuit for generating a write voltage.

The flash memory has a plurality of memory blocks with memory cells arranged in a matrix therein. Each of the memory blocks is provided with a bit line decoder and bit lines, independently of the other memory blocks. Information is read from the flash memory having such a configuration as follows.

First, a switching element connecting a main word line and a sub word line is turned on to select the main word line and the sub word line, and then a voltage required for a read operation is applied to the sub word line through the main word line. Subsequently, a predetermined voltage is applied to a selected bit line to select a memory cell. Then, a current flowing through the selected memory cell is compared with a predetermined reference value by a differential amplifier, and a result determined based on the comparison is output as data.

At this time, when a charge remains in drains of unselected memory cells commonly connected to the sub word line, that is, memory cells for which the associated word line is selected and of which the sources have a low potential, the charge accumulated in the drain is pulled out, or extracted to the source side. In the flash memory, since memory cells in the same memory block usually have their sources commonly connected, currents to the sources in these unselected memory cells raise a source potential and may result in misreading.

Furthermore, since the charge in the drain is pulled to the source side in the unselected memory cells, hot electrons, that is, high-energy electrons are generated, and the electrons are injected into the floating gate electrodes of the unselected memory cells. Therefore, the threshold value of the unselected memory cells may rise.

Therefore, in general, the bit lines connected to the drains of the memory cells are connected to a discharge circuit via a switching element so that the charge in the drains of the memory cells is extracted via the bit lines when the flash memory is in a standby state, that is, a non-access state.

Meanwhile, in the conventional flash memory, when electrons are extracted from a floating gate electrode of a memory cell (an erase operation is assumed here), a method of applying a negative voltage to a word line is employed in general. In this case, the following problems occur in a flash memory having main word lines and sub word lines, the latter being provided in each memory block independently of the other memory blocks.

The switching element connecting the main word line and the sub word line needs to transmit a positive voltage during read and write operations and a negative voltage during an erase operation. Therefore, voltage control of the switching element becomes complicated and a control circuit provided to apply the positive voltage and the negative voltage to the switching element disadvantageously enlarges the memory.

An example of a semiconductor integrated circuit device having main word lines and sub word lines like the above-described flash memory is shown in FIG. 5 . The semiconductor integrated circuit device has a memory cell region M made up of a plurality of memory blocks MB 0 , . . . , MB X and main word lines WLM 0 , . . . , WLM n commonly connected to the plurality of memory block MB 0 , . . . , MB X . Each memory block MB 0 , . . . , MB X has a plurality of memory cells MC 00 , . . . , MC nm arranged in a matrix. Each memory cell MC 00 , . . . , MC nm , consists of a floating gate type field effect transistor having a control electrode and a floating electrode. Furthermore, in each of the memory blocks MB 0 , . . . , MB X , drain regions of the memory cells in the same column are commonly connected by an associated bit line BL 0 , . . . , or BL m , while control gate electrodes of the memory cells in the same row are commonly connected by a sub word line WLS 0 , . . . , or WLS n . Furthermore, P-type MOS (Metal Oxide Semiconductor) field effect transistors LWS 00 , . . . , LWS Xn for selecting sub word lines WLS 0 , . . . , WLS n are provided in each of the memory blocks MB 0 , . . . , MB X . The P-type MOS field effect transistors LWS 00 , . . . , LWS Xn of each memory block are connected to a sub word line selecting circuit 100 via an associated memory block selecting gate line BS 0 , . . . , or BS X and to a voltage switching circuit 200 for switching between a back bias high voltage and a voltage VSS via an associated back bias supply line NW 0 , . . . , or NW X . Furthermore, to pull out a charge accumulated in the bit line BL 0 , . . . , BL m , the bit line BL 0 , . . . , BL m is grounded via a MOS field effect transistor DC 0 , . . . , DC m . The MOS field effect transistor DC 0 , . . . , DC m is controlled by a discharge selecting gate line DDC 0 , . . . , DDC m . Furthermore, the main word line WLM 0 , . . . , WLM n and the sub word line WLS 0 , . . . , WLS n are connected via the P-type MOS field effect transistor LWS 00 , . . . , LWS Xn . A voltage is supplied from a main word line decoder MWD to the main word line WLM 0 , . . . , WLM n . Furthermore, in the sub word line selecting circuit 100 from which a voltage is supplied to a P-type MOS field effect transistor LWS 00 , . . . , LWS Xn , control for generating a negative voltage required depending on the operation is performed. As is obvious, since the field effect transistors DC 0 , . . . , DC m , the sub word line selecting circuit 100 and the voltage switching circuit 200 are required in each memory block MB 0 , . . . , MB X , the circuit size becomes large.

Hereafter, voltage control during a read operation in the semiconductor integrated circuit device will be explained below with reference to FIG. 6 . In FIG. 6 , it is assumed that a memory cell MC 00 in the memory block MB 0 is selected.

In a read operation, as shown in FIG. 6 , a voltage of about 5 V is applied to the control gate electrode of the memory cell MC 00 , while a voltage of about 1 V is applied to the drain region of the memory cell MC 00 . At this time, a voltage to be applied to the control gate electrodes of unselected memory cells MC 10 , . . . , MC 1m ; . . . ; MC n0 , . . . , MC nm in the memory block MB 0 needs to be set at 0 V. Therefore, a voltage of −5 V is applied to the memory block selecting gate line BS 0 , and the main word lines WLM 1 −WLM n at 0 V are electrically connected to the associated sub word line WLS 1 −WLS n .

Voltage control during a write operation in the semiconductor integrated circuit device is explained below with reference to FIG. 7 . In FIG. 7 , it is assumed that a memory cell MC 00 in the memory block MB 0 is selected.

During a write operation, as shown in FIG. 7 , a voltage of about 10 V is applied to the control gate electrode of the memory cell MC 00 , while a voltage of 4 to 5 V is applied to the drain region of the memory cell MC 00 . At this time, a voltage to be applied to the control gate electrodes of unselected memory cells MC 10 , . . . , MC 1m ; . . . ; MC n0 , . . . , MC nm in the memory block MB 0 needs to be set at 0 V. Therefore, a voltage of the memory block selecting gate line BS 0 must be a negative voltage. Furthermore, a voltage of 10 V must not be applied to the sub word lines WLS 0 , . . . , WLS n in the unselected memory blocks MB 1 , . . . , MB X so that write reliability is ensured. That is, the voltage of the control gate electrodes of the memory cells MC 00 , . . . , MC nm in the unselected memory blocks MB 1 , . . . , MB X needs to be 0 V. Therefore, a voltage of about 10 V is applied to the gate electrodes of the P-type MOS field effect transistors LWS 10 —LWS xn in the unselected memory blocks MB 1 , . . . , MB X . Meanwhile, when a voltage of about −5 V similar to that of the read operation is applied to the gate electrode of the P-type MOS field effect transistor LWS 00 , . . . , LWS 0n in the selected memory block MB 0 , a voltage across the source and gate electrode of the P-type MOS field effect transistor LWS 00 exceeds the withstand or breakdown voltage, and the P-type MOS field effect transistor LWS 00 may be damaged. Therefore, during the write operation, the gate voltage of the P-type MOS field effect transistor LWS 00 , . . . , LWS 0n in the selected memory block MB 0 is generally set at a voltage smaller than that of the read operation, for example, −2 V.

As described above, in the case of a semiconductor integrated circuit device having main word lines WLM 0 , . . . , WLM n and sub word lines WLS 0 , . . . , WLS n , voltage control of gate electrodes of switching elements LWS 00 , . . . , LWS Xn or the like is essential during each of read and write operations. Therefore, a back bias control circuit of switching elements LWS 00 , . . . , LWS Xn selecting the sub word lines WLS 0 , . . . , WLS n and a circuit for controlling gate voltages of switching elements LWS 00 , . . . , LWS Xn are required. As a result, the control circuit becomes complicated and the peripheral circuit is enlarged, which may result in a larger chip size.

Meanwhile, with recent development in fine processing technology, a lower operating current for a memory cell has been achieved. Consequently, memory array configuration having main bit lines and sub bit lines has become employable in a semiconductor integrated circuit device. Since each memory block has word lines independently of the other memory blocks in the semiconductor integrated circuit device having main bit lines and sub bit lines, the switching elements requiring complicated voltage control become unnecessary. Furthermore, since the wiring capacitance of the word line is decreased, time required for reading or writing data from/to the memory cell can be shortened.

However, even in the semiconductor integrated circuit device having main bit lines and sub bit lines, a switching element for extracting a charge accumulated in the drain region of the memory cell at the time of standby (at the time of non-access) needs to be disposed in each memory block. As a result, a circuit for controlling the switching element is required in each memory block, and thus a problem arises that the circuit size is increased.

Examples of the semiconductor integrated circuit device having main bit lines and sub bit lines described above include the one disclosed in Japanese Patent Laid-Open Publication No. 9-153559. The semiconductor integrated circuit device described in this Japanese Patent Laid-Open Publication is provided with elements for pulling a charge accumulated in the drain regions of memory cells without passing through the memory cells and has a path for eliminating the charge. However, according to the semiconductor integrated circuit device of the Japanese Patent Laid-Open Publication No. 9-153559, since the elements for pulling the charge and a circuit for controlling the elements are provided in each of a plurality of memory blocks, a problem arises that a circuit occupation area around the memory block is increased.

SUMMARY OF THE INVENTION

Accordingly, the object of the present invention is to provide a semiconductor integrated circuit device which is allowed to have a reduced circuit occupation area, and a method of controlling the same.

A semiconductor integrated circuit device according to the present invention includes a plurality of memory blocks. Each memory block includes:

a plurality of nonvolatile memory cells arranged in a matrix form, each nonvolatile memory cell having a gate region, a source region and a drain region;

word lines each of which is commonly connected to the gate regions of the nonvolatile memory cells in the same row;

a source line which is commonly connected to the source regions of the nonvolatile memory cells;

sub bit lines each of which is commonly connected to the drain regions of the nonvolatile memory cells in the same column; and

first switching elements for selecting the associated sub bit lines,

The plurality of memory blocks being arranged in a column direction, and the semiconductor integrated circuit device further includes:

main bit lines which are common to the plurality of memory blocks and to which the sub bit lines in each memory block are connected via the respective first switching elements; and

at least one second switching element for extracting charges accumulated in drain regions of the nonvolatile memory cells via the first switching elements and the main bit lines.

According to the semiconductor integrated circuit device having the above configuration, when the first and second switching elements are turned on, charges accumulated in the drain regions of the nonvolatile memory cells are extracted or pulled out via the first switching elements and the main bit line. Since the charges in the drain regions of the nonvolatile memory cells are extracted therefrom via the first switching elements and the main bit lines, no switching elements for extracting the charges from the drain regions of the nonvolatile memory cells need to be provided on the sub bit lines. That is, no second switching elements for extracting the charges need to be provided in each memory block. Therefore, no circuits for controlling the second switching elements for extracting the charges need to be provided for each memory block, either. Thus the circuit occupation area of the semiconductor integrated circuit device of the present invention can be reduced.

Furthermore, because each of the main bit lines is commonly used by the plurality of memory blocks, control for extracting charges does not need to be performed in each memory block. Therefore, the control for extracting the charges from the drain regions of the nonvolatile memory cells is simplified.

Each memory cell may be constituted of a floating gate type field effect transistor.

In one embodiment, one second switching element is provided for one main bit line. Thus, a charge can be extracted every main bit line by controlling the second switching elements.

In one embodiment, the main bit lines are grounded via the at least one second switching element. Thus, the charge accumulated in the drain region of the nonvolatile memory cell can be allowed to escape to the ground.

The first switching elements in one memory block may be connected to a common signal line.

In one embodiment, each of the first switching elements is constituted of a MOS field effect transistor through which the sub bit lines are connected to the associated bit lines. Also, the gates of the MOS field effect transistors in one memory block are commonly connected to a memory block selecting gate line.

The present invention also provides a method of controlling the semiconductor integrated circuit device with the above arrangement. In the controlling method, upon completion of at least one of read, write and erase operations of selected nonvolatile memory cells in the memory blocks, the first switching elements and the at least one second switching element are turned on.

With this controlling method, occurrence of hot electrons can be prevented by extracting the charges in the drain regions of the nonvolatile memory cells via the first switching elements, the main bit lines and the at least one second switching element.

The present invention provides another method of controlling the semiconductor integrated circuit device with the above arrangement. In this controlling method, upon completion of each of read, write and erase operations of selected nonvolatile memory cells in the memory blocks, the first switching elements are turned on.

According to this controlling method, since the first switching elements are in an on state before and after the read, write and erase operations of the selected nonvolatile memory cells in the memory blocks, charges in the drain regions of the nonvolatile memory cells are extracted only by turning on the second switching element. Therefore, control for extracting the charges before and after the read, write and erase operations of the selected nonvolatile memory cells is simplified.

Furthermore, the present invention provides a still another method of controlling the semiconductor integrated circuit device with the above configuration. In the controlling method, the first switching elements and the at least one second switching element are turned on in a standby state of the device to thereby extract charges accumulated in the drain regions of the nonvolatile memory cells.

With this controlling method, occurrence of hot electrons after the device is released from the standby state can be prevented.

Other objects, features and advantages of the present invention will be obvious from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

FIG. 1 is a circuit diagram showing a substantial portion of a semiconductor integrated circuit device according to one embodiment of the invention;

FIG. 2 is a circuit diagram for explaining a standby state of the semiconductor integrated circuit device;

FIG. 3 is a circuit diagram for explaining a read operation of the semiconductor integrated circuit device;

FIG. 4 is a circuit diagram for explaining a write operation of the semiconductor integrated circuit device;

FIG. 5 is a circuit diagram showing a substantial portion of the conventional semiconductor integrated circuit;

FIG. 6 is a circuit diagram for explaining a read operation of the conventional semiconductor integrated circuit device; and

FIG. 7 is a circuit diagram for explaining a write operation of the conventional semiconductor integrated circuit device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the semiconductor integrated circuit device and a method of controlling the same according to the present invention will be described in detail below with reference to accompanying drawings.

FIG. 1 is a circuit diagram showing a substantial portion of a semiconductor integrated circuit device according to one embodiment of the present invention.

As shown in FIG. 1 , the semiconductor integrated circuit device has a memory cell region M constituted of a plurality of memory blocks MB 0 , . . . , MB X . Although not shown, further memory cell regions M are arrayed in a horizontal direction, and word lines WL 00 , . . . , WL Xn are commonly used. In each of the memory blocks MB 0 , . . . , MB X , a plurality of nonvolatile memory cells MC 00 , . . . , MC Nn are arranged in a matrix, namely in rows and columns. Each of the nonvolatile memory cells MC 00 , . . . , MC Nn is a floating gate type field effect transistor having a double-layer electrode structure composed of a source region, a drain region, a channel region, a floating gate electrode provided on the channel region via an insulating film and a control gate electrode provided on the floating gate electrode via an insulating film although not shown in the figure. Furthermore, each of the memory blocks MB 0 , . . . , MB X has word lines WL 00 , . . . , WL Xn to which gate regions of the nonvolatile memory cells MC 00 . . . MC N0 ; MC 01 . . . MC N1 ; . . . ; MC 0n . . . MC Nn in the same row are commonly connected, source lines SL 0 , . . . , SL X to which source regions of the nonvolatile memory cells MC 00 , . . . , MC Nn are commonly connected, and sub bit lines BLS 00 , . . . , BLS XN to which drain regions of the nonvolatile memory cells MC 00 . . . MC 0n ; MC 10 . . . MC 1n ; . . . ; MC N0 . . . MC Nn in the same column are commonly connected. Furthermore, the memory blocks MB 0 , . . . , MB X are provided with first MOS field effect transistors Q 1S00 , . . . , Q 1SXN as first switching elements for selecting each sub bit line BLS 00 , . . . , BLS XN . Furthermore, the nonvolatile memory cells MC 00 , . . . , MC Nn are connected in parallel between the sub bit lines BLS 00 , . . . , BLS XN and the source lines SL 0 , . . . , SL X .

Furthermore, the semiconductor integrated circuit device has main bit lines BLM 0 , . . . , BLM N commonly connected to a plurality of memory blocks MB 0 , . . . , MB X for each column.

The sub bit lines BLS 00 , . . . , BLS XN in each memory block MB 0 , . . . , MB X are electrically connected to the main bit lines BLM 0 , . . . , BLM N via the respective first MOS field effect transistors Q 1S00 , . . . , Q 1SXN . Furthermore, second MOS field effect transistors Q 2S0 , . . . , Q 2SN are provided as second switching elements for each of the main bit lines BLM 0 , . . . , BLM N , and one end of each main bit line BLM 0 , . . . , BLM N is electrically connected to a ground potential VSS via the respective second MOS field effect transistors Q 2S0 , . . . , Q 2SN . Meanwhile, the other end of each main bit line BLM 0 , . . . , BLM N is electrically connected to a sense amplifier SA 0 , . . . , SA N via a third MOS field effect transistor Q SE0 , . . . , Q SEN . The second MOS field effect transistor Q 2S0 , . . . , Q 2SN receives a signal from a discharge selecting gate line DDC 0 , . . . , DDC N , and the third MOS field effect transistor Q SE0 , . . . , Q SEN receives a signal from a main bit line selecting gate line TR 0 , . . . , TR N . Reference symbol SREF in FIG. 1 denotes a signal line for transmitting a reference voltage level for comparison when a nonvolatile memory cell MC 00 , . . . , MC Nn in a memory block MB 0 , . . . , MB X is read. This signal line SREF is connected to each sense amplifier SA 0 , SA 1 , . . . , SA N . Furthermore, the first MOS field effect transistors Q 1S00 , . . . , Q 1SXN are driven by the memory block selecting gate lines BS 0 , . . . , BS X . The first MOS field effect transistors Q 1S00 , . . . , Q 1SXN in each memory block MB 0 , . . . , MB X are commonly connected to the associated memory block selecting gate line BS 0 , . . . , BS X .

In FIG. 1 , the subscript ‘X’ corresponds to a block number. That is, the number of the memory blocks MB 0 , . . . , MB X is (X+1). The subscript ‘n’ for the word lines WL 00 , . . . , WL Xn and ‘N’ for the main bit line BLM 0 , . . . , BLM N correspond to the numbers of those lines, respectively. That is, the number of the word lines WL 00 , . . . , WL Xn is (n+1) in each memory block MB 0 , . . . , MB X and (X+1)·(n+1) in the whole circuit, while the number of the main bit lines BLM 0 , . . . , BLM N is (N+1) in the whole circuit. Furthermore, the number of the nonvolatile memory cells MC 00 , . . . , MC Nn corresponds to the numbers of the word lines WL 00 , . . . , WL Xn and the main bit lines BLM 0 , . . . , BLM N . Consequently, the number of the nonvolatile memory cells MC 00 , . . . , MC Nn is (N+1)·(n+1) in each memory block MB 0 , . . . , MB X and (X+1)·(N+1)·(n+1) in the whole circuit. It is noted that X, N and n are natural numbers. Furthermore, the number of the first MOS field effect transistors Q 1S00 , . . . , Q 1SXN connected to one main bit line BLM 0 , . . . , BLM N is (X+1).

According to the semiconductor integrated circuit device having the above configuration, when the first MOS field effect transistor Q 1S00 , . . . , Q 1SXN is turned on while the second MOS field effect transistor Q 2S0 , . . . , Q 2SN is turned on, a charge accumulated in a region between the nonvolatile memory cell MC 00 , . . . , MC Nn and the first MOS field effect transistor Q 1S00 , . . . , Q 1SXN , that is, the drain region of the nonvolatile memory cell MC 00 , . . . , MC Nn is extracted via the first MOS field effect transistor Q 1S00 , . . . , Q 1SXN and the main bit line BLM 0 , . . . , BLM N . Since the charge is extracted from the drain region of the nonvolatile memory cell MC 00 , . . . , MC Nn via the first MOS field effect transistor Q 1S00 , . . . , Q 1SXN and the main bit line BLM 0 , . . . , BLM N , no specialized switching elements for extracting a charge in the drain regions of the nonvolatile memory cells MC 00 , . . . , MC Nn are provided on the sub bit lines BLS 00 , . . . , BLS XN in each memory block. Accordingly, a circuit for controlling such specialized switching elements for extracting a charge is not provided for each memory block MB 0 , . . . , MB X , either. Thus, the circuit occupation area is smaller than the conventional circuit occupation area.

Furthermore, since the main bit line BLM 0 , . . . , BLM N is shared or commonly used by the plurality of memory blocks MB 0 , . . . , MB X , control for extracting the charge does not need to be performed in each memory block MB 0 , . . . , MB X . Therefore, the control for extracting the charge from the drain regions of the nonvolatile memory cells MC 00 , . . . , MC Nn is simplified.

Furthermore, since the second MOS field effect transistor Q 2S0 , . . . , Q 2SN is provided on each main bit line BLM 0 , . . . , BLM N , a charge can be extracted from each main bit line BLM 0 , . . . , BLM N by controlling the second MOS field effect transistor Q 2S0 , . . . , Q 2SN .

Furthermore, since the main bit line BLM 0 , . . . , BLM N is grounded via the second MOS field effect transistor Q 2S0 , . . . , Q 2SN , a charge accumulated in the drain region of the nonvolatile memory cell MC 00 , . . . , MC Nn can be allowed to escape to the ground.

A read operation and a write operation of the semiconductor integrated circuit device will be explained below with reference to FIGS. 2 , 3 and 4 . In FIGS. 2 , 3 and 4 , only one of the main bit lines BLM 0 , . . . , BLM N is representatively shown. Therefore, the subscripts 0−N for the main bit lines are omitted from the reference numerals in FIGS. 2 , 3 and 4 .

First, the read operation of the semiconductor integrated circuit device will be explained.

Before the read operation is started, a voltage Vcc is applied to the memory block selecting gate lines BS 0 , . . . , BS X , as shown in FIG. 2 , to turn on all the first MOS field effect transistors Q 1S0 , . . . , Q 1SX . Then, a voltage Vcc is applied to the discharge selecting gate line DDC to turn on the second MOS field effect transistor Q 2S . A charge accumulated in the main bit line BLM and a parasitic capacitor C 0 , . . . , C X connected to the sub bit line BLS 0 , . . . , BLS X in each memory block MB 0 , . . . , MB X is discharged to a ground potential VSS.

Subsequently, when the read operation is performed, the sub bit line selecting signals BS 1 , . . . , BS X are set at 0 V in unselected memory blocks MB 1 , . . . , MB X to turn off their first MOS field effect transistors Q 1S1 , . . . , Q 1SX . Then, the discharge selecting gate line DCC is set at 0 V to turn off the second MOS field effect transistor Q 2S . On the other hand, in the selected memory block MB 0 , a voltage of, for example, about 5 V is applied to a selected word line WL 0 , while the other unselected word lines WL 1 , . . . , WL n are set at 0 V. At this time, a voltage of, for example, about 1 V is applied to the main bit line BLM, while the voltage of the source line SL is set at 0 V.

Then, after the read operation has been finished, the memory block selecting gate lines BS 0 , . . . , BS X are set at Vcc again as shown in FIG. 2 to turn on the first MOS field effect transistors Q 1S0 , . . . , Q 1SX in the memory blocks MB 0 , . . . , MB X . Then, the discharge selecting gate line DDC is set at Vcc to turn on the second MOS field effect transistor Q 2S . Consequently, a charge accumulated in the main bit line BLM and the sub bit line BLS 0 , . . . , BLS X is discharged to the ground potential VSS via the first MOS field effect transistor Q 1S0 , . . . , Q 1SX , the main bit line BLM and the second MOS field effect transistor Q 2S .

The write operation of the semiconductor integrated circuit device will be explained below.

Before the write operation is started, the memory block selecting gate lines BS 0 , . . . , BS X are set at a high voltage, that is, Vcc, as shown in FIG. 2 , to turn on all the first MOS field effect transistors Q 1S0 , . . . , Q 1SX , while the discharge selecting gate line DDC is set at Vcc to turn on the second MOS field effect transistor Q 2S . Consequently, a charge accumulated in the main bit line BLM and a parasitic capacitor C 0 , . . . , C X connected to the sub bit line BLS 0 , . . . , BLS X in each memory block MB 0 , . . . , MB X is discharged to the ground potential VSS.

Subsequently, when the write operation is performed, memory block selecting gate lines BS 1 , . . . , BS X of unselected memory blocks MB 1 , . . . , MB X are set at 0 V, as shown in FIG. 4 , to turn off their first MOS field effect transistors Q 1S1 , . . . , Q 1SX . Furthermore, the discharge selecting gate line DDC is set at 0 V to turn off the second MOS field effect transistor Q 2S . Then, a high voltage of about 12 V is applied to the first MOS field effect transistor Q 1S0 of the selected memory block MB 0 . Consequently, a voltage of about 4 to 5 V is transmitted from the selected main bit line BLM to the drain region of the memory cell MC 0 , . . . , MC n in the memory block MB 0 . At this time, for example, a voltage of about 10 V is applied to a selected word line WL 0 , while the other unselected word lines WL 1 , . . . , WL X are set at 0 V. Furthermore, the source line SL 0 of the memory block MB 0 is set at 0 V.

After the write operation has been finished, the memory block selecting gate lines BS 0 , . . . , BS X are set at a high voltage, that is, Vcc again, as shown in FIG. 2 , to turn on the first MOS field effect transistors Q 1S0 , . . . , Q 1SX in each memory block MB 0 , . . . , MB X . At this time, the discharge selecting gate line DDC is set at Vcc to turn on the second MOS field effect transistor Q 2S . Consequently, a charge accumulated in the main bit line BLM and the sub bit line BLS 0 , . . . , BLS X is discharged to the ground potential VSS via the first MOS field effect transistor Q 1S0 , . . . , Q 1SX , the main bit line BLM and the second MOS field effect transistor Q 2S .

Because the charges are thus extracted from the drain regions of the nonvolatile memory cells MC 0 , . . . MC n before and after the read and write operations of the selected nonvolatile memory cell MC 0 in the memory block MB 0 , occurrence of hot electrons is prevented.

In the above embodiment, the second MOS field effect transistors Q 2S0 , . . . , Q 2SN as the second switching elements are provided for the respective main bit lines BLM 0 , . . . , BLM N . However, a plurality of main bit lines BLM 0 , . . . , BLM N may be connected to one common line and the second MOS field effect transistor Q 2S may be provided on this common line. In this case, a plurality of main bit lines BLM 0 , . . . , BLM N are controlled by one second MOS field effect transistor Q 2S .

Furthermore, the sub bit lines BLS 00 , . . . , BLS XN are not grounded in the above embodiment, but may be grounded via a switching element. That is, the switching element for extracting a charge in the drain region of the nonvolatile memory cell MC 00 , . . . , MC Nn may be provided on the main bit line BLM 0 , . . . , BLM N .

Furthermore, before and after the read and write operations of the selected nonvolatile memory cell MC 0 in the memory block MB 0 , the first MOS field effect transistor Q 1S0 , . . . , Q 1SX may be turned on. In this case, a charge in the drain region of the nonvolatile memory cell MC 0 , . . . MC n can be extracted only by turning on the second MOS field effect transistor Q 2S before and after the read and write operations of the nonvolatile memory cell MC 0 , control for extracting the charge is further simplified.

Furthermore, in the above embodiment, charges in the drain regions of the nonvolatile memory cells MC 0 , . . . , MC n are extracted before and after the read and write operations of the selected nonvolatile memory cell MC 0 in the memory block MB 0 . However, the charges in the drain regions of the nonvolatile memory cells MC 0 , . . . , MC n may be extracted before and after an erase operation.

Furthermore, in the above embodiment, the first MOS field effect transistors Q 1S0 , . . . , Q 1SX and the second MOS field effect transistor Q 2S are turned on before and after the read and write operations of the selected nonvolatile memory cell MC 0 in the memory block MB 0 . However, the first MOS field effect transistors Q 1S0 , . . . , Q 1SX and the second MOS field effect transistor Q 2S may be turned on after finishing at least one of the read, write and erase operations of the selected nonvolatile memory cell MC 0 in the memory block MB 0 , . . . , MB X .

Furthermore, in a non-access state of the device, the first MOS field effect transistor Q 1S0 , . . . , Q 1SX and the second MOS field effect transistor Q 2S may be turned on to extract a charge accumulated in the drain region of the nonvolatile memory cell MC 0 , . . . MC n .

Furthermore, the above has merely described a case where the present invention is applied to a flash memory technology, which is a field of the background of the present invention, but the present invention is not limited to this case, and, can be applied to other semiconductor integrated circuit device technology, such as a device in which EEPROM cells and a logic circuit are provided on the same semiconductor substrate. The present invention can be applied at least to a semiconductor integrated circuit device having the memory cell region M with the above-described configuration.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims

1. A semiconductor integrated circuit device comprising:a plurality of memory blocks, each memory block including: a plurality of nonvolatile memory cells arranged in a matrix form, each of the nonvolatile memory cells having a gate region, a source region and a drain region, the memory blocks being arranged in a column direction of the matrix form; word lines, each of which is commonly connected to the gate regions of the nonvolatile memory cells in a corresponding row of the matrix form; a source line commonly connected to the source regions of the nonvolatile memory cells of the corresponding memory block; sub bit lines, each of which is commonly connected to the drain regions of the nonvolatile memory cells in a corresponding column of the matrix form; and first switching elements for selecting the corresponding sub bit lines; main bit lines common to the memory blocks, the sub bit lines in each of the memory blocks being connected to the corresponding main bit lines via the corresponding first switching elements; and at least one second switching element for extracting charges accumulated in drain regions of the nonvolatile memory cells via the first switching elements and the main bit lines, wherein the main bit lines are grounded via the at least one second switching element.

2. The semiconductor integrated circuit device of claim 1, wherein each of the memory cells comprises a floating gate type field effect transistor.

3. The semiconductor integrated circuit device of claim 1, wherein the first switching elements in one of the memory blocks are connected to a common signal line.

4. The semiconductor integrated circuit device of claim 1, wherein each of the first switching elements comprises a MOS field effect transistor, the sub bit lines being connected to the corresponding main bit lines through the corresponding MOS field effect transistors, and the gates of the MOS field effect transistors in one of the memory blocks are commonly connected to a memory block selecting gate line.

5. The semiconductor integrated circuit device of claim 1, wherein one second switching element is provided for each main bit line.

6. A method of controlling a semiconductor integrated circuit device, comprising:providing a semiconductor integrated circuit device comprising: a plurality of memory blocks, each memory block including: a plurality of nonvolatile memory cells arranged in a matrix form, each of the nonvolatile memory cells having a gate region, a source region and a drain region, the memory blocks being arranged in a column direction of the matrix form; word lines, each of which is commonly connected to the gate regions of the nonvolatile memory cells in a corresponding row of the matrix form; a source line commonly connected to the source regions of the nonvolatile memory cells of the corresponding memory block; sub bit lines, each of which is commonly connected to the drain regions of the nonvolatile memory cells in a corresponding column of the matrix form; and first switching elements for selecting the corresponding sub bit lines; main bit lines common to the memory blocks, the sub bit lines in each of the memory blocks being connected to the corresponding main bit lines via the corresponding first switching elements; and at least one second switching element for extracting charges accumulated in drain regions of the nonvolatile memory cells via the first switching elements and the main bit lines; and turning on the first switching elements and the at least one second switching element upon completion of at least one of read, write and erase operations of a selected one of the nonvolatile memory cells in the memory blocks.

7. A method of controlling a semiconductor integrated circuit device, comprising:providing a semiconductor integrated circuit device comprising: a plurality of memory blocks, each memory block including: a plurality of nonvolatile memory cells arranged in a matrix form, each of the nonvolatile memory cells having a gate region, a source region and a drain region, the memory blocks being arranged in a column direction of the matrix form; word lines, each of which is commonly connected to the gate regions of the nonvolatile memory cells in a corresponding row of the matrix form; a source line commonly connected to the source regions of the nonvolatile memory cells of the corresponding memory block; sub bit lines, each of which is commonly connected to the drain regions of the nonvolatile memory cells in a corresponding column of the matrix form; and first switching elements for selecting the corresponding sub bit lines; main bit lines common to the memory blocks, the sub bit lines in each of the memory blocks being connected to the corresponding main bit lines via the corresponding first switching elements; and at least one second switching element for extracting charges accumulated in drain regions of the nonvolatile memory cells via the first switching elements and the main bit lines; and turning on the first switching elements upon completion of each of read, write and erase operations of a selected one of the nonvolatile memory cells in the memory blocks.

8. A method of controlling a semiconductor integrated circuit device, comprising:providing a semiconductor integrated circuit device comprising: a plurality of memory blocks, each memory block including: a plurality of nonvolatile memory cells arranged in a matrix form, each of the nonvolatile memory cells having a gate region, a source region and a drain region, the memory blocks being arranged in a column direction of the matrix form; word lines, each of which is commonly connected to the gate regions of the nonvolatile memory cells in a corresponding row of the matrix form; a source line commonly connected to the source regions of the nonvolatile memory cells of the corresponding memory block; sub bit lines, each of which is commonly connected to the drain regions of the nonvolatile memory cells in a corresponding column of the matrix form; and first switching elements for selecting the corresponding sub bit lines; main bit lines common to the memory blocks, the sub bit lines in each of the memory blocks being connected to the corresponding main bit lines via the corresponding first switching elements; and at least one second switching element for extracting charges accumulated in drain regions of the nonvolatile memory cells via the first switching elements and the main bit lines, turning on the first switching elements and the at least one second switching element in a standby state of the device to thereby extract the charges accumulated in the drain regions of the nonvolatile memory cells.