Claims
- 1. A semiconductor integrated circuit device, comprising:
a memory cell formed on a memory cell forming region of a semiconductor substrate, said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode, a first insulating film formed on the gate electrodes of said first and second n-channel MISFETs and said first and second p-channel MISFETs, a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first n-channel MISFET, a drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, a dielectric film formed on said first conductive film, and a second conductive film formed on said dielectric film and being electrically connected to a drain region of said second n-channel MISFET, a drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET, wherein said second conductive film extends over said first conductive film, and wherein a first capacitor element is comprised of said first conductive film, said dielectric film, and said second conductive film; and a second capacitor element formed on a peripheral circuit forming region of said semiconductor substrate, wherein said second capacitor element is comprised of same level conductive layers as said first conductive film and said second conductive film.
- 2. A semiconductor integrated circuit device according to claim 1, wherein a local wiring line is comprised of said first conductive film.
- 3. A semiconductor integrated circuit device according to claim 1, wherein said second capacitor element is included in an input/output protective circuit.
- 4. A semiconductor integrated circuit device according to claim 1, wherein said memory cell is a memory cell of a static random access memory.
- 5. A semiconductor integrated circuit device according to claim 1, wherein said dielectric film has a thickness less than that of said first conductive film.
- 6. A semiconductor integrated circuit device, comprising:
a memory cell formed on a first region of a semiconductor substrate, said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode, a first insulating film formed on the gate electrodes of said first and second n-channel MISFETs, and said first and second p-channel MISFETs, a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first n-channel MISFET, a drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, a dielectric film formed on said first conductive film, and a second conductive film formed on said dielectric film and being electrically connected to a drain region of said second n-channel MISFET, a drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET, wherein said second conductive film extends over said first conductive film, and wherein a first capacitor element is comprised of said first conductive film, said dielectric film, and said second conductive film; and a second capacitor element formed on a second region of said semiconductor substrate, wherein said second capacitor element is comprised of same level conductive layers as said first conductive film and said second conductive film.
- 7. A semiconductor integrated circuit device according to claim 6, wherein a local wiring line is comprised of said first conductive film.
- 8. A semiconductor integrated circuit device according to claim 6, wherein said second capacitor element is included in an input/output protective circuit.
- 9. A semiconductor integrated circuit device according to claim 6, wherein said second capacitor element is included in a memory cell of a dynamic random access memory.
- 10. A semiconductor integrated circuit device according to claim 6, wherein said memory cell is a memory cell of a static random access memory.
- 11. A semiconductor integrated circuit device according to claim 6, wherein said dielectric film has a thickness less than that of said first conductive film.
Priority Claims (1)
Number |
Date |
Country |
Kind |
7-181513 |
Jul 1995 |
JP |
|
Parent Case Info
[0001] This application is a Divisional application of Ser. No. 09/434,385, filed Nov. 5, 1999, which is a Continuation application of application Ser. No. 09/066,763, filed Apr. 28, 1998, which is a Divisional application of application Ser. No. 08/682,243, filed Jul. 17, 1996.
Divisions (2)
|
Number |
Date |
Country |
Parent |
09434385 |
Nov 1999 |
US |
Child |
09835419 |
Apr 2001 |
US |
Parent |
08682243 |
Jul 1996 |
US |
Child |
09066763 |
Apr 1998 |
US |
Continuations (2)
|
Number |
Date |
Country |
Parent |
09835419 |
Apr 2001 |
US |
Child |
09998628 |
Dec 2001 |
US |
Parent |
09066763 |
Apr 1998 |
US |
Child |
09434385 |
Nov 1999 |
US |