Claims
- 1. A semiconductor integrated circuit device, comprising:a memory cell array having a plurality of memory cells; a memory cell selecting circuit selecting said memory cell according to an internal address signal; a test mode setting circuit activating a test mode signal in accordance with an external instruction; an internal clock generating circuit generating an internal clock signal in response to activation of said test mode signal; and an internal address generating circuit generating said internal address in synchronization with said internal clock signal during an active state of said test mode signal.
- 2. The semiconductor integrated circuit device according to claim 1, further comprising a self refresh mode detector activating a self refresh mode signal in accordance with the external instruction, whereinsaid internal clock generating circuit generating said internal clock signal in response to activation of said self refresh mode signal, and said internal address generating circuit generates said internal address in synchronization with said internal clock signal during an active state of said self refresh mode signal.
Priority Claims (1)
Number |
Date |
Country |
Kind |
7-155015 |
May 1995 |
JP |
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Parent Case Info
This application is a Divisional of application Ser. No. 09/943,011, filed Aug. 31, 2001, now U.S. Pat. No. 6,462,996 which is a Continuation of application Ser. No. 09/624,601 filed Jul. 25, 2000, now U.S. Pat. No. 6,301,166 which is a Divisional of application Ser. No. 08/942,691 filed Sep. 29, 1997, now U.S. Pat. No. 6,122,190 which is a Divisional of application Ser. No. 08/589,358. filed Jan. 22, 1996, now U.S. Pat. No. 5,717,652.
US Referenced Citations (12)
Non-Patent Literature Citations (5)
Entry |
“A Delay Line Loop for Frequency Synthesis of De-Showed Clock” by Walzman, ISSC94, pp. 298-299. |
“A 2.5V Delay-Locked Loop for an 18Mb 500MB/s DRAM” by Lee et al., ISSC94, pp. 300-301. |
“PLL Design for a 500 MB/s Interface” by Holowitz et al., ISSCC93, pp. 160-161. |
“A 55ns 16mb DRAM” by Takeshima et al., ISSCC89, pp. 246-247. |
“A 30ns 64Mb DRAM with Built-in Self-test and Repair Function” by Koike et atl., ISSCC92, pp. 150-151. |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/624601 |
Jul 2000 |
US |
Child |
09/943011 |
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US |