Claims
- 1. A method of manufacturing a semiconductor integrated circuit device having data lines, word lines and memory cells each including a MISFET and a capacitor element, each memory cell being connected to one of the word lines and the data lines, comprising the steps of:(a) forming a gate electrode, a source region and a drain region for said MISFET, on a surface of a semiconductor substrate; (b) forming a first insulating film over said gate electrode; (c) performing a polishing of the surface of said first insulating film; (d) forming a second insulating film over said first insulating film; (e) forming grooves in said second insulating film; and (f) forming a conductive film in said grooves in order to form said data lines, one of said data lines being connnected to one of said source and drain regions of said MISFET.
- 2. A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the steps, between steps (c) and (d), of:(g) performing an etching of said first insulating film in order to form through holes exposing said one of said source and drain regions of said MISFET; and (h) forming second conductor strips in said through holes, wherein said second conductor strips are connected to said one of said data lines.
- 3. A method of manufacturing a semiconductor integrated circuit device having data lines, word lines and memory cells, each memory cell including a MISFET and a capacitor element, and each memory cell being connected to one of the word lines and the data lines, comprising the steps of:(a) forming a gate electrode, a source region and a drain region of said MISFET, on a surface of a semiconductor substrate; (b) forming a first insulating film over said gate electrode; (c) forming a second insulating film over said first insulating film; (d) forming a third insulating film over said second insulating film; (e) performing a polishing of the surface of said third insulating film; (f) forming grooves in said third and second insulating films; (g) forming a conductive film in said grooves and over said third insulating film; and (h) performing a polishing of the surface of said conductive film in order to form said data lines, one of said data lines being electrically connected to one of said source and drain regions of said MISFET.
- 4. A method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein said second insulating film comprises a silicon nitride film and said third insulating film comprises a silicon oxide film.
- 5. A method of manufacturing a semiconductor integrated circuit device according to claim 3, further comprising the steps, between steps (b) and (c), of:(i) performing an etching of said first insulating film in order to form through holes exposing said one of said source and drain regions of said MISFET; and (j) forming second conductor strips in said through holes, wherein said second conductive strips are connected to said one of said data lines.
- 6. A method of manufacturing a semiconductor integrated circuit device having data lines, word lines and memory cells, each memory cell including a MISFET and a capacitor element, and each memory cell being connected to one of the word lines and the data lines, comprising the steps of:(a) forming a gate electrode, a source region and a drain region of said MISFET on a surface of a semiconductor substrate; (b) forming a first insulating film over said gate electrode; (c) performing an etching of said first insulating film in order to form a through hole exposing one of the source and drain regions of said MISFET; (d) forming a first conductive strip in said through hole; (e) forming a second insulating film over said first insulating film; (f) forming grooves in said second insulating film so as to expose the surface of said first conductive strip; (g) forming a second conductive film in said grooves and over said second insulating film; and (h) performing a polishing of the surface of said second conductive film in order to form said data lines, one of said data lines being electrically connected to one of said source and drain regions of said MISFET.
- 7. A method of manufacturing a semiconductor integrated circuit device according to claim 6, further comprising the step, between steps (d) and (e), of:(i) forming a third insulating film over said first conductive strip and said first insulating film, wherein said third insulating film comprises a silicon nitride film and said second insulating film comprises a silicon oxide film.
- 8. A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein said first conductive strip comprises a polysilicon strip and said second conductive film comprises a tungsten film.
- 9. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device also includes a peripheral circuit portion including a second MISFET, and wherein the method includes the further steps of forming a gate electrode and source and drain regions for the second MISFET, on a surface of the semiconductor substrate.
- 10. A method of manufacturing a semiconductor integrated circuit device having a memory cell including a first MISFET, a bit line conductor and a capacitor element, and a peripheral circuit portion including a second MISFET, a first interconnect conductor, and a second interconnect conductor, comprising the steps of:(a) forming a first gate electrode and a first pair of semiconductor regions for the first MISFET, and a second gate electrode and a second pair of semiconductor regions for the second MISFET, on a surface of a semiconductor substrate; (b) forming a first insulating film over said first and second MISFETs; (c) forming a first contact hole over one of the first pair of semiconductor regions, a second contact hole over one of the second pair of semiconductor regions and a third contact hole over the other one of the second pair of semiconductor regions, in the first insulating film; (d) forming a second insulating film over the first insulating film; (e) forming a first groove over the first contact hole, a second groove over the second contact hole and a third groove over the third contact hole, in the second insulating film; (f) forming a conductive film in the first, second and third grooves and on the second insulating film; (g) removing parts of the conductive film formed on the second insulating film in order to form a bit line electrically connected with the one of the first pair of semiconductor regions through the first contact hole, a first interconnect conductor electrically connected with the one of the second pair of semiconductor regions through the second contact hole and a second interconnect conductor electrically connected with the other one of the second pair of semiconductor regions through the third contact hole; and (h) forming a capacitor element electrically connected with the other one of the first pair of semiconductor regions.
- 11. A method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein a chemical mechanical polishing method is applied to remove parts of the conductive film in step (g).
- 12. A method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein removal of the parts of the conductive film in step (g) is achieved by a planarizing method.
Priority Claims (2)
Number |
Date |
Country |
Kind |
8-302821 |
Nov 1996 |
JP |
|
9-283419 |
Oct 1997 |
JP |
|
Parent Case Info
This application is a Continuation application of application Ser. No. 08/968,586, filed Nov. 13, 1997.
US Referenced Citations (6)
Foreign Referenced Citations (1)
Number |
Date |
Country |
7-122654 |
May 1995 |
JP |
Non-Patent Literature Citations (1)
Entry |
Kang, et al., “Highly Manufacturable Process Technology for Reliable 256 Mbit and 1Gbit DRAMS”, IEDM-1994. |
Continuations (1)
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Number |
Date |
Country |
Parent |
08/968586 |
Nov 1997 |
US |
Child |
09/332894 |
|
US |