BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic plan view showing the layout of a semiconductor integrated circuit device of the present invention.
FIG. 2 is a schematic cross-sectional view taken along line A-A of FIG. 1.
FIG. 3 is a schematic plan view of a semiconductor integrated circuit device according to a first example of the present invention.
FIG. 4 is a schematic cross-sectional view taken along line B-B of FIG. 3.
FIG. 5 is a schematic plan view of a semiconductor integrated circuit device according to a second example of the present invention.
FIG. 6 is a schematic cross-sectional view taken along line C-C of FIG. 5.
FIG. 7 is a schematic cross-sectional view taken along line D-D of FIG. 5.
FIG. 8 is a schematic plan view of a semiconductor integrated circuit device according to a third example of the present invention.
FIG. 9 is a schematic cross-sectional view taken along line E-E of FIG. 5.
FIG. 10 is a schematic cross-sectional view taken along line F-F of FIG. 5.
FIG. 11 is a schematic plan view of a semiconductor integrated circuit device according to a fourth example of the present invention.
FIG. 12 is a schematic plan view of a semiconductor integrated circuit device according to a fifth example of the present invention.
FIG. 13 is a schematic plan view for explaining the destruction of a gate insulating film by the antenna effect.
FIG. 14 is a side view showing components shown in FIG. 13.
PREFERRED MODES OF THE DISCLOSURE
A semiconductor integrated circuit device and a method for producing the device, according to the present invention, will now be described with reference to a case of a complementary metal oxide semiconductor (CMOS) including a p type semiconductor substrate and an n-well generated in the substrate.
Referring first to FIGS. 1 and 2, an example of layout of a semiconductor integrated circuit device according to the present invention is now described. FIG. 1 depicts a schematic plan view showing a layout in a semiconductor integrated circuit device 1, and FIG. 2 depicts a schematic cross-sectional view along line A-A of FIG. 1. Meanwhile, in the plan view of the present invention, a silicon oxide film is omitted from the drawing for clarifying the area of e.g., a diffusion region. The semiconductor integrated circuit device 1 includes a p type semiconductor substrate 2, as a semiconductor region, and an n-well 3, as a semiconductor region formed in the p type semiconductor substrate 2. In the p type semiconductor substrate 2 and in the n-well 3, there are formed a body contact or substrate contact 4 and a well contact 6, as diffusion regions, respectively. These contacts 4, 6 are generally U-shaped and are formed extending along the rim of a basic circuit cell, not shown in detail. In the configuration shown in FIG. 1, there are formed diffusion regions 5 between the body contact 4 and the n-well 3, so that the diffusion regions 5 are isolated, that is, made independent from, the body contact 4 from the outset. There are also formed diffusion regions 7 between the well contact 6 and the p type semiconductor substrate 2, so that the diffusion regions 7 are isolated, that is, made independent from, the well contact 6 from the outset. According to the present invention, the diffusion regions 5 and 7 are used as a body contact or as a well contact, respectively, in case the antenna effect averting action is not needed. The diffusion regions 5 and 7 are used as a discharge path in case the antenna effect averting action is needed. Preferred examples of the present invention are now described in detail.
The semiconductor integrated circuit device according to a first example of the present invention is now described. In a layout of the semiconductor integrated circuit device 1 of the first example, shown in FIGS. 1 and 2, no antenna effect averting action is taken, that is, the diffusion regions 5 and 7 are used as a body contact and as a well contact, respectively. FIG. 3 depicts a schematic plan view of a semiconductor integrated circuit device of the first example, and FIG. 4 depicts a schematic cross-sectional view taken along line B-B of FIG. 3.
In the semiconductor integrated circuit device 1, a MOS field effect transistor (FET) is formed in the p type semiconductor substrate 2. The MOSFET includes a gate electrode 11, a source 12, a drain 13 and a gate insulating film, not shown in FIG. 3. To the gate electrode 11, there is connected a third wiring layer 14 via a contact, not shown. The diffusion regions 5 are diffusion regions of the p type which is the same conductivity type as that of the body contact 4, and are labeled 4a. The body contact 4 and each first conductivity type diffusion region 4a are electrically connected to each other via a first contact 15 and a first wiring (interconnect) layer 9, and hence the first conductivity type diffusion region 4a may operate as a body contact. Similarly, the second conductivity type diffusion regions 7 are diffusion regions of an n type, which is the same conductivity type as that of the well contact 6, and are labeled 6a. The well contact 6 and each second conductivity type diffusion region 6a are electrically connected to each other via a second contact 16 and a second wiring layer 10, and hence the second conductivity type diffusion region 6a may operate as a well contact.
In the first example, the case in which the MOSFET is in a p type semiconductor substrate 2 has been described. However, the above applies for a case in which the MOSFET is in an n type semiconductor substrate 3.
A semiconductor integrated circuit device according to a second example of the present invention and the method for fabrication of the same will now be described. In the first example, the semiconductor integrated circuit device is of the form in which an antenna effect averting action is not required. Stated differently, the semiconductor integrated circuit device is shown in a form prior to applying the antenna effect averting action. In the second example, the semiconductor integrated circuit device is of the form in which the antenna effect averting action has been taken, that is, the device is shown in the form in which the diffusion regions 5 are used as a discharge path. FIG. 5 depicts a schematic plan view showing a semiconductor integrated circuit device according to the second example of the present invention. FIGS. 6 and 7 depict schematic cross-sectional views taken along lines C-C and D-D of FIG. 5, respectively.
The semiconductor integrated circuit device, shown in FIGS. 3 and 4, is already fabricated, that is, respective components of the device are formed and the wiring (or interconnection) of respective wiring layers is finished. It is then checked whether or not there is possibility of the antenna effect taking place in connection with e.g., the third wiring layer 14. If it is recognized to be necessary to take an antenna effect preventive action, such action is taken for e.g., the third wiring layer 14. A decision as to whether or not it is necessary to take the antenna effect preventive action may be given based on a desired standard or reference.
It is assumed that it has become necessary to take the antenna effect preventive action for a wiring layer connected to the gate electrode 11, for example, the third wiring layer 14 or the fourth wiring layer 17. In this case, the first wiring layer 9 and the first contact 15, connected to the first conductivity type diffusion region 4a (the region corresponding to the diffusion region 5 shown in FIGS. 1 and 2) are removed. The region corresponding to the diffusion region 5 is now changed from the p type diffusion region 4a to an n type diffusion region 18, such as an ion injection layer. This generates a pn junction provided by the n type diffusion region 18 and the p type semiconductor region 2. The fourth wiring layer 17, formed on top of the third wiring layer 14, and the n type diffusion region 18, are interconnect by a contact 22. The fourth wiring layer 17 and the third wiring layer 14 are interconnected via a via 21. This electrically connects the n type diffusion region 18 to the third wiring layer 14 which is in need of the antenna effect preventive action.
If, in this configuration, the electrical charges stored in the wiring (interconnect) layers connected to the gate electrode 11, for example, the third wiring layer 14 and the fourth wiring layer 17, exceed the reverse voltage provided by the pn junction of the n type diffusion region 18 and the p type semiconductor region 2, the charges are discharged to the semiconductor region of the first conductivity type 2. The reverse voltage is the forward bias of the pn junction and hence is sufficiently smaller than the voltage which might destruct a gate insulating film 19. Hence, the region corresponding to the diffusion region 5 may be in operation as a discharge path.
Thus, in the semiconductor integrated circuit device and the method for fabrication thereof, according to the second example, part of the body contact may be used as a discharge path, whereby the antenna effect may be prevented from being generated without the necessity of newly securing a region for a discharge path without forming a by-pass wiring.
A semiconductor integrated circuit device and a method for fabrication thereof, according to a third example of the present invention, will now be described. In the second example, the antenna effect preventive action needs to be taken for the wiring layer connected to the MOSFET formed in the p type semiconductor substrate 2. In the present third example, the antenna effect preventive action needs to be taken for the wiring layer connected to the MOSFET formed in the n-well 3. FIG. 8 depicts a schematic plan view of a semiconductor integrated circuit device according to the third example. FIGS. 9 and 10 depict cross-sectional views taken along lines E-E and F-F in FIG. 8, respectively.
Initially, such a semiconductor integrated circuit device is fabricated, in which a MOSFET is formed in the n-well 3, and in which the diffusion region 7 is used as part of the well contact (n type diffusion layer 6a), as shown in FIGS. 3 and 4. If it is verified that an action needs to be taken for averting the antenna effect, the second wiring layer 10 and the second contact 16, so far connected to the n type diffusion region 6a, are removed. The portion of the n-well 3, overlying or surrounding the n type diffusion region 6a, is then scraped off and replaced by a p type diffusion region 23 (e.g., an ion injection layer). The n type diffusion layer 6a and the fourth wiring layer 17 are then interconnected by a contact 22, as in the second example. The third wiring layer 14 and the fourth wiring layer 17 are interconnected by a via 21. By so doing, a pn junction is generated by the n type diffusion region 6a and the p type diffusion region 23 so that the n type diffusion region 6a may be used as a discharge path for electrical charges stored in the wiring layer.
Thus, with the second and third examples, part of the body contact or the well-contact may be used as a discharge path for averting the antenna effect, no matter whether the wiring in need of the antenna effect preventive action is in a p type semiconductor region or in an n type semiconductor region.
In the second and third examples, a semiconductor integrated circuit device is used in which the diffusion layers 5 and 7 are isolated from the outset from the body contact 4 and from the well-contact 6, respectively, as shown in FIG. 1. It is however possible to form the diffusion regions 18, 23, operating as discharge paths, from a unitary or non-interrupted structure made up of diffusion regions 5, 7, the body contact 4 and the well-contact 6.
A semiconductor integrated circuit device and a method for fabrication thereof, according to a fourth example of the present invention, will now be described. It is noted that the basic structure of the second and third examples is a unitary basic circuit cell, while that of the fourth example is a parallel array of a plural number of basic circuit cells. FIG. 11 depicts a schematic plan view of a semiconductor integrated circuit device according to the fourth example of the present invention.
A semiconductor integrated circuit device shown in FIG. 11 is composed of two basic circuit cells of the same profile arrayed vertically in the drawing. On the rim of each basic circuit cell, there are formed a body contact 4 and a well contact 6 in a lattice configuration. A body contact 4c and a well contact 6c, provided at a mid portion between the two basic circuit cells, are shared by the two basic circuit cells. As in the first to third examples, a diffusion region, formed in isolation from the body contact 4, is formed between the body contact 4 and the n-well 3, while another diffusion region, formed in isolation from the well contact 6, is formed between the well contact 6 and a p type semiconductor substrate 2. As in the second example, a MOSFET is formed on the p type semiconductor substrate 2, while a third wiring layer 14 and so forth are connected to a gate electrode 11. In case the wiring layer connected to the gate electrode 11 is in need of an action against the antenna effect, an isolated diffusion region, neighboring to the body contact 4c, is replaced by an n type diffusion layer 18, as in the second example. A fourth wiring layer 17 and the n type diffusion region 18 are electrically connected to each other. This allows electrical charges stored in the wiring layers 14, 17 to be discharged via n type diffusion layer 18. In the configuration shown in FIG. 11, the diffusion regions 4a, separated from the body contacts 4b, 4d, are electrically connected to the first wiring layer 9 to act a part of the body contact 4.
A semiconductor integrated circuit device, and a method for fabrication thereof, according to a fifth example of the present invention, will now be described. In the fourth example, the wiring layer connected to the MOSFET formed in the p type semiconductor substrate 2 is in need of an action against the antenna effect. In the present fifth example, the wiring layer connected to the MOSFET formed in the n-well 3 is in need of an action against the antenna effect. FIG. 12 depicts a schematic plan view of the semiconductor integrated circuit device according to the fifth example.
The semiconductor integrated circuit device, shown in FIG. 12, has the configuration similar to that of the device of the fourth example shown in FIG. 11. However, a MOSFET is formed in an n-well 3. In case an action against the antenna effect is needed, the portion of the n-well 3 surrounding the diffusion region 6a, neighboring to the well contact 6c, is replaced by a p type diffusion region 23, which p type diffusion region 23 is then electrically connected to a fourth wiring layer 17. This allows electrical charges, stored in the wiring layers 14, 17, to be discharged via diffusion region 6a and p type diffusion region 23. Meanwhile, the isolated diffusion regions 6a, neighboring to the well contacts 6b, 6d, are electrically connected to second wiring layers 10 to operate as part of the well contact 6.
With the fourth and fifth examples, part of the region of the body contact or well contact, shared by plural basic circuit cells, may be utilized as a discharge path for averting the antenna effect.
The above-described examples of the semiconductor integrated circuit device are merely illustrative of the present invention. It is to be appreciated that those skilled in the art can change or modify the examples without departing from the scope and spirit of the invention.
It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith.
Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items may fall under the modifications aforementioned.
Patent Application
20070262350
