1. Field of the Invention
The present invention relates to an analog semiconductor device having a sensor or power management function.
2. Description of the Related Art
When an analog semiconductor integrated circuit device having a sensor or power management function is constructed from MOS transistors, a plurality of threshold voltage (hereinafter, referred to as “Vth”) of MOS transistors is generally used instead of a single Vth to meet such a need as to deal with complicated analog signal processing or various input voltage levels. So-called multi-Vth technique is used.
In a conventional semiconductor integrated circuit device as shown in
Since the conventional method requires repeating steps of photolithography and ion implantation several times for attaining the multiple Vth as shown above, there arises a problem in terms of a longer manufacturing period, which affects product delivery, and a higher manufacturing cost.
The present invention adopts the following means in order to solve the aforementioned problem.
(1) A semiconductor integrated circuit device, comprising: a first MOS transistor in which wiring metal connected to a source of the MOS transistor overlaps a gate electrode of the MOS transistor on a side of the source; and a second MOS transistor in which wiring metal connected to a source does not overlap a gate electrode on a side of the source.
(2) The semiconductor integrated circuit device according to (1), in which a ratio of an overlap amount in which the wiring metal overlaps the gate electrode in the first MOS transistor to a channel width is a predetermined value of 0 or larger and 1 or smaller.
(3) The semiconductor integrated circuit device according to (1), in which an overlap amount in which the wiring metal overlaps the gate electrode in the first MOS transistor is 0.2 μm or more.
According to the present invention, a multi-Vth integrated circuit can be attained without increasing the number of steps, and quick product delivery, which is comparable with that of a product available with a non-multi-Vth technique, is possible.
In the accompanying drawings:
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
Here, the first MOS transistor differs from the second MOS transistor in terms of patterns of the source wiring metals 107 and 108. In an ordinary layout, the source wiring metal does not overlap the gate electrode as in the second MOS transistor. When the source wiring metal overlaps the gate electrode, the Vth increases in an NMOS transistor and decreases in a PMOS transistor, which means that an absolute value of the Vth increase in both the MOS transistors.
In general, the MOS transistor has an interface state at an interface between a semiconductor substrate and a gate insulating film. The interface state density is high in a region where the gate electrode overlaps the source/drain. Since the interface state are terminated by hydrogen atom diffusing into the insulating film and reaching the interface between the semiconductor substrate and the gate insulating film at the time of sintering in an atmosphere containing hydrogen that promotes an alloying reaction between the wiring metal and the semiconductor, or formation of a protective film containing hydrogen such as a plasma nitride film, the interface state density lowers.
When the source/drain wiring metals are laid out to overlap the gate electrode, the wiring metal suppresses the hydrogen diffusion. Thus, in a MOS transistor having such a layout, the interface state density is not reduced, and an absolute value of the Vth becomes large.
The present invention makes use of this phenomenon. In
If the drain wiring metal overlaps the gate electrode, the same effect is obtained. In the case of operating the MOS transistor in a saturated mode, an increase of the Vth is small, and thus it is more effective to form the source wiring metal to overlap the gate electrode. Note that effects of the present invention can be expected under such a condition that the overlap width in which the wiring metal overlaps the gate electrode is 0.2 μm or more.
As has been described so far, according to the present invention, the multi-Vth integrated circuit can be attained without increasing a cost nor prolonging a manufacturing period. Consequently, it is possible to provide the high-value added analog semiconductor integrated circuit device with high performance.
Number | Date | Country | Kind |
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2004-053727 | Feb 2004 | JP | national |