The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2022-0060409 filed on May 17, 2022, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein.
Various embodiments of the present invention relate generally to a semiconductor memory device and a method of manufacturing the semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the three-dimensional semiconductor memory device.
In general, a non-volatile memory device can electrically erase and program data and retain the data even in the absence of a power supply. Recently, the use of non-volatile memory devices has been surging in a variety of fields.
Non-volatile memory devices include memory cell transistors in various forms and are classified into NAND type and NOR type memory devices according to their cell array structures. Both NAND and NOR type non-volatile memory devices have their own advantages and disadvantages.
More particularly, a NAND type non-volatile memory device has an advantage in that it offers high integration since it has a cell string structure in which a plurality of memory cell transistors are coupled in series with each other. In addition, a NAND type non-volatile memory device adopts an operating method by which information stored in a plurality of memory cell transistors is changed at the same time. Therefore, an information update speed of the NAND type non-volatile memory device is remarkably faster than that of the NOR type non-volatile memory device. NAND type non-volatile memory devices with high integration and fast update speed as above are used mainly in portable electronic products requiring mass storage, such as digital cameras or MP3 players. Research and development is being conducted to promote and highlight the advantages of NAND type non-volatile memory devices. Accordingly, three-dimensionally structured NAND non-volatile memory devices have been developed.
Various embodiments of the present disclosure are directed to a semiconductor memory device capable of simplifying processes.
According to an embodiment, a semiconductor memory device may include a semiconductor substrate including a memory cell region and contact regions, a first stacked structure on the semiconductor substrate, a second stacked structure disposed between the semiconductor substrate and the first stacked structure, a plurality of cell plugs extending in a vertical direction crossing a top surface of the semiconductor substrate and arranged between the first stacked structure and the second stacked structure in the memory cell region, and a plurality of supports extending in the vertical direction and arranged on the first stacked structure in the contact region, wherein the second stacked structure is arranged in a different level from the plurality of supports.
According to an embodiment, a semiconductor memory device may include a semiconductor substrate including a peripheral circuit structure, a first stacked structure including a plurality of first interlayer insulating layers and a plurality of first conductive layers stacked alternately with each other in a vertical direction crossing a top surface of the semiconductor substrate, a second stacked structure arranged between the first stacked structure and the semiconductor substrate and including a plurality of second interlayer insulating layers and a plurality of second conductive layers stacked alternately with each other in the vertical direction, a cell plug arranged in the first stacked structure and the second stacked structure, a first support arranged on the first stacked structure and having a smaller length than the cell plug in the vertical direction, and a connection structure arranged between the second stacked structure and the peripheral circuit structure.
Specific structural or functional descriptions of examples of embodiments in accordance with concepts which are disclosed in this specification are illustrated only to describe the examples of embodiments in accordance with the concepts and the examples of embodiments in accordance with the concepts may be carried out by various forms but the descriptions are not limited to the examples of embodiments described in this specification.
While terms such as “first” and “second” may be used to describe various components, such components must not be understood as being limited to the above terms. The above terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of rights of the present disclosure, and likewise a second component may be referred to as a first component.
Referring to
The substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth method.
The peripheral circuit structure PC may include a row decoder, a column decoder, a page buffer, and a control circuit which constitute a circuit for controlling operations of the memory blocks BLK1 to BLKk. For example, the peripheral circuit structure PC may include an NMOS transistor, a PMOS transistor, a resistor, and a capacitor which are electrically coupled to the memory blocks BLK1 to BLKk. The peripheral circuit structure PC may be arranged between the substrate SUB and the memory blocks BLK1 to BLKk.
Each of the memory blocks BLK1 to BLKk may include a source structure, bit lines, cell strings which are electrically coupled to the source structure and the bit lines, word lines which are electrically coupled to the cell strings, and select lines which are electrically coupled to the cell strings. Each of the cell strings may include memory cells and select transistors which are coupled in series with each other by a channel structure. Each of the select lines may serve as a gate electrode of a corresponding one of the select transistors. Each of the word lines may serve as a gate electrode of a corresponding one of the memory cells.
According to another embodiment, the substrate SUB, the peripheral circuit structure PC, and the memory blocks BLK1 to BLKk may be stacked in reverse order to the order shown in
Referring to
The substrate 10 may be configured in the same manner as described above with reference to
The second connection structures C2 and a second insulation layer structure 12 may be arranged on the substrate 10. Each of the second connection structures C2 may include a plurality of conductive layers 61, 63, 65, 67, 69, 71, 73, and 75. The second insulation layer structure 12 may cover the transistors TR. The second connection structures C2 may be disposed in the second insulation layer structure 12. The second insulation layer structure 12 may include one insulating layer as shown in the example of
The first connection structures C1 and a first insulation layer structure 35 may be arranged on the second insulation layer structure 12. Each of the first connection structures C1 may include a plurality of conductive layers 43 and 45. The first insulation layer structure 35 may cover the second insulation layer structure 12. The first connection structures C1 may be disposed in the first insulation layer structure 35. The first insulation layer structure 35 may include one insulating layer as shown in the example of
Each of the plurality of conductive layers 43 and 45 which constitute the first connection structures C1 may include a first bonding metal 45. Each of the plurality of conductive layers 61, 63, 65, 67, 69, 71, 73, and 75 which form the second connection structures C2 may include a second bonding metal 75. The first bonding metal 45 and the second bonding metal 75 may be bonded to each other.
The wiring array 41 may be disposed in the first insulating structure 35 and overlap the first connection structures C1. The gate stack structure GST may overlap the wiring array 41 with at least one insulating layer interposed therebetween. According to an embodiment, an upper insulating layer 31 may be arranged between the gate stack structure GST and the wiring array 41.
The gate stack structure GST may be arranged between the wiring array 41 and a source layer 81. The gate stack structure GST may include a plurality of interlayer insulating layers ILD1 and ILD2 and a plurality of conductive layers CP1 and CP2. The plurality of interlayer insulating layers ILD1 and ILD2 and the plurality of conductive layers CP1 and CP2 may be stacked alternately with each other in a vertical direction Y crossing a top surface of the substrate 10. The gate stack structure GST may include at least two stacked structures which are stacked in the vertical direction Y. According to an embodiment, the gate stack structure GST may include a first stacked structure GST1 and a second stacked structure GST2 which are stacked in the vertical direction Y. The plurality of interlayer insulating layers ILD1 and ILD2 may be divided into a plurality of first interlayer insulating layers ILD1 which form the first stacked structure GST1 and a plurality of second interlayer insulating layers ILD2 which form the second stacked structure GST2. The plurality of conductive layers CP1 and CP2 may be divided into a plurality of first conductive layers CP1 which form the first stacked structure GST1 and a plurality of second conductive layers CP2 which form the second stacked structure GST2.
Among the plurality of conductive layers CP1 and CP2, at least one conductive layer may serve as a source select line, at least one conductive layer may serve as a drain select line, and the other conductive layers between the drain select line and the source select line may serve as word lines. According to an embodiment, the second conductive layer CP2 which is adjacent to the wiring array 41 as shown in
The plurality of interlayer insulating layers ILD1 and ILD2 and the plurality of conductive layers CP1 and CP2 may extend in a first direction X and a second direction Z on a plane which crosses the vertical direction Y. A line which extends in the first direction X and a line which extends in the second direction Z may cross each other. According to an embodiment, the line which extends in the first direction X and the line which extends in the second direction Z may be orthogonal to each other. The plurality of interlayer insulating layers ILD1 and ILD2 and the plurality of conductive layers CP1 and CP2 may be arranged in the memory cell region Ra of the substrate 10 and may extend to the contact region Rb of the substrate 10. A portion of the gate stack structure GST in the contact region Rb may be covered by an insulating layer 83.
Referring to
The channel structures CH may be coupled to the wiring array 41 through upper contacts 27. The upper contacts 27 may pass through the upper insulating layer 31. The number and shape of the upper insulating layer 31 and the upper contacts 27 between the wiring array 41 and the second stacked structure GST2 may not be limited to those shown in
Though not shown in
A vertical insulator VI may be arranged between cell plugs CPL. The gate stack structure GST may be divided by the vertical insulator VI.
Referring to
The conductive contact 25 may extend from the end of the conductive layer corresponding thereto toward the wiring array 41. The stepped structure formed by the plurality of interlayer insulating layers ILD1 and ILD2 and the plurality of conductive layers CP1 and CP2 may be covered by a gap-filling insulating layer 21. The upper insulating layer 31 may extend to overlap the gap-filling insulating layer 21. Some of the insulating layers included in the second insulation layer structure 12 may extend between the wiring array 41 and the upper insulating layer 31. The conductive contact 25 may extend in the vertical direction Y to pass through the gap-filling insulating layer 21 and the upper insulating layer 31. The conductive contact 25 may be coupled to the wiring array 41 through a contact plug 33. The contact plug 33 may be arranged in the second insulation layer structure 12 between the wiring array 41 and the contact plug 25. The wiring array 41 may include connecting wires which are coupled to the conductive contact 25.
Each of the plurality of conductive layers CP1 and CP2 may be connected to the transistor TR corresponding thereto through the conductive contact 25, the contact plug 33, the connecting wires of the wiring array 41, the first connection structure C1 and the second connection structure C2.
Referring to
The plurality of interlayer insulating layers ILD1 and ILD2 and the plurality of conductive layers CP1 and CP2 in the contact region Rb may be penetrated by a plurality of supports SP1 and SP2. The plurality of supports SP1 and SP2 may include a plurality of first supports SP1 and a plurality of second supports SP2.
The plurality of first supports SP1 may pass through some of the plurality of interlayer insulating layers ILD1 and ILD2 and the plurality of conductive layers CP1 and CP2 which are adjacent to the source layer 81 and the insulating layer 83, so that the plurality of first supports SP1 may have a smaller length than the cell plug CPL. According to an embodiment, the plurality of first supports SP1 may pass through the first interlayer insulating layer ILD1 and the first conductive layer CP1 of the first stacked structure GST1. The second stacked structure GST2 may be arranged between the first stacked structure GST1 and the wiring array 41 and open an end portion of the first stacked structure GST1. The plurality of first supports SP1 may pass through the end portion of the first stacked structure GST1 which is opened by the second stacked structure GST2. In other words, the second stacked structure GST2 may be provided to open an area between the plurality of first supports SP1 and the substrate 10 and may be arranged at a different level from a level of the plurality of first supports SP1.
The plurality of second supports SP2 may pass through the stacks of the gate stack structure GST. According to an embodiment, the plurality of second supports SP2 may pass through the first stacked structure GST1 and the second stacked structure GST2. At least one of the plurality of second supports SP2 may include a portion which passes through the gap-filling insulating layer 21. The second supports SP2 may have the same structure and material as the cell plug CPL. According to an embodiment, each of the second supports SP2 may include a support channel structure CH′ and a support memory layer ML′. The support channel structure CH′ may include the same material as the channel structure CH of the cell plug CPL. The support channel structure ML′ may include the same material layers as those of the memory layer ML of the cell plug CPL and surround the support channel structure CH′. Each of the support memory layer ML′ and the memory layer ML may include a tunnel isolation layer, a data storage layer, and a blocking insulating layer.
The first support SP1 may have a smaller length than the second support SP2. The first support SP1 may have a different structure from the second support SP2. Hereinafter, the first support SP1 will be described in more details with reference to
Referring to
Referring to
Referring to
The first substrate 100 may include a material with a different etch rate from the first and second material layers 111 and 113. For example, the first substrate 100 may include silicon.
The second material layers 113 may include a different material from the first material layers 111. According to an embodiment, the first material layers 111 may include an insulating material for interlayer insulating layers ILD as described above with reference to
The first material layers 111 and the second material layers 113 may extend from the memory cell region Ra to the contact region Rb. The first material layers 111 and the second material layers 113 may extend to different lengths on the side so as to form a steppe structure in the contact region Rb. The stepped structure of the first preliminary stacked structure 110 may be referred to as a first stepped portion. An end portion of the second material layer 113 exposed by the first stepped portion may be referred to as a first pad region PAD1.
Operation S1A may include forming a first gap-filling insulating layer 115 on the first stepped portion of the first preliminary stacked structure 110. The first gap-filling insulating layer 115 may cover the first pad region PAD1 exposed through the first stepped portion.
Operation S1A may include forming a first trench T1, first holes H1, second holes H2, and third holes H3 which pass through the first gap-filling insulating layer 115 and the first preliminary stacked structure 110. The first trench T1 may pass through the first preliminary stacked structure 110 in the memory cell region Ra. The first holes H1 may pass through the first preliminary stacked structure 110 in the memory cell region Ra and be arranged at both sides of the first trench T1. The second holes H2 and the third holes H3 may pass through the first preliminary stacked structure 110 in the contact region Rb. Each of the second holes H2 may pass through the first gap-filling insulating layer 115 which overlaps the first pad region PAD1, and may pass through at least one first material layer 111 and at least one second material layer 113 under the first pad region PAD1. Each of the third holes H3 may be arranged between the first pad region PAD1 and the memory cell region Ra.
Thereafter, the first trench T1, the first holes H1, the second holes H2, and the third holes H3 may be filled with a material to form the lower supports 230, respectively. The material for the lower supports 230 may have an etch selectivity with respect to the first material layers 111 and the second material layers 113. For example, the material for the lower support 230 may include a semiconductor material. In a specific embodiment, the material for the lower support 230 may include polysilicon. However, embodiments of the present disclosure are not limited thereto.
Referring to
The third material layers 211 of the second preliminary stacked structure 210 may include the same material as the first material layers 111. The fourth material layers 213 of the second preliminary stacked structure 210 may include the same material as the second material layers 113 of the first preliminary stacked structure 110.
The third material layers 211 and the fourth material layers 213 may extend from the memory cell region Ra to the contact region Rb. The third material layers 211 and the fourth material layers 213 may laterally extend to different lengths so as to form a stepped structure in the contact region Rb. The stepped structure of the second preliminary stacked structure 210 may be defined as a second stepped portion. The end portion of the fourth material layer 213 exposed by the second stepped portion may be defined as a second pad region PAD2. The second pad region PAD2 may overlap the lower support 230 in the third hole H3.
Operation S1A may include forming a second gap-filling insulating layer 215 on the second stepped portion of the second preliminary stacked structure 210. The second gap-filling insulating layer 215 may cover the second pad region PAD2 exposed through the second stepped portion and extend to the first gap-filling insulating layer 115.
Operation S1A may include forming fourth holes H4 and fifth holes H5 which pass through the second gap-filling insulating layer 215 and the second preliminary stacked structure 210. The fourth holes H4 may pass through the second preliminary stacked structure 210 in the memory cell region Ra and expose the lower supports 230 in the first holes H1. The fifth holes H5 may pass through the second preliminary stacked structure 210 in the contact region Rb. Each of the fifth holes H5 may pass through the second gap-filling insulating layer 215 which overlaps the second pad region PAD2 and may pass through at least one third material layer 211 and at least one fourth material layer 213 under the second pad region PAD2. The fifth holes H5 may expose the lower supports 230 in the third holes H3, respectively.
A portion of each of the fourth holes H4 and the fifth holes H5 may pass through the second preliminary stacked structure 210. Therefore, when the fourth holes H4 and the fifth holes H5 are etched, a difference in etch speed may be reduced as compared with a case in which a hole passing through the second preliminary stacked structure 210 and a hole passing through only the second gap-filling insulating layer 215 are formed at the same time. When the fourth holes H4 and the fifth holes H5 are etched, by ruling out a process of forming the hole which passes through only the second gap-filling insulating layer 215, the lower support 230 may remain in the second hole H2 with the second gap-filling insulating layer 215 covering the lower support 230.
Referring to
The lower support 230 in the memory cell region Ra may remain as a sacrificial pattern 230A while the lower support 230 fills the first trench T1, and may be covered by the second preliminary stacked structure 210. In addition, the lower support 230 in the contact region Rb may remain as a first support 230B while the lower support 230 fills the second hole H2, and may be covered by the second gap-filling insulating layer 215.
Referring to
The second support 250B may extend in a vertical direction in which the second support 250B crosses a top surface of the first substrate 100 so as to be longer than the first support 230B. According to an embodiment, the first support 230B may have a length equal to the distance between the interface between the first gap-filling insulating layer 115 and the second gap-filling insulating layer 215 and the first substrate 100 in the vertical direction, and the second support 250B may have a greater length than the first support 230B by a height of the second preliminary stacked structure 210 in the vertical direction.
Referring to
Referring to
Portions of the first supports 230B may be exposed by the first openings 281A, respectively.
The exposed portions of the first supports 230B may be oxidized by an oxidation process. In this manner, insulation portions 230IP may be formed in the first supports 230B, respectively.
Referring to
According to the above-described embodiments, the cell plugs 250A and the second supports 250B may pass through the first stacked structure 110′ and the second stacked structure 210′. The first supports 230B may pass through the first stacked structure 110′ and be insulated from the conductive layers 123 of the first stacked structure 110′ by the insulation portions 230IP.
According to another embodiment, the cell plugs 250A, the first supports 230B, and the second supports 250B may extend into the first substrate 100.
Referring to
Contact holes 311H may be formed to expose a first pad region PAD1 and a second pad region PAD2 of the first stacked structure 110′ in the contact region Rb. The first pad region PAD1 may be defined as an end portion of the conductive layer 123 which is exposed through a first stepped portion of the first stacked structure 110′. The second pad region PAD2 may be defined as an end portion of the conductive layer 223 which is exposed by a second stepped portion of the second stacked structure 210′.
The contact holes 311H may pass through the upper insulating layer 310 and at least one of the first gap-filling insulating layer 115 and the second gap-filling insulating layer 215.
Referring to
In the memory cell region Ra, upper contacts 313 may pass through the upper insulating layer 310. The upper contacts 313 may be connected to the cell plugs 250A.
Referring to
The contact plugs 321 may contact the upper contacts 313.
The wiring array 323 may include a bit line which is connected to the cell plug 250A through some of the contact plugs 321 and some of the upper contacts 313. The wiring array 323 may include a connecting wire which is connected to the conductive contact 311 through some of the contact plugs 321 and some of the upper contacts 313.
Each of the first connection structures 329 may include a plurality of conductive layers 325 and 327. The first insulation layer structure 335 and the first connection structures 329 may not be limited to the example as shown in the drawings but may vary. Some of the first connection structures 329 may be connected to the conductive contact 311. Other first connection structures 329 may be connected to the cell plug 250A of the memory cell array. The conductive layers 325 and 327 included in each of the first connection structures 329 may include a first bonding metal 327 which has a surface exposed to the outside of the first insulation layer structure 335.
Referring to
Each of the transistors 410 may be formed in an active region of the second substrate 400 divided by an isolation layer 403. Each of the transistors 410 may include a gate insulating layer 407 and a gate electrode 409 stacked on each other in the active region corresponding thereto, and junctions 405a and 405b formed in the active region at both sides of the gate electrode 409. The junctions 405a and 405b may include dopants for forming transistors corresponding thereto. The junctions 405a and 405b may include at least one of an n type dopant and a p type dopant.
At operation S2A as shown in
The second insulation layer structure 411 may include two or more insulating layers. Each of the second connection structures 429 may include a plurality of conductive layers 413, 415, 417, 419, 421, 423, 425, and 427. The second insulation layer structure 411 and the second connection structures 429 may not be limited to the example as shown in
Referring to
The first bonding metal 327 and the second bonding metal 427 may include various metals including copper.
Operation S3 may include bonding the first bonding metal 327 and the second bonding metal 427 to each other. For example, after heat is applied to the first bonding metal 327 and the second bonding metal 427, the first bonding metal 327 and the second bonding metal 427 may be hardened. However, the present disclosure is not limited thereto. Various processes may be performed to connect the first bonding metal 327 and the second bonding metal 427 to each other.
Referring to
Subsequently, at operation S7, a source layer 511 may be formed. The source layer 511 may contact the channel structure 253A of the cell plug 250A. The source layer 511 may be removed from the contact region Rb to expose the first support 230B and the second support 250B. The region from which the source layer 511 is removed may be filled with an insulating layer 513. The source layer 511 may include a doped semiconductor layer which includes at least one of an n type dopant and a p type dopant.
Referring to
The memory device 1120 may be a multi-chip package which includes a plurality of flash memory chips.
The memory controller 1110 may be configured to control the memory device 1120, and may include static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may serve as operation memory of the CPU 1112. The CPU 1112 may perform an overall control operation for data exchange of the memory controller 1110. The host interface 1113 may include a data exchange protocol of a host connected to the memory system 1100. In addition, the error correction block 1114 may detect and correct an error included in data read from the memory device 1120. The memory interface 1115 may perform interfacing with the memory device 1120. In addition, the memory controller 1110 may further include read only memory (ROM) that stores code data for interfacing with the host.
The memory system 1100 may be a memory card or a solid state drive (SSD) into which the memory device 1120 and the memory controller 1110 are integrated. For example, when the memory system 1100 serves as the SSD, the memory controller 1110 may communicate with an external device (e.g., a host) through one of the interface protocols including Universal Serial Bus (USB), MultiMedia Card (MMC), Peripheral Component Interconnection-Express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and integrated Drive Electronics (IDE).
Referring to
The memory system 1210 may include a memory device 1212 and a memory controller 1211.
The memory controller 1211 may be configured in the same manner as the memory controller 1110 as described above with reference to
According to the present disclosure, processes may be simplified by forming cell plugs and supports at the same time without performing a separate process for forming the supports in a plurality of stacked structures.
Number | Date | Country | Kind |
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10-2022-0060409 | May 2022 | KR | national |