SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

The disclosure concerns a semiconductor memory device including an insulating film; a semiconductor layer provided on the insulating film; a source layer and a drain layer formed on the semiconductor layer; a body region provided between the source layer and the drain layer, the body region being in an electrically floating state, accumulating or emitting charges for storing data, and including a first body part and a second body part, the first body part being smaller than the second body part in a thickness measured in a direction perpendicular to a surface of the insulating film; a gate insulating film provided on the first body part and the second body part; and a gate electrode provided on the gate insulating film.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of an FBC memory device according to a first embodiment;

FIG. 2 is a cross-sectional view of the FBC memory device taken along a line 2-2 of FIG. 1;

FIG. 3 is a cross-sectional view of the FBC memory device taken along a line 3-3 of FIG. 1;

FIG. 4 is a cross-sectional view of the FBC memory device taken along a line 4-4 of FIG. 1;

FIG. 5 is a cross-sectional view of the FBC memory device taken along a line 5-5 of FIG. 1;

FIGS. 6A to 10B are cross-sectional views of the FBC memory device, showing a method of manufacturing the FBC memory device according to the first embodiment;

FIG. 11 is a cross-sectional view of an FBC memory device according to a second embodiment;

FIGS. 12A to 13B are cross-sectional views showing a method of manufacturing the FBC memory device according to the second embodiment;

FIG. 14 is a plan view of an FBC memory device according to a third embodiment;

FIG. 15 is a cross-sectional view of the FBC memory device taken along a line 13-13 of FIG. 14;

FIG. 16 is a cross-sectional view of the FBC memory device taken along a line 14-14 of FIG. 14;

FIG. 17 is a cross-sectional view of the FBC memory device taken along a line 15-15 of FIG. 14;

FIGS. 18A and 18B are cross-sectional views showing a method of manufacturing the FBC memory device according to the third embodiment;

FIGS. 19A and 19B are cross-sectional views showing a method of manufacturing the FBC memory device subsequent to FIGS. 18A and 18B;

FIG. 20 is a cross-sectional view of the FBC memory device taken along a line 18-18 of FIG. 19;

FIG. 21 is a cross-sectional view of the FBC memory device taken along a line 19-19 of FIG. 19;

FIG. 22 is a cross-sectional view of the FBC memory device subsequent to FIG. 20;

FIG. 23 is a cross-sectional view of the FBC memory device subsequent to FIG. 22;

FIG. 24 is a cross-sectional view of the FBC memory device subsequent to FIG. 21;

FIG. 25 is a plan view of the FBC memory device, showing the positional relationship between the first sidewall film 47 and the second sidewall film 80;

FIGS. 26A and 26B are cross-sectional views showing a method of manufacturing the FBC memory device according to the fourth embodiment;

FIGS. 27A and 27B are cross-sectional views showing a method of manufacturing the FBC memory device subsequent to FIGS. 26A and 26B;

FIG. 28 is a cross-sectional view of the FBC memory device taken along a line 26-26 of FIG. 27A;

FIG. 29 is a cross-sectional view of the FBC memory device taken along a line 27-27 of FIG. 27A;

FIG. 30 is a cross-sectional view of the FBC memory device subsequent to FIG. 28;

FIG. 31 is a cross-sectional view of the FBC memory device subsequent to FIG. 30;

FIG. 32 is a cross-sectional view of the FBC memory device subsequent to FIG. 29;

FIG. 33 is are cross-sectional views showing a manufacturing method of the FBC memory device according to a modification of the fourth embodiment;

FIG. 34 is a cross-sectional view of the FBC memory device subsequent to FIG. 33;

FIG. 35 is a cross-sectional view of the FBC memory device subsequent to FIG. 34;

FIG. 36 is a cross-sectional view of the FBC memory device subsequent to FIG. 35;

FIG. 37A is a cross-sectional view of the FBC memory device taken along a line 35A-35A of FIG. 36;

FIG. 37B is a cross-sectional view of the FBC memory device taken along a line 35B-35B of FIG. 36;

FIGS. 38A and 38B are cross-sectional views of the FBC memory device, showing the manufacturing method subsequent to FIGS. 37A and 37B, respectively;

FIG. 39 is a plan view of an FBC memory device according to a fifth embodiment;

FIG. 40 is a cross-sectional view of the FBC memory device taken along a line 40-40 of FIG. 39;

FIG. 41 is a cross-sectional view of the FBC memory device taken along a line 41-41 of FIG. 39;

FIG. 42 is a cross-sectional view of the FBC memory device taken along a line 42-42 of FIG. 39;

FIGS. 43A to 50 are cross-sectional views of the FBC memory device, showing a method of manufacturing the FBC memory device according to the fifth embodiment;

FIG. 51 is a cross-sectional view of the FBC memory device taken along a line 51-51 of FIG. 50;

FIG. 52 is a cross-sectional view of the FBC memory device taken along a line 52-52 of FIG. 50;

FIG. 53 is a cross-sectional view of the FBC memory device subsequent to FIG. 51; and

FIG. 54 is a cross-sectional view of the FBC memory device subsequent to FIG. 52.

Claims

1. A semiconductor memory device comprising: an insulating film;a semiconductor layer provided on the insulating film;a source layer and a drain layer formed on the semiconductor layer;a body region provided between the source layer and the drain layer, the body region being in an electrically floating state, accumulating or emitting charges for storing data, and including a first body part and a second body part, the first body part being smaller than the second body part in a thickness measured in a direction perpendicular to a surface of the insulating film;a gate insulating film provided on the first body part and the second body part; anda gate electrode provided on the gate insulating film.

2. The semiconductor memory device according to claim 1, wherein the source layer includes a first source part and a second source part, the first source part and the second source part differing in a thickness measured in a direction perpendicular to a surface of the insulating film, andthe drain layer includes a first drain part and a second drain part, the first drain part and the second drain part differing in a thickness measured in a direction perpendicular to a surface of the insulating film.

3. The semiconductor memory device according to claim 2, wherein the first source part is thinner than the second source part and is made of a silicide in contact with the insulating film, andthe first drain part is thinner than the second drain part and is made of a silicide in contact with the insulating film.

4. The semiconductor memory device according to claim 2, wherein the second source part is a multilayer including the semiconductor layer and a silicide layer formed on the semiconductor layer, andthe second drain part is a multilayer including the semiconductor layer and the silicide layer formed on the semiconductor layer.

5. The semiconductor memory device according to claim 3, wherein the second source part is a multilayer including the semiconductor layer and a silicide layer formed on the semiconductor layer, andthe second drain part is a multilayer including the semiconductor layer and the silicide layer formed on the semiconductor layer.

6. The semiconductor memory device according to claim 5, wherein the silicide layer is formed on a side surface of the semiconductor layer at a boundary between the first source part and the second source part, andthe silicide layer is formed on the side surface of the semiconductor layer at a boundary between the first drain part and the second drain part.

7. A semiconductor memory device comprising: an insulating film;a semiconductor layer provided on the insulating film;a source layer and a drain layer formed on the semiconductor layer;a body region provided between the source layer and the drain layer, the body region being in an electrically floating state, accumulating or emitting charges for storing data, and including a first body part and a second body part, the first body part and the second body part differing in width between the source layer and the drain layer;a gate insulating film provided on the first body part and the second body part; anda gate electrode provided on the gate insulating film.

8. The semiconductor memory device according to claim 7, wherein the first body part is a channel formation part in the body region;the second body part is an end portion of the body region in which a channel is not formed, and the second body part is wider than the first body part in width between the source layer and the drain layer.

9. The semiconductor memory device according to claim 7, wherein the first body part and the second body part are different in a thickness measured in a direction perpendicular to a surface of the insulating film.

10. The semiconductor memory device according to claim 7, wherein the source layer includes a first source part and a second source part, the first source part and the second source part differing in a thickness measured in a direction perpendicular to a surface of the insulating film, andthe drain layer includes a first drain part and a second drain part, the first drain part and the second drain part differing in a thickness measured in a direction perpendicular to a surface of the insulating film.

11. The semiconductor memory device according to claim 10, wherein the first source part is thinner than the second source part in a thickness measured in a direction perpendicular to a surface of the insulating film and is made of a silicide in contact with the insulating film, andthe first drain part is thinner than the second drain part in a thickness measured in a direction perpendicular to a surface of the insulating film and is made of a silicide in contact with the insulating film.

12. The semiconductor memory device according to claim 10, wherein the second source part is a multilayer including the semiconductor layer and a silicide layer formed on the semiconductor layer, andthe second drain part is a multilayer including the semiconductor layer and the silicide layer formed on the semiconductor layer.

13. The semiconductor memory device according to claim 11, wherein the second source part is a multilayer including the semiconductor layer and a silicide layer formed on the semiconductor layer, andthe second drain part is a multilayer including the semiconductor layer and the silicide layer formed on the semiconductor layer.

14. The semiconductor memory device according to claim 13, wherein the silicide layer is formed on a side surface of the semiconductor layer at a boundary between the first source part and the second source part, andthe silicide layer is formed on the side surface of the semiconductor layer at a boundary between the first drain part and the second drain part.

15. A manufacturing method of a semiconductor memory device, the semiconductor memory device including a body region provided between a drain layer and a source layer in an electrically floating state, the body region including a first body part and a second body part, the semiconductor memory device storing data according to a quantity of charges accumulated in the body region, the method comprising: preparing a substrate including a semiconductor layer provided on an insulating film;forming a first mask material on an element formation region of the semiconductor layer;removing the semiconductor layer of element isolation regions by using the first mask material as a mask;forming element isolations by filling the element isolation regions with an element isolation material;forming a second mask material covering the second body part of the body region between the element isolations;reducing a thickness of the first body part by using the second mask material as a mask, so that the first body part is smaller than the second body part in a thickness measured in a direction perpendicular to a surface of the insulating film.

16. The manufacturing method of the semiconductor memory device according to claim 15, further comprising: forming the gate insulating filmon the first body part using the second mask material as a mask.

17. The manufacturing method of the semiconductor memory device according to claim 15, wherein the second mask material does not cover a first source part of the source layer and a first drain part of the drain layer and covers a second source part of the source layer and a second drain part of the drain layer,when thinning the first body part, the first source part and the first drain part are also reduced in a thickness measured in a direction perpendicular to a surface of the insulating film, so that the first source part and the first drain part are thinner than the second source part and the second drain part,the method further comprises, after removing the second mask material, forming a silicide layer on the first source part, the second source part, the first drain part, and the second drain part.

18. The manufacturing method of the semiconductor memory device according to claim 17, wherein the silicide layer is formed on the insulating film in the first source part and the first drain part, and is stacked on the semiconductor layer in the second source part and the second drain part, andthe silicide layer is formed on a side surface of the semiconductor layer at a boundary between the first source part and the second source part, and is formed on the side surface of the semiconductor layer at a boundary between the first drain part and the second drain part.

19. A manufacturing method of a semiconductor memory device, the semiconductor memory device including a body region provided between a drain layer and a source layer in an electrically floating state, the body region including a first body part and a second body part, the drain layer including a first drain part and a second drain part, the source layer including a first source part and a second source part, the semiconductor memory device storing data according to a quantity of charges accumulated in the body region, the method comprising: preparing a substrate including a semiconductor layer provided on an insulating film;forming a first mask material on an element formation region of the semiconductor layer;anisotropically etching the semiconductor layer of element isolation regions by using the first mask material as a mask;forming element isolations by filling the element isolation regions with an element isolation material;forming a second mask material covering the second body part, the second source part and the second drain part between the element isolations;forming a gate insulating film on the first body part;forming a gate electrode on the gate insulating film, the gate electrode extending in a perpendicular direction to an extension direction of the second mask material;implanting impurities into the semiconductor layer using the second mask material as the mask, and forming the first source part and the first drain part;removing the second mask material;depositing a sidewall film;leaving the sidewall film on a side surface of the gate electrode by anisotropically etching the sidewall film; andimplanting the impurities into the semiconductor layer using the sidewall film as the mask, and forming the second source part and the second drain part.

20. The manufacturing method of the semiconductor memory device according to claim 19, further comprising, after forming of the second mask material and before forming of the gate insulating film, thinning the first body part using the second mask material as the mask.